isadmavar.h revision 1.14
1 /* $NetBSD: isadmavar.h,v 1.14 1998/06/28 06:59:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_ISA_ISADMAVAR_H_ 41 #define _DEV_ISA_ISADMAVAR_H_ 42 43 #define MAX_ISADMA 65536 44 45 #define DMAMODE_WRITE 0x00 46 #define DMAMODE_READ 0x01 47 #define DMAMODE_LOOP 0x02 48 #define DMAMODE_LOOPDEMAND 0x04 49 50 /* 51 * ISA DMA state. This structure is provided by the ISA chipset 52 * DMA entry points to the generic back-end functions that actually 53 * frob the controller. 54 */ 55 struct isa_dma_state { 56 struct device *ids_dev; /* associated device (for dv_xname) */ 57 bus_space_tag_t ids_bst; /* bus space tag for DMA controller */ 58 bus_space_handle_t ids_dma1h; /* handle for DMA controller #1 */ 59 bus_space_handle_t ids_dma2h; /* handle for DMA controller #2 */ 60 bus_space_handle_t ids_dmapgh; /* handle for DMA page registers */ 61 bus_dma_tag_t ids_dmat; /* DMA tag for DMA controller */ 62 bus_dmamap_t ids_dmamaps[8]; /* DMA maps for each channel */ 63 bus_size_t ids_dmalength[8]; /* size of DMA transfer per channel */ 64 int ids_drqmap; /* available DRQs (bitmap) */ 65 int ids_dmareads; /* state for isa_dmadone() (bitmap) */ 66 int ids_dmafinished; /* DMA completion state (bitmap) */ 67 int ids_masked; /* masked channels (bitmap) */ 68 int ids_frozen; /* `frozen' count */ 69 int ids_initialized; /* only initialize once... */ 70 }; 71 72 #define ISA_DMA_DRQ_ISFREE(state, drq) \ 73 (((state)->ids_drqmap & (1 << (drq))) == 0) 74 75 #define ISA_DMA_DRQ_ALLOC(state, drq) \ 76 (state)->ids_drqmap |= (1 << (drq)) 77 78 #define ISA_DMA_DRQ_FREE(state, drq) \ 79 (state)->ids_drqmap &= ~(1 << (drq)) 80 81 #define ISA_DMA_MASK_SET(state, drq) \ 82 (state)->ids_masked |= (1 << (drq)) 83 84 #define ISA_DMA_MASK_CLR(state, drq) \ 85 (state)->ids_masked &= ~(1 << (drq)) 86 87 /* 88 * Memory list used by _isa_malloc(). 89 */ 90 struct isa_mem { 91 struct isa_dma_state *ids; 92 int chan; 93 bus_size_t size; 94 bus_addr_t addr; 95 caddr_t kva; 96 struct isa_mem *next; 97 }; 98 99 #ifdef _KERNEL 100 struct proc; 101 102 void _isa_dmainit __P((struct isa_dma_state *, bus_space_tag_t, 103 bus_dma_tag_t, struct device *)); 104 105 int _isa_dmacascade __P((struct isa_dma_state *, int)); 106 107 int _isa_dmamap_create __P((struct isa_dma_state *, int, 108 bus_size_t, int)); 109 void _isa_dmamap_destroy __P((struct isa_dma_state *, int)); 110 111 int _isa_dmastart __P((struct isa_dma_state *, int, void *, bus_size_t, 112 struct proc *, int, int)); 113 void _isa_dmaabort __P((struct isa_dma_state *, int)); 114 bus_size_t _isa_dmacount __P((struct isa_dma_state *, int)); 115 int _isa_dmafinished __P((struct isa_dma_state *, int)); 116 void _isa_dmadone __P((struct isa_dma_state *, int)); 117 118 void _isa_dmafreeze __P((struct isa_dma_state *)); 119 void _isa_dmathaw __P((struct isa_dma_state *)); 120 121 int _isa_dmamem_alloc __P((struct isa_dma_state *, int, bus_size_t, 122 bus_addr_t *, int)); 123 void _isa_dmamem_free __P((struct isa_dma_state *, int, bus_addr_t, 124 bus_size_t)); 125 int _isa_dmamem_map __P((struct isa_dma_state *, int, bus_addr_t, 126 bus_size_t, caddr_t *, int)); 127 void _isa_dmamem_unmap __P((struct isa_dma_state *, int, caddr_t, 128 size_t)); 129 int _isa_dmamem_mmap __P((struct isa_dma_state *, int, bus_addr_t, 130 bus_size_t, int, int, int)); 131 132 int _isa_drq_isfree __P((struct isa_dma_state *, int)); 133 134 void *_isa_malloc __P((struct isa_dma_state *, int, size_t, int, int)); 135 void _isa_free __P((void *, int)); 136 int _isa_mappage __P((void *, int, int)); 137 #endif /* _KERNEL */ 138 139 #endif /* _DEV_ISA_ISADMAVAR_H_ */ 140
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