isadmavar.h revision 1.15
1 /* $NetBSD: isadmavar.h,v 1.15 1999/02/22 02:32:43 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_ISA_ISADMAVAR_H_ 41 #define _DEV_ISA_ISADMAVAR_H_ 42 43 #define MAX_ISADMA 65536 44 45 #define DMAMODE_WRITE 0x00 46 #define DMAMODE_READ 0x01 47 #define DMAMODE_SINGLE 0x00 48 #define DMAMODE_DEMAND 0x02 49 #define DMAMODE_LOOP 0x04 50 #define DMAMODE_LOOPDEMAND (DMAMODE_LOOP | DMAMODE_DEMAND) 51 52 /* 53 * ISA DMA state. This structure is provided by the ISA chipset 54 * DMA entry points to the generic back-end functions that actually 55 * frob the controller. 56 */ 57 struct isa_dma_state { 58 struct device *ids_dev; /* associated device (for dv_xname) */ 59 bus_space_tag_t ids_bst; /* bus space tag for DMA controller */ 60 bus_space_handle_t ids_dma1h; /* handle for DMA controller #1 */ 61 bus_space_handle_t ids_dma2h; /* handle for DMA controller #2 */ 62 bus_space_handle_t ids_dmapgh; /* handle for DMA page registers */ 63 bus_dma_tag_t ids_dmat; /* DMA tag for DMA controller */ 64 bus_dmamap_t ids_dmamaps[8]; /* DMA maps for each channel */ 65 bus_size_t ids_dmalength[8]; /* size of DMA transfer per channel */ 66 int ids_drqmap; /* available DRQs (bitmap) */ 67 int ids_dmareads; /* state for isa_dmadone() (bitmap) */ 68 int ids_dmafinished; /* DMA completion state (bitmap) */ 69 int ids_masked; /* masked channels (bitmap) */ 70 int ids_frozen; /* `frozen' count */ 71 int ids_initialized; /* only initialize once... */ 72 }; 73 74 #define ISA_DMA_DRQ_ISFREE(state, drq) \ 75 (((state)->ids_drqmap & (1 << (drq))) == 0) 76 77 #define ISA_DMA_DRQ_ALLOC(state, drq) \ 78 (state)->ids_drqmap |= (1 << (drq)) 79 80 #define ISA_DMA_DRQ_FREE(state, drq) \ 81 (state)->ids_drqmap &= ~(1 << (drq)) 82 83 #define ISA_DMA_MASK_SET(state, drq) \ 84 (state)->ids_masked |= (1 << (drq)) 85 86 #define ISA_DMA_MASK_CLR(state, drq) \ 87 (state)->ids_masked &= ~(1 << (drq)) 88 89 /* 90 * Memory list used by _isa_malloc(). 91 */ 92 struct isa_mem { 93 struct isa_dma_state *ids; 94 int chan; 95 bus_size_t size; 96 bus_addr_t addr; 97 caddr_t kva; 98 struct isa_mem *next; 99 }; 100 101 #ifdef _KERNEL 102 struct proc; 103 104 void _isa_dmainit __P((struct isa_dma_state *, bus_space_tag_t, 105 bus_dma_tag_t, struct device *)); 106 107 int _isa_dmacascade __P((struct isa_dma_state *, int)); 108 109 int _isa_dmamap_create __P((struct isa_dma_state *, int, 110 bus_size_t, int)); 111 void _isa_dmamap_destroy __P((struct isa_dma_state *, int)); 112 113 int _isa_dmastart __P((struct isa_dma_state *, int, void *, bus_size_t, 114 struct proc *, int, int)); 115 void _isa_dmaabort __P((struct isa_dma_state *, int)); 116 bus_size_t _isa_dmacount __P((struct isa_dma_state *, int)); 117 int _isa_dmafinished __P((struct isa_dma_state *, int)); 118 void _isa_dmadone __P((struct isa_dma_state *, int)); 119 120 void _isa_dmafreeze __P((struct isa_dma_state *)); 121 void _isa_dmathaw __P((struct isa_dma_state *)); 122 123 int _isa_dmamem_alloc __P((struct isa_dma_state *, int, bus_size_t, 124 bus_addr_t *, int)); 125 void _isa_dmamem_free __P((struct isa_dma_state *, int, bus_addr_t, 126 bus_size_t)); 127 int _isa_dmamem_map __P((struct isa_dma_state *, int, bus_addr_t, 128 bus_size_t, caddr_t *, int)); 129 void _isa_dmamem_unmap __P((struct isa_dma_state *, int, caddr_t, 130 size_t)); 131 int _isa_dmamem_mmap __P((struct isa_dma_state *, int, bus_addr_t, 132 bus_size_t, int, int, int)); 133 134 int _isa_drq_isfree __P((struct isa_dma_state *, int)); 135 136 void *_isa_malloc __P((struct isa_dma_state *, int, size_t, int, int)); 137 void _isa_free __P((void *, int)); 138 int _isa_mappage __P((void *, int, int)); 139 #endif /* _KERNEL */ 140 141 #endif /* _DEV_ISA_ISADMAVAR_H_ */ 142
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