isv.c revision 1.5
1 /* $NetBSD: isv.c,v 1.5 2014/03/16 05:20:28 dholland Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: isv.c,v 1.5 2014/03/16 05:20:28 dholland Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/conf.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <sys/bus.h> 44 45 #include <dev/isa/isareg.h> 46 #include <dev/isa/isavar.h> 47 48 #include <dev/isa/isvio.h> 49 50 #define ISV_CONTROL 0x0 /* control: write-only */ 51 #define ISV_CONTROL_MODE_MASK __BIT(0) 52 #define ISV_CONTROL_MODE_CAPTURE __SHIFTIN(0, ISV_CONTROL_MODE_MASK) 53 #define ISV_CONTROL_MODE_READ __SHIFTIN(1, ISV_CONTROL_MODE_MASK) 54 #define ISV_CONTROL_COUNTER_MASK __BIT(1) 55 #define ISV_CONTROL_COUNTER_RESET __SHIFTIN(1, ISV_CONTROL_COUNTER_MASK) 56 #define ISV_CONTROL_COUNTER_AUTOINC __SHIFTIN(0, ISV_CONTROL_COUNTER_MASK) 57 58 #define ISV_DATA ISV_CONTROL /* data: read-only */ 59 60 #define ISV_STATUS 0x2 /* status: read-only */ 61 #define ISV_STATUS_VIDEO_MASK __BIT(15) 62 #define ISV_STATUS_VIDEO_RETRACE __SHIFTIN(0, ISV_STATUS_VIDEO_MASK) 63 #define ISV_STATUS_VIDEO_WRITE __SHIFTIN(1, ISV_STATUS_VIDEO_MASK) 64 65 struct isv_regs { 66 bus_space_tag_t ir_bt; 67 bus_space_handle_t ir_bh; 68 }; 69 70 enum isv_state { 71 ISV_S_CAPTURE0 = 0 72 , ISV_S_CAPTURE1 = 1 73 , ISV_S_CAPTURE2 = 2 74 , ISV_S_RETRACE = 3 75 }; 76 77 struct isv_softc { 78 struct isv_regs sc_ir; 79 device_t sc_dev; 80 uint16_t *sc_frame; 81 int sc_speed; 82 }; 83 84 extern struct cfdriver isv_cd; 85 86 static dev_type_ioctl(isv_ioctl); 87 static dev_type_open(isv_open); 88 static dev_type_mmap(isv_mmap); 89 90 static int isv_capture(struct isv_softc *); 91 static int isv_match(device_t, cfdata_t, void *); 92 static void isv_attach(device_t, device_t, void *); 93 static int isv_detach(device_t, int); 94 static uint16_t isv_read(struct isv_regs *, bus_size_t); 95 static void isv_write(struct isv_regs *, bus_size_t, uint16_t); 96 static bool isv_retrace(struct isv_regs *); 97 static int isv_retrace_wait(struct isv_regs *, int *, 98 const struct timeval *); 99 static int isv_capture_wait(struct isv_regs *, int *, 100 const struct timeval *); 101 static bool isv_delta(int *, bool); 102 static int isv_probe(struct isv_regs *); 103 104 CFATTACH_DECL_NEW(isv_isa, sizeof(struct isv_softc), 105 isv_match, isv_attach, isv_detach, NULL); 106 107 const struct cdevsw isv_cdevsw = { 108 .d_open = isv_open, 109 .d_close = nullclose, 110 .d_read = noread, 111 .d_write = nowrite, 112 .d_ioctl = isv_ioctl, 113 .d_stop = nostop, 114 .d_tty = notty, 115 .d_poll = nopoll, 116 .d_mmap = isv_mmap, 117 .d_kqfilter = nokqfilter, 118 .d_flag = D_OTHER 119 }; 120 121 static uint16_t 122 isv_read(struct isv_regs *ir, bus_size_t reg) 123 { 124 return bus_space_read_2(ir->ir_bt, ir->ir_bh, reg); 125 } 126 127 static void 128 isv_write(struct isv_regs *ir, bus_size_t reg, uint16_t val) 129 { 130 bus_space_write_2(ir->ir_bt, ir->ir_bh, reg, val); 131 } 132 133 static bool 134 isv_retrace(struct isv_regs *ir) 135 { 136 uint16_t video; 137 138 video = isv_read(ir, ISV_STATUS) & ISV_STATUS_VIDEO_MASK; 139 return video == ISV_STATUS_VIDEO_RETRACE; 140 } 141 142 #define state_and_input(__state, __retrace) \ 143 (((__state) << 1) | ((__retrace) ? 1 : 0)) 144 145 static bool 146 isv_delta(int *state, bool retrace) 147 { 148 bool transition = false; 149 150 switch (state_and_input(*state, retrace)) { 151 case state_and_input(ISV_S_CAPTURE0, false): 152 case state_and_input(ISV_S_RETRACE, true): 153 break; 154 case state_and_input(ISV_S_CAPTURE2, true): 155 transition = true; 156 /*FALLTHROUGH*/ 157 case state_and_input(ISV_S_CAPTURE1, true): 158 case state_and_input(ISV_S_CAPTURE0, true): 159 (*state)++; 160 break; 161 case state_and_input(ISV_S_RETRACE, false): 162 transition = true; 163 /*FALLTHROUGH*/ 164 case state_and_input(ISV_S_CAPTURE2, false): 165 case state_and_input(ISV_S_CAPTURE1, false): 166 *state = ISV_S_CAPTURE0; 167 break; 168 } 169 return transition; 170 } 171 172 static int 173 isv_probe(struct isv_regs *ir) 174 { 175 int state, transitions; 176 struct timeval end, now, 177 wait = {.tv_sec = 0, .tv_usec = 1000000 * 4 / 30}; 178 179 aprint_debug("%s: resetting\n", __func__); 180 isv_write(ir, ISV_CONTROL, 181 ISV_CONTROL_MODE_CAPTURE|ISV_CONTROL_COUNTER_AUTOINC); 182 183 aprint_debug("%s: waiting\n", __func__); 184 185 microtime(&now); 186 timeradd(&now, &wait, &end); 187 188 state = transitions = 0; 189 190 do { 191 if (isv_delta(&state, isv_retrace(ir))) 192 transitions++; 193 194 if (state == ISV_S_CAPTURE0 || state == ISV_S_RETRACE) 195 microtime(&now); 196 } while (timercmp(&now, &end, <)); 197 198 aprint_debug("%s: %d transitions\n", __func__, transitions); 199 200 return transitions >= 4 && transitions <= 10; 201 } 202 203 static int 204 isv_match(device_t parent, cfdata_t match, void *aux) 205 { 206 struct isv_regs ir; 207 struct isa_attach_args *ia = aux; 208 int rv; 209 210 /* Must supply an address */ 211 if (ia->ia_nio < 1 || ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 212 return 0; 213 214 ir.ir_bt = ia->ia_iot; 215 216 if (bus_space_map(ir.ir_bt, ia->ia_io[0].ir_addr, 8, 0, &ir.ir_bh)) 217 return 0; 218 219 rv = isv_probe(&ir); 220 221 bus_space_unmap(ir.ir_bt, ir.ir_bh, 8); 222 223 if (rv) { 224 ia->ia_nio = 1; 225 ia->ia_io[0].ir_size = 8; 226 227 ia->ia_niomem = 0; 228 ia->ia_nirq = 0; 229 ia->ia_ndrq = 0; 230 } 231 232 return rv; 233 } 234 235 236 static void 237 isv_attach(device_t parent, device_t self, void *aux) 238 { 239 struct isv_softc *sc = device_private(self); 240 struct isv_regs *ir = &sc->sc_ir; 241 struct isa_attach_args *ia = aux; 242 243 ir->ir_bt = ia->ia_iot; 244 245 if (bus_space_map(ir->ir_bt, ia->ia_io[0].ir_addr, 8, 0, &ir->ir_bh)) { 246 aprint_error(": can't map i/o space\n"); 247 return; 248 } 249 250 /* Bus-independent attachment */ 251 sc->sc_dev = self; 252 253 aprint_normal(": IDEC Supervision/16\n"); 254 255 /* TBD */ 256 } 257 258 int 259 isv_open(dev_t dev, int flag, int devtype, lwp_t *l) 260 { 261 vaddr_t va; 262 struct isv_softc *sc = device_lookup_private(&isv_cd, minor(dev)); 263 264 if (sc == NULL) 265 return ENXIO; 266 267 if (sc->sc_frame != NULL) 268 return 0; 269 270 if ((va = uvm_km_alloc(kernel_map, ISV_WIDTH * ISV_LINES, PAGE_SIZE, 271 UVM_KMF_WIRED|UVM_KMF_ZERO|UVM_KMF_CANFAIL|UVM_KMF_WAITVA)) == 0) 272 return ENOMEM; 273 274 sc->sc_frame = (uint16_t *)(void *)va; 275 return 0; 276 } 277 278 /* wait for retrace */ 279 static int 280 isv_retrace_wait(struct isv_regs *ir, int *state, const struct timeval *end) 281 { 282 struct timeval now; 283 284 for (;;) { 285 if (!isv_delta(state, isv_retrace(ir))) { 286 microtime(&now); 287 continue; 288 } 289 if (*state == ISV_S_RETRACE) 290 break; 291 if (*state != ISV_S_CAPTURE0) 292 continue; 293 294 microtime(&now); 295 if (timercmp(&now, end, >=)) 296 return EIO; 297 } 298 return 0; 299 } 300 301 /* wait for capture mode */ 302 static int 303 isv_capture_wait(struct isv_regs *ir, int *state, const struct timeval *end) 304 { 305 struct timeval now; 306 307 for (;;) { 308 if (!isv_delta(state, isv_retrace(ir))) { 309 microtime(&now); 310 continue; 311 } 312 if (*state != ISV_S_RETRACE) 313 break; 314 315 microtime(&now); 316 if (timercmp(&now, end, >=)) 317 return EIO; 318 } 319 return 0; 320 } 321 322 323 static int 324 isv_capture(struct isv_softc *sc) 325 { 326 int speed; 327 uint16_t discard; 328 int rc, state = ISV_S_CAPTURE0; 329 struct timeval diff, end, start, stop; 330 static const struct timeval wait = {.tv_sec = 0, .tv_usec = 200000}; 331 struct isv_regs *ir = &sc->sc_ir; 332 333 if (sc->sc_frame == NULL) 334 return EAGAIN; 335 336 microtime(&start); 337 338 timeradd(&start, &wait, &end); 339 340 speed = sc->sc_speed; 341 sc->sc_speed = 0; 342 343 if (speed < 1 && (rc = isv_retrace_wait(ir, &state, &end)) != 0) 344 return rc; 345 346 if (speed < 2 && (rc = isv_capture_wait(ir, &state, &end)) != 0) 347 return rc; 348 349 if ((rc = isv_retrace_wait(ir, &state, &end)) != 0) 350 return rc; 351 352 microtime(&stop); 353 354 timersub(&stop, &start, &diff); 355 356 aprint_debug_dev(sc->sc_dev, "%ssync in %" PRId64 ".%06d seconds\n", 357 (speed < 1) ? "" : ((speed < 2) ? "faster " : "fastest "), 358 diff.tv_sec, diff.tv_usec); 359 360 microtime(&start); 361 362 /* enter read mode, then toggle counter mode, 363 * autoinc -> reset -> autoinc, so that we start reading 364 * at the top of the frame. 365 */ 366 isv_write(ir, ISV_CONTROL, 367 ISV_CONTROL_MODE_READ|ISV_CONTROL_COUNTER_AUTOINC); 368 isv_write(ir, ISV_CONTROL, 369 ISV_CONTROL_MODE_READ|ISV_CONTROL_COUNTER_RESET); 370 isv_write(ir, ISV_CONTROL, 371 ISV_CONTROL_MODE_READ|ISV_CONTROL_COUNTER_AUTOINC); 372 /* read one dummy word to prime the state machine on the 373 * image capture board 374 */ 375 discard = isv_read(ir, ISV_DATA); 376 bus_space_read_multi_stream_2(ir->ir_bt, ir->ir_bh, ISV_DATA, 377 sc->sc_frame, ISV_WIDTH * ISV_LINES / 2); 378 379 /* restore to initial conditions */ 380 isv_write(ir, ISV_CONTROL, 381 ISV_CONTROL_MODE_CAPTURE|ISV_CONTROL_COUNTER_AUTOINC); 382 383 microtime(&stop); 384 385 timersub(&stop, &start, &diff); 386 387 aprint_debug_dev(sc->sc_dev, "read in %" PRId64 ".%06d seconds\n", 388 diff.tv_sec, diff.tv_usec); 389 390 state = 0; 391 392 if (isv_retrace_wait(ir, &state, &end) != 0) 393 return 0; 394 sc->sc_speed++; 395 396 if (isv_capture_wait(ir, &state, &end) != 0) 397 return 0; 398 sc->sc_speed++; 399 400 return 0; 401 } 402 403 int 404 isv_ioctl(dev_t dev, u_long cmd, void *data, int flag, lwp_t *l) 405 { 406 struct isv_cmd ic; 407 struct isv_softc *sc = device_lookup_private(&isv_cd, minor(dev)); 408 409 if (cmd != ISV_CMD) 410 return ENOTTY; 411 412 memcpy(&ic, data, sizeof(ic)); 413 414 if (ic.c_cmd != ISV_CMD_READ) 415 return EINVAL; 416 417 ic.c_frameno = 0; 418 419 return isv_capture(sc); 420 } 421 422 paddr_t 423 isv_mmap(dev_t dev, off_t offset, int prot) 424 { 425 struct isv_softc *sc = device_lookup_private(&isv_cd, minor(dev)); 426 paddr_t pa; 427 428 if ((prot & ~(VM_PROT_READ)) != 0) 429 return -1; 430 431 if (sc->sc_frame == NULL) 432 return -1; 433 434 if (offset >= ISV_WIDTH * ISV_LINES) 435 return -1; 436 437 if (!pmap_extract(pmap_kernel(), (vaddr_t)&sc->sc_frame[offset/2], &pa)) 438 return -1; 439 440 return atop(pa); 441 } 442 443 static int 444 isv_detach(device_t self, int flags) 445 { 446 struct isv_softc *sc = device_private(self); 447 struct isv_regs *ir = &sc->sc_ir; 448 449 if (sc->sc_frame != NULL) { 450 uvm_km_free(kernel_map, (vaddr_t)sc->sc_frame, 451 ISV_WIDTH * ISV_LINES, UVM_KMF_WIRED); 452 } 453 bus_space_unmap(ir->ir_bt, ir->ir_bh, 8); 454 return 0; 455 } 456
Indexes created Tue Sep 23 14:10:03 GMT 2025