itesio_isavar.h revision 1.1 1 1.1 xtraeme /* $NetBSD: itesio_isavar.h,v 1.1 2007/11/15 12:53:43 xtraeme Exp $ */
2 1.1 xtraeme /* $OpenBSD: itvar.h,v 1.2 2003/11/05 20:57:10 grange Exp $ */
3 1.1 xtraeme
4 1.1 xtraeme /*
5 1.1 xtraeme * Copyright (c) 2006-2007 Juan Romero Pardines <juan (at) xtrarom.org>
6 1.1 xtraeme * Copyright (c) 2003 Julien Bordet <zejames (at) greyhats.org>
7 1.1 xtraeme * All rights reserved.
8 1.1 xtraeme *
9 1.1 xtraeme * Redistribution and use in source and binary forms, with or without
10 1.1 xtraeme * modification, are permitted provided that the following conditions
11 1.1 xtraeme * are met:
12 1.1 xtraeme * 1. Redistributions of source code must retain the above copyright
13 1.1 xtraeme * notice, this list of conditions and the following disclaimer.
14 1.1 xtraeme * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 xtraeme * notice, this list of conditions and the following disclaimer in the
16 1.1 xtraeme * documentation and/or other materials provided with the distribution.
17 1.1 xtraeme *
18 1.1 xtraeme * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 xtraeme * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITD TO, THE IMPLIED WARRANTIES
20 1.1 xtraeme * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 xtraeme * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 xtraeme * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 1.1 xtraeme * NOT LIMITD TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 1.1 xtraeme * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 1.1 xtraeme * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 1.1 xtraeme * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 1.1 xtraeme * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 1.1 xtraeme */
29 1.1 xtraeme
30 1.1 xtraeme #ifndef _DEV_ISA_ITVAR_H
31 1.1 xtraeme #define _DEV_ISA_ITVAR_H
32 1.1 xtraeme
33 1.1 xtraeme #define IT_NUM_SENSORS 15
34 1.1 xtraeme
35 1.1 xtraeme /* Super I/O Configuration Registers */
36 1.1 xtraeme #define ITESIO_ADDR 0 /* Address Port = 0x2e */
37 1.1 xtraeme #define ITESIO_DATA 1 /* Data Port = 0x2f */
38 1.1 xtraeme
39 1.1 xtraeme #define ITESIO_LDNSEL 0x07 /* Logical Device Number Selection */
40 1.1 xtraeme
41 1.1 xtraeme #define ITESIO_EC_LDN 0x04 /* EC Logical Device Number */
42 1.1 xtraeme #define ITESIO_EC_MSB 0x60 /* EC Base Address (MSB) */
43 1.1 xtraeme #define ITESIO_EC_LSB 0x61 /* EC Base Address (LSB) */
44 1.1 xtraeme
45 1.1 xtraeme #define ITESIO_CHIPID1 0x20 /* Chip ID 1 */
46 1.1 xtraeme #define ITESIO_CHIPID2 0x21 /* Chip ID 2 */
47 1.1 xtraeme #define ITESIO_DEVREV 0x22 /* Device Revision */
48 1.1 xtraeme
49 1.1 xtraeme #define ITESIO_ID8705 0x8705
50 1.1 xtraeme #define ITESIO_ID8712 0x8712
51 1.1 xtraeme #define ITESIO_ID8716 0x8716
52 1.1 xtraeme #define ITESIO_ID8718 0x8718
53 1.1 xtraeme
54 1.1 xtraeme /*
55 1.1 xtraeme * Control registers for the Environmental Controller, relative
56 1.1 xtraeme * to the Base Address Register.
57 1.1 xtraeme */
58 1.1 xtraeme #define ITESIO_EC_ADDR 0x05
59 1.1 xtraeme #define ITESIO_EC_DATA 0x06
60 1.1 xtraeme
61 1.1 xtraeme /* Data registers */
62 1.1 xtraeme #define ITESIO_EC_CONFIG 0x00
63 1.1 xtraeme #define ITESIO_EC_ISR1 0x01
64 1.1 xtraeme #define ITESIO_EC_ISR2 0x02
65 1.1 xtraeme #define ITESIO_EC_ISR3 0x03
66 1.1 xtraeme #define ITESIO_EC_SMI1 0x04
67 1.1 xtraeme #define ITESIO_EC_SMI2 0x05
68 1.1 xtraeme #define ITESIO_EC_SMI3 0x06
69 1.1 xtraeme #define ITESIO_EC_IMR1 0x07
70 1.1 xtraeme #define ITESIO_EC_IMR2 0x08
71 1.1 xtraeme #define ITESIO_EC_IMR3 0x09
72 1.1 xtraeme #define ITESIO_EC_VID 0x0a
73 1.1 xtraeme #define ITESIO_EC_FAN_TDR 0x0b /* Fan Tachometer Divisor Register */
74 1.1 xtraeme #define ITESIO_EC_FAN16_CER 0x0c /* Fan Tachometer 16-bit Counter Enable Register */
75 1.1 xtraeme
76 1.1 xtraeme #define ITESIO_EC_VOLTENABLE 0x50
77 1.1 xtraeme #define ITESIO_EC_TEMPENABLE 0x51
78 1.1 xtraeme
79 1.1 xtraeme #define ITESIO_EC_FANMINBASE 0x10
80 1.1 xtraeme #define ITESIO_EC_FANENABLE 0x13
81 1.1 xtraeme
82 1.1 xtraeme #define ITESIO_EC_SENSORFANBASE 0x0d /* Fan from 0x0d to 0x0f */
83 1.1 xtraeme #define ITESIO_EC_SENSORFANEXTBASE 0x18 /* Fan (MSB) from 0x18 to 0x1A */
84 1.1 xtraeme #define ITESIO_EC_SENSORVOLTBASE 0x20 /* Voltage from 0x20 to 0x28 */
85 1.1 xtraeme #define ITESIO_EC_SENSORTEMPBASE 0x29 /* Temperature from 0x29 to 0x2b */
86 1.1 xtraeme
87 1.1 xtraeme #define ITESIO_EC_VIN0 0x20
88 1.1 xtraeme #define ITESIO_EC_VIN1 0x21
89 1.1 xtraeme #define ITESIO_EC_VIN2 0x22
90 1.1 xtraeme #define ITESIO_EC_VIN3 0x23
91 1.1 xtraeme #define ITESIO_EC_VIN4 0x24
92 1.1 xtraeme #define ITESIO_EC_VIN5 0x25
93 1.1 xtraeme #define ITESIO_EC_VIN6 0x26
94 1.1 xtraeme #define ITESIO_EC_VIN7 0x27
95 1.1 xtraeme #define ITESIO_EC_VBAT 0x28
96 1.1 xtraeme
97 1.1 xtraeme #define ITESIO_EC_UPDATEVBAT 0x40 /* Update VBAT voltage reading */
98 1.1 xtraeme #define ITESIO_EC_BEEPEER 0x5c /* Beep Event Enable Register */
99 1.1 xtraeme
100 1.1 xtraeme /* High and Low limits for voltages */
101 1.1 xtraeme #define ITESIO_EC_VIN0_HIGH_LIMIT 0x30
102 1.1 xtraeme #define ITESIO_EC_VIN0_LOW_LIMIT 0x31
103 1.1 xtraeme #define ITESIO_EC_VIN1_HIGH_LIMIT 0x32
104 1.1 xtraeme #define ITESIO_EC_VIN1_LOW_LIMIT 0x33
105 1.1 xtraeme #define ITESIO_EC_VIN2_HIGH_LIMIT 0x34
106 1.1 xtraeme #define ITESIO_EC_VIN2_LOW_LIMIT 0x35
107 1.1 xtraeme #define ITESIO_EC_VIN3_HIGH_LIMIT 0x36
108 1.1 xtraeme #define ITESIO_EC_VIN3_LOW_LIMIT 0x37
109 1.1 xtraeme #define ITESIO_EC_VIN4_HIGH_LIMIT 0x38
110 1.1 xtraeme #define ITESIO_EC_VIN4_LOW_LIMIT 0x39
111 1.1 xtraeme #define ITESIO_EC_VIN5_HIGH_LIMIT 0x3a
112 1.1 xtraeme #define ITESIO_EC_VIN5_LOW_LIMIT 0x3b
113 1.1 xtraeme #define ITESIO_EC_VIN6_HIGH_LIMIT 0x3c
114 1.1 xtraeme #define ITESIO_EC_VIN6_LOW_LIMIT 0x3d
115 1.1 xtraeme #define ITESIO_EC_VIN7_HIGH_LIMIT 0x3e
116 1.1 xtraeme #define ITESIO_EC_VIN7_LOW_LIMIT 0x3f
117 1.1 xtraeme
118 1.1 xtraeme /* High and Low limits for temperatures */
119 1.1 xtraeme #define ITESIO_EC_TEMP0_HIGH_LIMIT 0x40
120 1.1 xtraeme #define ITESIO_EC_TEMP0_LOW_LIMIT 0x41
121 1.1 xtraeme #define ITESIO_EC_TEMP1_HIGH_LIMIT 0x42
122 1.1 xtraeme #define ITESIO_EC_TEMP1_LOW_LIMIT 0x43
123 1.1 xtraeme #define ITESIO_EC_TEMP2_HIGH_LIMIT 0x44
124 1.1 xtraeme #define ITESIO_EC_TEMP2_LOW_LIMIT 0x45
125 1.1 xtraeme
126 1.1 xtraeme #define ITESIO_EC_VREF (4096) /* Vref = 4.096 V */
127 1.1 xtraeme
128 1.1 xtraeme struct itesio_softc {
129 1.1 xtraeme bus_space_tag_t sc_iot;
130 1.1 xtraeme bus_space_handle_t sc_ioh;
131 1.1 xtraeme
132 1.1 xtraeme struct sysmon_envsys sc_sysmon;
133 1.1 xtraeme envsys_data_t sc_data[IT_NUM_SENSORS];
134 1.1 xtraeme
135 1.1 xtraeme uint16_t sc_hwmon_baseaddr;
136 1.1 xtraeme bool sc_hwmon_mapped;
137 1.1 xtraeme bool sc_hwmon_enabled;
138 1.1 xtraeme
139 1.1 xtraeme uint16_t sc_chipid;
140 1.1 xtraeme uint8_t sc_devrev;
141 1.1 xtraeme };
142 1.1 xtraeme
143 1.1 xtraeme #endif /* _DEV_ISA_ITVAR_H_ */
144