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itesio_isavar.h revision 1.6
      1  1.6  xtraeme /*	$NetBSD: itesio_isavar.h,v 1.6 2008/04/26 19:01:53 xtraeme Exp $	*/
      2  1.1  xtraeme /*	$OpenBSD: itvar.h,v 1.2 2003/11/05 20:57:10 grange Exp $	*/
      3  1.1  xtraeme 
      4  1.1  xtraeme /*
      5  1.5  xtraeme  * Copyright (c) 2006-2007 Juan Romero Pardines <xtraeme (at) netbsd.org>
      6  1.1  xtraeme  * Copyright (c) 2003 Julien Bordet <zejames (at) greyhats.org>
      7  1.1  xtraeme  * All rights reserved.
      8  1.1  xtraeme  *
      9  1.1  xtraeme  * Redistribution and use in source and binary forms, with or without
     10  1.1  xtraeme  * modification, are permitted provided that the following conditions
     11  1.1  xtraeme  * are met:
     12  1.1  xtraeme  * 1. Redistributions of source code must retain the above copyright
     13  1.1  xtraeme  *    notice, this list of conditions and the following disclaimer.
     14  1.1  xtraeme  * 2. Redistributions in binary form must reproduce the above copyright
     15  1.1  xtraeme  *    notice, this list of conditions and the following disclaimer in the
     16  1.1  xtraeme  *    documentation and/or other materials provided with the distribution.
     17  1.1  xtraeme  *
     18  1.1  xtraeme  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  1.1  xtraeme  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITD TO, THE IMPLIED WARRANTIES
     20  1.1  xtraeme  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  1.1  xtraeme  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22  1.1  xtraeme  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     23  1.1  xtraeme  * NOT LIMITD TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     24  1.1  xtraeme  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     25  1.1  xtraeme  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     26  1.1  xtraeme  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     27  1.1  xtraeme  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28  1.1  xtraeme  */
     29  1.1  xtraeme 
     30  1.2  xtraeme #ifndef _DEV_ISA_ITESIO_ISAVAR_H
     31  1.2  xtraeme #define _DEV_ISA_ITESIO_ISAVAR_H
     32  1.1  xtraeme 
     33  1.1  xtraeme #define IT_NUM_SENSORS	15
     34  1.1  xtraeme 
     35  1.1  xtraeme /* Super I/O Configuration Registers */
     36  1.1  xtraeme #define ITESIO_ADDR	0	/* Address Port = 0x2e */
     37  1.1  xtraeme #define ITESIO_DATA	1	/* Data Port = 0x2f */
     38  1.1  xtraeme 
     39  1.1  xtraeme #define ITESIO_LDNSEL	0x07	/* Logical Device Number Selection */
     40  1.1  xtraeme 
     41  1.1  xtraeme #define ITESIO_EC_LDN	0x04	/* EC Logical Device Number */
     42  1.1  xtraeme #define ITESIO_EC_MSB	0x60	/* EC Base Address (MSB) */
     43  1.1  xtraeme #define ITESIO_EC_LSB	0x61	/* EC Base Address (LSB) */
     44  1.1  xtraeme 
     45  1.4  xtraeme #define ITESIO_WDT_LDN	0x07	/* Watchdog Logical Device Number */
     46  1.4  xtraeme #define ITESIO_WDT_CTL	0x71	/* Watchdog Control Register */
     47  1.4  xtraeme #define ITESIO_WDT_CNF	0x72	/* Watchdog Configuration Register */
     48  1.4  xtraeme #define   ITESIO_WDT_CNF_SECS	(1<<7)	/* Use seconds for the timer */
     49  1.4  xtraeme #define   ITESIO_WDT_CNF_KRST	(1<<6)	/* Enable KRST */
     50  1.4  xtraeme #define   ITESIO_WDT_CNF_PWROK	(1<<4)	/* Enable PWROK */
     51  1.4  xtraeme #define ITESIO_WDT_TMO_LSB	0x73	/* Watchdog Timeout Value LSB */
     52  1.4  xtraeme #define ITESIO_WDT_TMO_MSB	0x74	/* Watchdog Timeout Value MSB */
     53  1.4  xtraeme 
     54  1.4  xtraeme #define ITESIO_WDT_MAXTIMO	0xffff	/* either seconds or minutes */
     55  1.4  xtraeme 
     56  1.1  xtraeme #define ITESIO_CHIPID1	0x20	/* Chip ID 1 */
     57  1.1  xtraeme #define ITESIO_CHIPID2	0x21	/* Chip ID 2 */
     58  1.1  xtraeme #define ITESIO_DEVREV	0x22	/* Device Revision */
     59  1.1  xtraeme 
     60  1.1  xtraeme #define ITESIO_ID8705	0x8705
     61  1.1  xtraeme #define ITESIO_ID8712	0x8712
     62  1.1  xtraeme #define ITESIO_ID8716	0x8716
     63  1.1  xtraeme #define ITESIO_ID8718	0x8718
     64  1.6  xtraeme #define ITESIO_ID8726	0x8726
     65  1.1  xtraeme 
     66  1.1  xtraeme /*
     67  1.1  xtraeme  * Control registers for the Environmental Controller, relative
     68  1.1  xtraeme  * to the Base Address Register.
     69  1.1  xtraeme  */
     70  1.1  xtraeme #define ITESIO_EC_ADDR 	0x05
     71  1.1  xtraeme #define ITESIO_EC_DATA 	0x06
     72  1.1  xtraeme 
     73  1.1  xtraeme /* Data registers */
     74  1.1  xtraeme #define ITESIO_EC_CONFIG 	0x00
     75  1.1  xtraeme #define ITESIO_EC_ISR1 		0x01
     76  1.1  xtraeme #define ITESIO_EC_ISR2 		0x02
     77  1.1  xtraeme #define ITESIO_EC_ISR3 		0x03
     78  1.1  xtraeme #define ITESIO_EC_SMI1 		0x04
     79  1.1  xtraeme #define ITESIO_EC_SMI2 		0x05
     80  1.1  xtraeme #define ITESIO_EC_SMI3 		0x06
     81  1.1  xtraeme #define ITESIO_EC_IMR1 		0x07
     82  1.1  xtraeme #define ITESIO_EC_IMR2 		0x08
     83  1.1  xtraeme #define ITESIO_EC_IMR3 		0x09
     84  1.1  xtraeme #define ITESIO_EC_VID 		0x0a
     85  1.1  xtraeme #define ITESIO_EC_FAN_TDR 	0x0b	/* Fan Tachometer Divisor Register */
     86  1.1  xtraeme #define ITESIO_EC_FAN16_CER 	0x0c	/* Fan Tachometer 16-bit Counter Enable Register */
     87  1.1  xtraeme 
     88  1.1  xtraeme #define ITESIO_EC_VOLTENABLE 	0x50
     89  1.1  xtraeme #define ITESIO_EC_TEMPENABLE 	0x51
     90  1.1  xtraeme 
     91  1.1  xtraeme #define ITESIO_EC_FANMINBASE	0x10
     92  1.1  xtraeme #define ITESIO_EC_FANENABLE	0x13
     93  1.1  xtraeme 
     94  1.4  xtraeme #define ITESIO_EC_SENSORFANBASE 	0x0d	/* Fan from 0x0d to 0x0f */
     95  1.1  xtraeme #define ITESIO_EC_SENSORFANEXTBASE 	0x18 	/* Fan (MSB) from 0x18 to 0x1A */
     96  1.1  xtraeme #define ITESIO_EC_SENSORVOLTBASE 	0x20 	/* Voltage from 0x20 to 0x28 */
     97  1.1  xtraeme #define ITESIO_EC_SENSORTEMPBASE 	0x29 	/* Temperature from 0x29 to 0x2b */
     98  1.1  xtraeme 
     99  1.1  xtraeme #define ITESIO_EC_VIN0 	0x20
    100  1.1  xtraeme #define ITESIO_EC_VIN1 	0x21
    101  1.1  xtraeme #define ITESIO_EC_VIN2 	0x22
    102  1.1  xtraeme #define ITESIO_EC_VIN3 	0x23
    103  1.1  xtraeme #define ITESIO_EC_VIN4 	0x24
    104  1.1  xtraeme #define ITESIO_EC_VIN5 	0x25
    105  1.1  xtraeme #define ITESIO_EC_VIN6 	0x26
    106  1.1  xtraeme #define ITESIO_EC_VIN7 	0x27
    107  1.1  xtraeme #define ITESIO_EC_VBAT 	0x28
    108  1.1  xtraeme 
    109  1.1  xtraeme #define ITESIO_EC_UPDATEVBAT 	0x40 	/* Update VBAT voltage reading */
    110  1.1  xtraeme #define ITESIO_EC_BEEPEER 	0x5c	/* Beep Event Enable Register */
    111  1.1  xtraeme 
    112  1.1  xtraeme /* High and Low limits for voltages */
    113  1.1  xtraeme #define ITESIO_EC_VIN0_HIGH_LIMIT 	0x30
    114  1.1  xtraeme #define ITESIO_EC_VIN0_LOW_LIMIT 	0x31
    115  1.1  xtraeme #define ITESIO_EC_VIN1_HIGH_LIMIT 	0x32
    116  1.1  xtraeme #define ITESIO_EC_VIN1_LOW_LIMIT 	0x33
    117  1.1  xtraeme #define ITESIO_EC_VIN2_HIGH_LIMIT 	0x34
    118  1.1  xtraeme #define ITESIO_EC_VIN2_LOW_LIMIT 	0x35
    119  1.1  xtraeme #define ITESIO_EC_VIN3_HIGH_LIMIT	0x36
    120  1.1  xtraeme #define ITESIO_EC_VIN3_LOW_LIMIT 	0x37
    121  1.1  xtraeme #define ITESIO_EC_VIN4_HIGH_LIMIT 	0x38
    122  1.1  xtraeme #define ITESIO_EC_VIN4_LOW_LIMIT 	0x39
    123  1.1  xtraeme #define ITESIO_EC_VIN5_HIGH_LIMIT 	0x3a
    124  1.1  xtraeme #define ITESIO_EC_VIN5_LOW_LIMIT 	0x3b
    125  1.1  xtraeme #define ITESIO_EC_VIN6_HIGH_LIMIT 	0x3c
    126  1.1  xtraeme #define ITESIO_EC_VIN6_LOW_LIMIT 	0x3d
    127  1.1  xtraeme #define ITESIO_EC_VIN7_HIGH_LIMIT 	0x3e
    128  1.1  xtraeme #define ITESIO_EC_VIN7_LOW_LIMIT 	0x3f
    129  1.1  xtraeme 
    130  1.1  xtraeme /* High and Low limits for temperatures */
    131  1.1  xtraeme #define ITESIO_EC_TEMP0_HIGH_LIMIT	0x40
    132  1.1  xtraeme #define ITESIO_EC_TEMP0_LOW_LIMIT	0x41
    133  1.1  xtraeme #define ITESIO_EC_TEMP1_HIGH_LIMIT	0x42
    134  1.1  xtraeme #define ITESIO_EC_TEMP1_LOW_LIMIT	0x43
    135  1.1  xtraeme #define ITESIO_EC_TEMP2_HIGH_LIMIT	0x44
    136  1.1  xtraeme #define ITESIO_EC_TEMP2_LOW_LIMIT	0x45
    137  1.1  xtraeme 
    138  1.1  xtraeme #define ITESIO_EC_VREF			(4096) /* Vref = 4.096 V */
    139  1.1  xtraeme 
    140  1.1  xtraeme struct itesio_softc {
    141  1.4  xtraeme 	bus_space_tag_t 	sc_iot;
    142  1.4  xtraeme 	bus_space_handle_t 	sc_ioh;
    143  1.4  xtraeme 
    144  1.4  xtraeme 	bus_space_tag_t		sc_ec_iot;
    145  1.4  xtraeme 	bus_space_handle_t	sc_ec_ioh;
    146  1.1  xtraeme 
    147  1.4  xtraeme 	struct sysmon_wdog	sc_smw;
    148  1.4  xtraeme 	struct sysmon_envsys 	*sc_sme;
    149  1.4  xtraeme 	envsys_data_t 		sc_sensor[IT_NUM_SENSORS];
    150  1.1  xtraeme 
    151  1.4  xtraeme 	uint16_t 		sc_hwmon_baseaddr;
    152  1.4  xtraeme 	bool 			sc_hwmon_mapped;
    153  1.4  xtraeme 	bool 			sc_hwmon_enabled;
    154  1.4  xtraeme 	bool 			sc_wdt_enabled;
    155  1.1  xtraeme 
    156  1.4  xtraeme 	uint16_t 		sc_chipid;
    157  1.4  xtraeme 	uint8_t 		sc_devrev;
    158  1.1  xtraeme };
    159  1.1  xtraeme 
    160  1.2  xtraeme #endif /* _DEV_ISA_ITSIO_ISAVAR_H_ */
    161