nct.c revision 1.1
1 /* $NetBSD: nct.c,v 1.1 2019/10/25 17:39:57 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Nuvoton NCT5104D 34 * 35 * - GPIO: full support. 36 * - Watchdog: no support. Watchdog uses GPIO pins. 37 * - UARTS: handled by com driver. 3rd & 4th UARTs use GPIO pins. 38 * 39 * If asked to probe with a wildcard address, we'll only do so if known to 40 * be running on a PC Engines APU board. Probe is invasive. 41 * 42 * Register access on Super I/O chips typically involves one or two levels 43 * of indirection, so we try hard to avoid needless register access. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: nct.c,v 1.1 2019/10/25 17:39:57 martin Exp $"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/types.h> 52 #include <sys/device.h> 53 #include <sys/module.h> 54 #include <sys/bus.h> 55 #include <sys/gpio.h> 56 57 #include <machine/autoconf.h> 58 59 #include <dev/isa/isavar.h> 60 61 #include <dev/gpio/gpiovar.h> 62 63 /* 64 * Hardware interface definition (enough for GPIO only). 65 */ 66 67 /* I/O basics */ 68 #define NCT_IOBASE_A 0x2e 69 #define NCT_IOBASE_B 0x4e 70 #define NCT_IOSIZE 2 71 #define NCT_CHIP_ID_1 0x1061 72 #define NCT_CHIP_ID_2 0xc452 /* PC Engines APU1 */ 73 #define NCT_NUM_PINS 17 74 75 /* Enable/disable keys */ 76 #define NCT_KEY_UNLOCK 0x87 77 #define NCT_KEY_LOCK 0xaa 78 79 /* I/O ports */ 80 #define NCT_PORT_SELECT 0 81 #define NCT_PORT_DATA 1 82 83 /* Global registers */ 84 #define GD_DEVSEL 0x0007 /* logical device select */ 85 #define GD_MULTIFUN 0x001c /* multi function selection */ 86 #define GD_MULTIFUN_GPIO1 0x04 /* clr: gpio1 available */ 87 #define GD_MULTIFUN_GPIO0 0x08 /* clr: gpio0 available */ 88 #define GD_MULTIFUN_GPIO67 0x10 /* set: gpio67 available */ 89 #define GD_GLOBOPT 0x0027 /* global option */ 90 #define GD_GLOBOPT_GPIO67 0x04 /* clr: gpio67 available */ 91 #define GD_ID_HIGH 0x0020 /* ID high byte */ 92 #define GD_ID_LOW 0x0021 /* ID low byte */ 93 94 /* Logical device 7 */ 95 #define LD7_ENABLE 0x0730 /* GPIO function enable */ 96 #define LD7_ENABLE_GPIO0 0x01 97 #define LD7_ENABLE_GPIO1 0x02 98 #define LD7_ENABLE_GPIO67 0x40 99 #define LD7_GPIO0_DIRECTION 0x07e0 /* clr for output, set for input */ 100 #define LD7_GPIO0_DATA 0x07e1 /* current status */ 101 #define LD7_GPIO0_INVERSION 0x07e2 /* set to invert i/o */ 102 #define LD7_GPIO0_STATUS 0x07e3 /* edge detect, reading clears */ 103 #define LD7_GPIO1_DIRECTION 0x07e4 /* clr for output, set for input */ 104 #define LD7_GPIO1_DATA 0x07e5 /* current status */ 105 #define LD7_GPIO1_INVERSION 0x07e6 /* set to invert i/o */ 106 #define LD7_GPIO1_STATUS 0x07e7 /* edge detect, reading clears */ 107 #define LD7_GPIO67_DIRECTION 0x07f8 /* clr for output, set for input */ 108 #define LD7_GPIO67_DATA 0x07f9 /* current status */ 109 #define LD7_GPIO67_INVERSION 0x07fa /* set to invert i/o */ 110 #define LD7_GPIO67_STATUS 0x07fb /* edge detect, reading clears */ 111 112 /* Logical device 8 */ 113 #define LD8_DEVCFG 0x0830 /* WDT/GPIO device config */ 114 #define LD8_GPIO0_MULTIFUNC 0x08e0 /* clr: gpio, set: pin unusable */ 115 #define LD8_GPIO1_MULTIFUNC 0x08e1 /* clr: gpio, set: pin unusable */ 116 #define LD8_GPIO67_MULTIFUNC 0x08e7 /* clr: gpio, set: pin unusable */ 117 118 /* Logical device 10 */ 119 #define LDA_UARTC_ENABLE 0x0a30 /* bit 0: UARTC active */ 120 121 /* Logical device 11 */ 122 #define LDB_UARTD_ENABLE 0x0b30 /* bit 0: UARTD active */ 123 124 /* Logical device 15 */ 125 #define LDF_GPIO0_OUTMODE 0x0fe0 /* clr: push/pull, set: open drain */ 126 #define LDF_GPIO1_OUTMODE 0x0fe1 /* clr: push/pull, set: open drain */ 127 #define LDF_GPIO67_OUTMODE 0x0fe6 /* clr: push/pull, set: open drain */ 128 129 /* 130 * Internal GPIO bank description, including register addresses and cached 131 * register content. 132 */ 133 struct nct_bank { 134 /* Pin descriptions */ 135 u_int8_t nb_firstpin; 136 u_int8_t nb_numpins; 137 u_int8_t nb_enabled; 138 139 /* Cached values */ 140 u_int8_t nb_val_dir; 141 u_int8_t nb_val_inv; 142 u_int8_t nb_val_mode; 143 144 /* Register addresses */ 145 u_int16_t nb_reg_dir; 146 u_int16_t nb_reg_data; 147 u_int16_t nb_reg_inv; 148 u_int16_t nb_reg_stat; 149 u_int16_t nb_reg_mode; 150 }; 151 152 /* 153 * Driver instance. 154 */ 155 struct nct_softc { 156 device_t sc_dev; /* MI device */ 157 bus_space_tag_t sc_iot; /* I/O tag */ 158 bus_space_handle_t sc_ioh; /* I/O handle */ 159 struct gpio_chipset_tag sc_gc; /* GPIO tag */ 160 gpio_pin_t sc_pins[NCT_NUM_PINS]; /* GPIO pin descr. */ 161 162 /* Access to the remaining members is covered by sc_lock. */ 163 kmutex_t sc_lock; /* Serialization */ 164 int sc_curdev; /* Cur. logical dev */ 165 int sc_curreg; /* Cur. register */ 166 struct nct_bank sc_bank[3]; /* Bank descriptions */ 167 }; 168 169 static void nct_attach(device_t, device_t, void *); 170 static int nct_detach(device_t, int); 171 static void nct_gpio_ctl(void *, int, int); 172 static int nct_gpio_read(void *, int); 173 static void nct_gpio_write(void *, int, int); 174 static int nct_match(device_t, cfdata_t , void *); 175 static u_int8_t nct_rd(struct nct_softc *, int); 176 static struct nct_bank *nct_sel(struct nct_softc *, int, u_int8_t *); 177 static void nct_wr(struct nct_softc *, int, u_int8_t); 178 179 static inline void 180 nct_outb(struct nct_softc *sc, int reg, u_int8_t data) 181 { 182 183 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, data); 184 } 185 186 static inline u_int8_t 187 nct_inb(struct nct_softc *sc, int reg) 188 { 189 190 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg); 191 } 192 193 CFATTACH_DECL_NEW(nct, 194 sizeof(struct nct_softc), 195 nct_match, 196 nct_attach, 197 nct_detach, 198 NULL); 199 200 MODULE(MODULE_CLASS_DRIVER, nct, "gpio"); 201 202 /* 203 * Module linkage. 204 */ 205 #ifdef _MODULE 206 #include "ioconf.c" 207 #endif 208 209 static int 210 nct_modcmd(modcmd_t cmd, void *priv) 211 { 212 int error = 0; 213 214 switch (cmd) { 215 case MODULE_CMD_INIT: 216 #ifdef _MODULE 217 error = config_init_component(cfdriver_ioconf_nct, 218 cfattach_ioconf_nct, cfdata_ioconf_nct); 219 #endif 220 return error; 221 case MODULE_CMD_FINI: 222 #ifdef _MODULE 223 error = config_fini_component(cfdriver_ioconf_nct, 224 cfattach_ioconf_nct, cfdata_ioconf_nct); 225 #endif 226 return error; 227 default: 228 return ENOTTY; 229 } 230 } 231 232 /* 233 * Probe for device. 234 */ 235 static int 236 nct_match(device_t parent, cfdata_t match, void *aux) 237 { 238 int ioaddrs[2] = { 0x2e, 0x4e }; 239 struct isa_attach_args *ia = aux; 240 bus_space_handle_t ioh; 241 int nioaddr, i; 242 u_int8_t low, high; 243 u_int16_t id; 244 245 /* 246 * Allow override of I/O base address. If no I/O base address is 247 * provided, proceed to probe if running on a PC Engines APU. 248 */ 249 if (ia->ia_nio > 0 && ia->ia_io[0].ir_addr != ISA_UNKNOWN_PORT) { 250 ioaddrs[0] = ia->ia_io[0].ir_addr; 251 nioaddr = 1; 252 } else if ((strcmp(pmf_get_platform("system-vendor"), "PC Engines") | 253 strcmp(pmf_get_platform("system-product"), "APU")) == 0) { 254 nioaddr = __arraycount(ioaddrs); 255 } else { 256 nioaddr = 0; 257 } 258 259 /* 260 * Probe at the selected addresses, if any. 261 */ 262 for (i = 0; i < nioaddr; i++) { 263 if (bus_space_map(ia->ia_iot, ioaddrs[i], NCT_IOSIZE, 0, 264 &ioh) != 0) { 265 continue; 266 } 267 /* Unlock chip */ 268 bus_space_write_1(ia->ia_iot, ioh, NCT_PORT_SELECT, 269 NCT_KEY_UNLOCK); 270 bus_space_write_1(ia->ia_iot, ioh, NCT_PORT_SELECT, 271 NCT_KEY_UNLOCK); 272 /* Read ID */ 273 bus_space_write_1(ia->ia_iot, ioh, NCT_PORT_SELECT, GD_ID_LOW); 274 low = bus_space_read_1(ia->ia_iot, ioh, NCT_PORT_DATA); 275 bus_space_write_1(ia->ia_iot, ioh, NCT_PORT_SELECT, GD_ID_HIGH); 276 high = bus_space_read_1(ia->ia_iot, ioh, NCT_PORT_DATA); 277 id = (u_int16_t)low | ((u_int16_t)high << 8); 278 bus_space_unmap(ia->ia_iot, ioh, NCT_IOSIZE); 279 if (id == NCT_CHIP_ID_1 || id == NCT_CHIP_ID_2) { 280 ia->ia_nirq = 0; 281 ia->ia_ndrq = 0; 282 ia->ia_niomem = 0; 283 ia->ia_nio = 1; 284 ia->ia_io[0].ir_size = NCT_IOSIZE; 285 ia->ia_io[0].ir_addr = ioaddrs[i]; 286 return 1; 287 } 288 } 289 return 0; 290 } 291 292 /* 293 * Attach device instance. 294 */ 295 static void 296 nct_attach(device_t parent, device_t self, void *aux) 297 { 298 struct nct_softc *sc = device_private(self); 299 struct isa_attach_args *ia = aux; 300 struct gpiobus_attach_args gba; 301 struct nct_bank *nb; 302 u_int8_t multifun, enable; 303 bool apu; 304 int i, j; 305 306 /* 307 * Set up register space and basics of our state. 308 */ 309 if (bus_space_map(ia->ia_iot, ia->ia_io[0].ir_addr, 310 ia->ia_io[0].ir_size, 0, &sc->sc_ioh) != 0) { 311 aprint_normal(": can't map i/o space\n"); 312 return; 313 } 314 aprint_normal(": Nuvoton NCT5104D GPIO\n"); 315 sc->sc_dev = self; 316 sc->sc_iot = ia->ia_iot; 317 sc->sc_curdev = -1; 318 sc->sc_curreg = -1; 319 apu = ((strcmp(pmf_get_platform("system-vendor"), "PC Engines") | 320 strcmp(pmf_get_platform("system-product"), "APU")) == 0); 321 322 /* 323 * All pin access is funneled through a common, indirect register 324 * interface. The gpio framework doesn't serialize calls to our 325 * access methods, so do it internally. This is likely such a 326 * common requirement that it should be factored out as is done for 327 * audio devices, allowing the driver to specify the appropriate 328 * locks. Anyhow, acquire the lock immediately to pacify locking 329 * assertions. 330 */ 331 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 332 mutex_spin_enter(&sc->sc_lock); 333 334 /* 335 * Disable watchdog timer and GPIO alternate I/O mapping. 336 */ 337 nct_wr(sc, LD8_DEVCFG, 0); 338 339 /* 340 * Fill out descriptions of GPIO0, GPIO1 and GPIO67. 341 * Determine which banks and pins are enabled. 342 */ 343 multifun = nct_rd(sc, GD_MULTIFUN); 344 enable = nct_rd(sc, LD7_ENABLE); 345 346 nb = &sc->sc_bank[0]; 347 nb->nb_firstpin = 0; 348 nb->nb_numpins = 8; 349 nb->nb_reg_dir = LD7_GPIO0_DIRECTION; 350 nb->nb_reg_data = LD7_GPIO0_DATA; 351 nb->nb_reg_inv = LD7_GPIO0_INVERSION; 352 nb->nb_reg_stat = LD7_GPIO0_STATUS; 353 nb->nb_reg_mode = LDF_GPIO0_OUTMODE; 354 if ((multifun & GD_MULTIFUN_GPIO0) == 0 && 355 ((nct_rd(sc, LDA_UARTC_ENABLE) & 1) == 0 || apu)) { 356 nct_wr(sc, LD8_GPIO0_MULTIFUNC, 0); 357 nb->nb_enabled = 0xff; 358 enable |= LD7_ENABLE_GPIO0; 359 } else { 360 sc->sc_bank[0].nb_enabled = 0; 361 } 362 363 nb = &sc->sc_bank[1]; 364 nb->nb_firstpin = 8; 365 nb->nb_numpins = 8; 366 nb->nb_reg_dir = LD7_GPIO1_DIRECTION; 367 nb->nb_reg_data = LD7_GPIO1_DATA; 368 nb->nb_reg_inv = LD7_GPIO1_INVERSION; 369 nb->nb_reg_stat = LD7_GPIO1_STATUS; 370 nb->nb_reg_mode = LDF_GPIO1_OUTMODE; 371 if ((multifun & GD_MULTIFUN_GPIO1) == 0 && 372 (nct_rd(sc, LDB_UARTD_ENABLE) & 1) == 0) { 373 nct_wr(sc, LD8_GPIO1_MULTIFUNC, 0); 374 nb->nb_enabled = 0xff; 375 enable |= LD7_ENABLE_GPIO1; 376 } else { 377 sc->sc_bank[1].nb_enabled = 0; 378 } 379 380 nb = &sc->sc_bank[2]; 381 nb->nb_firstpin = 16; 382 nb->nb_numpins = 1; 383 nb->nb_reg_dir = LD7_GPIO67_DIRECTION; 384 nb->nb_reg_data = LD7_GPIO67_DATA; 385 nb->nb_reg_stat = LD7_GPIO67_STATUS; 386 nb->nb_reg_mode = LDF_GPIO67_OUTMODE; 387 if ((multifun & GD_MULTIFUN_GPIO67) != 0 && 388 (nct_rd(sc, GD_GLOBOPT) & GD_GLOBOPT_GPIO67) == 0) { 389 nct_wr(sc, LD8_GPIO67_MULTIFUNC, 0); 390 nb->nb_enabled = 0x01; 391 enable |= LD7_ENABLE_GPIO67; 392 } else { 393 sc->sc_bank[2].nb_enabled = 0; 394 } 395 396 /* 397 * Display enabled pins and enable GPIO devices accordingly. 398 */ 399 nct_wr(sc, LD7_ENABLE, enable); 400 mutex_spin_exit(&sc->sc_lock); 401 402 aprint_normal_dev(self, 403 "enabled pins: GPIO0(%02x) GPIO1(%02x) GPIO67(%01x)\n", 404 (unsigned)sc->sc_bank[0].nb_enabled, 405 (unsigned)sc->sc_bank[1].nb_enabled, 406 (unsigned)sc->sc_bank[2].nb_enabled); 407 408 /* 409 * Fill pin descriptions and initialize registers. 410 */ 411 memset(sc->sc_pins, 0, sizeof(sc->sc_pins)); 412 for (i = 0; i < __arraycount(sc->sc_bank); i++) { 413 nb = &sc->sc_bank[i]; 414 mutex_spin_enter(&sc->sc_lock); 415 nb->nb_val_dir = nct_rd(sc, nb->nb_reg_dir); 416 nb->nb_val_inv = nct_rd(sc, nb->nb_reg_inv); 417 nb->nb_val_mode = nct_rd(sc, nb->nb_reg_mode); 418 mutex_spin_exit(&sc->sc_lock); 419 for (j = 0; j < nb->nb_numpins; j++) { 420 gpio_pin_t *pin = &sc->sc_pins[nb->nb_firstpin + j]; 421 pin->pin_num = nb->nb_firstpin + j; 422 /* Skip pin if not configured as GPIO. */ 423 if ((nb->nb_enabled & (1 << j)) == 0) { 424 continue; 425 } 426 pin->pin_caps = 427 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 428 GPIO_PIN_OPENDRAIN | 429 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 430 GPIO_PIN_INVIN | GPIO_PIN_INVOUT; 431 pin->pin_flags = 432 GPIO_PIN_INPUT | GPIO_PIN_OPENDRAIN; 433 nct_gpio_ctl(sc, pin->pin_num, pin->pin_flags); 434 pin->pin_state = nct_gpio_read(sc, pin->pin_num); 435 } 436 } 437 438 /* 439 * Attach to gpio framework, and attach all pins unconditionally. 440 * If the pins are disabled, we'll ignore any access later. 441 */ 442 sc->sc_gc.gp_cookie = sc; 443 sc->sc_gc.gp_pin_read = nct_gpio_read; 444 sc->sc_gc.gp_pin_write = nct_gpio_write; 445 sc->sc_gc.gp_pin_ctl = nct_gpio_ctl; 446 447 gba.gba_gc = &sc->sc_gc; 448 gba.gba_pins = sc->sc_pins; 449 gba.gba_npins = NCT_NUM_PINS; 450 451 (void)config_found(sc->sc_dev, &gba, gpiobus_print); 452 } 453 454 /* 455 * Detach device instance. 456 */ 457 static int 458 nct_detach(device_t self, int flags) 459 { 460 struct nct_softc *sc = device_private(self); 461 462 bus_space_unmap(sc->sc_iot, sc->sc_ioh, NCT_IOSIZE); 463 mutex_destroy(&sc->sc_lock); 464 return 0; 465 } 466 467 /* 468 * Read byte from specified register. 469 */ 470 static u_int8_t 471 nct_rd(struct nct_softc *sc, int reg) 472 { 473 int dev; 474 475 KASSERT(mutex_owned(&sc->sc_lock)); 476 477 dev = reg >> 8; 478 reg &= 0xff; 479 480 if (dev != sc->sc_curdev && dev != 0x00) { 481 sc->sc_curdev = dev; 482 sc->sc_curreg = reg; 483 nct_outb(sc, NCT_PORT_SELECT, GD_DEVSEL); 484 nct_outb(sc, NCT_PORT_DATA, dev); 485 nct_outb(sc, NCT_PORT_SELECT, reg); 486 return nct_inb(sc, NCT_PORT_DATA); 487 } else if (reg != sc->sc_curreg) { 488 sc->sc_curreg = reg; 489 nct_outb(sc, NCT_PORT_SELECT, reg); 490 return nct_inb(sc, NCT_PORT_DATA); 491 } else { 492 return nct_inb(sc, NCT_PORT_DATA); 493 } 494 } 495 496 /* 497 * Write byte to specified register. 498 */ 499 static void 500 nct_wr(struct nct_softc *sc, int reg, u_int8_t data) 501 { 502 int dev; 503 504 KASSERT(mutex_owned(&sc->sc_lock)); 505 506 dev = reg >> 8; 507 reg &= 0xff; 508 509 if (dev != sc->sc_curdev && dev != 0x00) { 510 sc->sc_curdev = dev; 511 sc->sc_curreg = reg; 512 nct_outb(sc, NCT_PORT_SELECT, GD_DEVSEL); 513 nct_outb(sc, NCT_PORT_DATA, dev); 514 nct_outb(sc, NCT_PORT_SELECT, reg); 515 nct_outb(sc, NCT_PORT_DATA, data); 516 } else if (reg != sc->sc_curreg) { 517 sc->sc_curreg = reg; 518 nct_outb(sc, NCT_PORT_SELECT, reg); 519 nct_outb(sc, NCT_PORT_DATA, data); 520 } else { 521 nct_outb(sc, NCT_PORT_DATA, data); 522 } 523 } 524 525 /* 526 * Given pin number, return bank and pin mask. This alters no state and so 527 * can safely be called without the mutex held. 528 */ 529 static struct nct_bank * 530 nct_sel(struct nct_softc *sc, int pin, u_int8_t *mask) 531 { 532 struct nct_bank *nb; 533 534 KASSERT(pin >= 0 && pin < NCT_NUM_PINS); 535 nb = &sc->sc_bank[pin >> 3]; 536 KASSERT(pin >= nb->nb_firstpin); 537 KASSERT((pin & 7) < nb->nb_numpins); 538 *mask = (u_int8_t)(1 << (pin & 7)) & nb->nb_enabled; 539 return nb; 540 } 541 542 /* 543 * GPIO hook: read pin. 544 */ 545 static int 546 nct_gpio_read(void *arg, int pin) 547 { 548 struct nct_softc *sc = arg; 549 struct nct_bank *nb; 550 u_int8_t data, mask; 551 int rv = GPIO_PIN_LOW; 552 553 nb = nct_sel(sc, pin, &mask); 554 if (__predict_true(mask != 0)) { 555 mutex_spin_enter(&sc->sc_lock); 556 data = nct_rd(sc, nb->nb_reg_data); 557 if ((data & mask) != 0) { 558 rv = GPIO_PIN_HIGH; 559 } 560 mutex_spin_exit(&sc->sc_lock); 561 } 562 return rv; 563 } 564 565 /* 566 * GPIO hook: write pin. 567 */ 568 static void 569 nct_gpio_write(void *arg, int pin, int val) 570 { 571 struct nct_softc *sc = arg; 572 struct nct_bank *nb; 573 u_int8_t data, mask; 574 575 nb = nct_sel(sc, pin, &mask); 576 if (__predict_true(mask != 0)) { 577 mutex_spin_enter(&sc->sc_lock); 578 data = nct_rd(sc, nb->nb_reg_data); 579 if (val == GPIO_PIN_LOW) { 580 data &= ~mask; 581 } else if (val == GPIO_PIN_HIGH) { 582 data |= mask; 583 } 584 nct_wr(sc, nb->nb_reg_data, data); 585 mutex_spin_exit(&sc->sc_lock); 586 } 587 } 588 589 /* 590 * GPIO hook: change pin parameters. 591 */ 592 static void 593 nct_gpio_ctl(void *arg, int pin, int flg) 594 { 595 struct nct_softc *sc = arg; 596 struct nct_bank *nb; 597 u_int8_t data, mask; 598 599 nb = nct_sel(sc, pin, &mask); 600 if (__predict_false(mask == 0)) { 601 return; 602 } 603 604 /* 605 * Set input direction early to avoid perturbation. 606 */ 607 mutex_spin_enter(&sc->sc_lock); 608 data = nb->nb_val_dir; 609 if ((flg & (GPIO_PIN_INPUT | GPIO_PIN_TRISTATE)) != 0) { 610 data |= mask; 611 } 612 if (data != nb->nb_val_dir) { 613 nct_wr(sc, nb->nb_reg_dir, data); 614 nb->nb_val_dir = data; 615 } 616 617 /* 618 * Set inversion. 619 */ 620 data = nb->nb_val_inv; 621 if ((flg & (GPIO_PIN_OUTPUT | GPIO_PIN_INVOUT)) == 622 (GPIO_PIN_OUTPUT | GPIO_PIN_INVOUT) || 623 (flg & (GPIO_PIN_INPUT | GPIO_PIN_INVIN)) == 624 (GPIO_PIN_INPUT | GPIO_PIN_INVIN)) { 625 data |= mask; 626 } else { 627 data &= ~mask; 628 } 629 if (data != nb->nb_val_inv) { 630 nct_wr(sc, nb->nb_reg_inv, data); 631 nb->nb_val_inv = data; 632 } 633 634 /* 635 * Set drain mode. 636 */ 637 data = nb->nb_val_mode; 638 if ((flg & GPIO_PIN_PUSHPULL) != 0) { 639 data |= mask; 640 } else /* GPIO_PIN_OPENDRAIN */ { 641 data &= ~mask; 642 } 643 if (data != nb->nb_val_mode) { 644 nct_wr(sc, nb->nb_reg_mode, data); 645 nb->nb_val_mode = data; 646 } 647 648 /* 649 * Set output direction late to avoid perturbation. 650 */ 651 data = nb->nb_val_dir; 652 if ((flg & (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE)) == GPIO_PIN_OUTPUT) { 653 data &= ~mask; 654 } 655 if (data != nb->nb_val_dir) { 656 nct_wr(sc, nb->nb_reg_dir, data); 657 nb->nb_val_dir = data; 658 } 659 mutex_spin_exit(&sc->sc_lock); 660 } 661
Indexes created Tue Sep 23 01:09:51 GMT 2025