nsclpcsio_isa.c revision 1.21
1 /* $NetBSD: nsclpcsio_isa.c,v 1.21 2007/11/09 01:09:47 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2002 5 * Matthias Drochner. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * National Semiconductor PC87366 LPC Super I/O driver. 31 * Supported logical devices: GPIO, TMS, VLM. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: nsclpcsio_isa.c,v 1.21 2007/11/09 01:09:47 xtraeme Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/mutex.h> 41 #include <sys/gpio.h> 42 #include <sys/bus.h> 43 44 /* Don't use gpio for now in the LKM */ 45 #ifdef _LKM 46 #undef NGPIO 47 #endif 48 49 #include <dev/isa/isareg.h> 50 #include <dev/isa/isavar.h> 51 52 #ifndef _LKM 53 #include "gpio.h" 54 #endif 55 #if NGPIO > 0 56 #include <dev/gpio/gpiovar.h> 57 #endif 58 #include <dev/sysmon/sysmonvar.h> 59 60 #define SIO_REG_SID 0x20 /* Super I/O ID */ 61 #define SIO_SID_PC87366 0xE9 /* PC87366 is identified by 0xE9.*/ 62 63 #define SIO_REG_SRID 0x27 /* Super I/O Revision */ 64 65 #define SIO_REG_LDN 0x07 /* Logical Device Number */ 66 #define SIO_LDN_FDC 0x00 /* Floppy Disk Controller (FDC) */ 67 #define SIO_LDN_PP 0x01 /* Parallel Port (PP) */ 68 #define SIO_LDN_SP2 0x02 /* Serial Port 2 with IR (SP2) */ 69 #define SIO_LDN_SP1 0x03 /* Serial Port 1 (SP1) */ 70 #define SIO_LDN_SWC 0x04 /* System Wake-Up Control (SWC) */ 71 #define SIO_LDN_KBCM 0x05 /* Mouse Controller (KBC) */ 72 #define SIO_LDN_KBCK 0x06 /* Keyboard Controller (KBC) */ 73 #define SIO_LDN_GPIO 0x07 /* General-Purpose I/O (GPIO) Ports */ 74 #define SIO_LDN_ACB 0x08 /* ACCESS.bus Interface (ACB) */ 75 #define SIO_LDN_FSCM 0x09 /* Fan Speed Control and Monitor (FSCM) */ 76 #define SIO_LDN_WDT 0x0A /* WATCHDOG Timer (WDT) */ 77 #define SIO_LDN_GMP 0x0B /* Game Port (GMP) */ 78 #define SIO_LDN_MIDI 0x0C /* Musical Instrument Digital Interface */ 79 #define SIO_LDN_VLM 0x0D /* Voltage Level Monitor (VLM) */ 80 #define SIO_LDN_TMS 0x0E /* Temperature Sensor (TMS) */ 81 82 #define SIO_REG_ACTIVE 0x30 /* Logical Device Activate Register */ 83 #define SIO_ACTIVE_EN 0x01 /* enabled */ 84 85 #define SIO_REG_IO_MSB 0x60 /* I/O Port Base, bits 15-8 */ 86 #define SIO_REG_IO_LSB 0x61 /* I/O Port Base, bits 7-0 */ 87 88 #define SIO_LDNUM 15 /* total number of logical devices */ 89 90 /* Supported logical devices description */ 91 static const struct { 92 const char *ld_name; 93 int ld_num; 94 int ld_iosize; 95 } sio_ld[] = { 96 { "GPIO", SIO_LDN_GPIO, 16 }, 97 { "VLM", SIO_LDN_VLM, 16 }, 98 { "TMS", SIO_LDN_TMS, 16 } 99 }; 100 101 /* GPIO */ 102 #define SIO_GPIO_PINSEL 0xf0 103 #define SIO_GPIO_PINCFG 0xf1 104 #define SIO_GPIO_PINEV 0xf2 105 106 #define SIO_GPIO_CONF_OUTPUTEN (1 << 0) 107 #define SIO_GPIO_CONF_PUSHPULL (1 << 1) 108 #define SIO_GPIO_CONF_PULLUP (1 << 2) 109 110 #define SIO_GPDO0 0x00 111 #define SIO_GPDI0 0x01 112 #define SIO_GPEVEN0 0x02 113 #define SIO_GPEVST0 0x03 114 #define SIO_GPDO1 0x04 115 #define SIO_GPDI1 0x05 116 #define SIO_GPEVEN1 0x06 117 #define SIO_GPEVST1 0x07 118 #define SIO_GPDO2 0x08 119 #define SIO_GPDI2 0x09 120 #define SIO_GPDO3 0x0a 121 #define SIO_GPDI3 0x0b 122 123 #define SIO_GPIO_NPINS 29 124 125 /* TMS */ 126 #define SIO_TEVSTS 0x00 /* Temperature Event Status */ 127 #define SIO_TEVSMI 0x02 /* Temperature Event to SMI */ 128 #define SIO_TEVIRQ 0x04 /* Temperature Event to IRQ */ 129 #define SIO_TMSCFG 0x08 /* TMS Configuration */ 130 #define SIO_TMSBS 0x09 /* TMS Bank Select */ 131 #define SIO_TCHCFST 0x0a /* Temperature Channel Config and Status */ 132 #define SIO_RDCHT 0x0b /* Read Channel Temperature */ 133 #define SIO_CHTH 0x0c /* Channel Temperature High Limit */ 134 #define SIO_CHTL 0x0d /* Channel Temperature Low Limit */ 135 #define SIO_CHOTL 0x0e /* Channel Overtemperature Limit */ 136 137 /* VLM */ 138 #define SIO_VEVSTS0 0x00 /* Voltage Event Status 0 */ 139 #define SIO_VEVSTS1 0x01 /* Voltage Event Status 1 */ 140 #define SIO_VEVSMI0 0x02 /* Voltage Event to SMI 0 */ 141 #define SIO_VEVSMI1 0x03 /* Voltage Event to SMI 1 */ 142 #define SIO_VEVIRQ0 0x04 /* Voltage Event to IRQ 0 */ 143 #define SIO_VEVIRQ1 0x05 /* Voltage Event to IRQ 1 */ 144 #define SIO_VID 0x06 /* Voltage ID */ 145 #define SIO_VCNVR 0x07 /* Voltage Conversion Rate */ 146 #define SIO_VLMCFG 0x08 /* VLM Configuration */ 147 #define SIO_VLMBS 0x09 /* VLM Bank Select */ 148 #define SIO_VCHCFST 0x0a /* Voltage Channel Config and Status */ 149 #define SIO_RDCHV 0x0b /* Read Channel Voltage */ 150 #define SIO_CHVH 0x0c /* Channel Voltage High Limit */ 151 #define SIO_CHVL 0x0d /* Channel Voltage Low Limit */ 152 #define SIO_OTSL 0x0e /* Overtemperature Shutdown Limit */ 153 154 #define SIO_REG_SIOCF1 0x21 155 #define SIO_REG_SIOCF2 0x22 156 #define SIO_REG_SIOCF3 0x23 157 #define SIO_REG_SIOCF4 0x24 158 #define SIO_REG_SIOCF5 0x25 159 #define SIO_REG_SIOCF8 0x28 160 #define SIO_REG_SIOCFA 0x2a 161 #define SIO_REG_SIOCFB 0x2b 162 #define SIO_REG_SIOCFC 0x2c 163 #define SIO_REG_SIOCFD 0x2d 164 165 #define SIO_VLM_OFF 3 166 #define SIO_NUM_SENSORS (SIO_VLM_OFF + 14) 167 #define SIO_VREF 1235 /* 1000.0 * VREF */ 168 169 struct nsclpcsio_softc { 170 struct device sc_dev; 171 bus_space_tag_t sc_iot; 172 bus_space_handle_t sc_ioh; 173 174 bus_space_handle_t sc_ld_ioh[SIO_LDNUM]; 175 int sc_ld_en[SIO_LDNUM]; 176 177 /* TMS and VLM */ 178 struct sysmon_envsys sc_sysmon; 179 envsys_data_t sc_sensor[SIO_NUM_SENSORS]; 180 181 kmutex_t sc_lock; 182 #if NGPIO > 0 183 /* GPIO */ 184 struct gpio_chipset_tag sc_gpio_gc; 185 struct gpio_pin sc_gpio_pins[SIO_GPIO_NPINS]; 186 #endif 187 }; 188 189 #define GPIO_READ(sc, reg) \ 190 bus_space_read_1((sc)->sc_iot, \ 191 (sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg)) 192 #define GPIO_WRITE(sc, reg, val) \ 193 bus_space_write_1((sc)->sc_iot, \ 194 (sc)->sc_ld_ioh[SIO_LDN_GPIO], (reg), (val)) 195 #define TMS_WRITE(sc, reg, val) \ 196 bus_space_write_1((sc)->sc_iot, \ 197 (sc)->sc_ld_ioh[SIO_LDN_TMS], (reg), (val)) 198 #define TMS_READ(sc, reg) \ 199 bus_space_read_1((sc)->sc_iot, \ 200 (sc)->sc_ld_ioh[SIO_LDN_TMS], (reg)) 201 #define VLM_WRITE(sc, reg, val) \ 202 bus_space_write_1((sc)->sc_iot, \ 203 (sc)->sc_ld_ioh[SIO_LDN_VLM], (reg), (val)) 204 #define VLM_READ(sc, reg) \ 205 bus_space_read_1((sc)->sc_iot, \ 206 (sc)->sc_ld_ioh[SIO_LDN_VLM], (reg)) 207 208 static int nsclpcsio_isa_match(struct device *, struct cfdata *, void *); 209 static void nsclpcsio_isa_attach(struct device *, struct device *, void *); 210 static int nsclpcsio_isa_detach(struct device *, int); 211 212 CFATTACH_DECL(nsclpcsio_isa, sizeof(struct nsclpcsio_softc), 213 nsclpcsio_isa_match, nsclpcsio_isa_attach, nsclpcsio_isa_detach, NULL); 214 215 static uint8_t nsread(bus_space_tag_t, bus_space_handle_t, int); 216 static void nswrite(bus_space_tag_t, bus_space_handle_t, int, uint8_t); 217 static int nscheck(bus_space_tag_t, int); 218 219 static void nsclpcsio_tms_init(struct nsclpcsio_softc *); 220 static void nsclpcsio_vlm_init(struct nsclpcsio_softc *); 221 static int nsclpcsio_gtredata(struct sysmon_envsys *, envsys_data_t *); 222 223 #if NGPIO > 0 224 static void nsclpcsio_gpio_init(struct nsclpcsio_softc *); 225 static void nsclpcsio_gpio_pin_select(struct nsclpcsio_softc *, int); 226 static void nsclpcsio_gpio_pin_write(void *, int, int); 227 static int nsclpcsio_gpio_pin_read(void *, int); 228 static void nsclpcsio_gpio_pin_ctl(void *, int, int); 229 #endif 230 231 static uint8_t 232 nsread(bus_space_tag_t iot, bus_space_handle_t ioh, int idx) 233 { 234 bus_space_write_1(iot, ioh, 0, idx); 235 return bus_space_read_1(iot, ioh, 1); 236 } 237 238 static void 239 nswrite(bus_space_tag_t iot, bus_space_handle_t ioh, int idx, uint8_t data) 240 { 241 bus_space_write_1(iot, ioh, 0, idx); 242 bus_space_write_1(iot, ioh, 1, data); 243 } 244 245 static int 246 nscheck(bus_space_tag_t iot, int base) 247 { 248 bus_space_handle_t ioh; 249 int rv = 0; 250 251 if (bus_space_map(iot, base, 2, 0, &ioh)) 252 return 0; 253 254 /* XXX this is for PC87366 only for now */ 255 if (nsread(iot, ioh, SIO_REG_SID) == SIO_SID_PC87366) 256 rv = 1; 257 258 bus_space_unmap(iot, ioh, 2); 259 return rv; 260 } 261 262 static int 263 nsclpcsio_isa_match(struct device *parent, struct cfdata *match, void *aux) 264 { 265 struct isa_attach_args *ia = aux; 266 int iobase; 267 268 if (ISA_DIRECT_CONFIG(ia)) 269 return 0; 270 271 if (ia->ia_nio > 0 && ia->ia_io[0].ir_addr != ISA_UNKNOWN_PORT) { 272 /* XXX check for legal iobase ??? */ 273 if (nscheck(ia->ia_iot, ia->ia_io[0].ir_addr)) { 274 iobase = ia->ia_io[0].ir_addr; 275 goto found; 276 } 277 return 0; 278 } 279 280 /* PC87366 has two possible locations depending on wiring */ 281 if (nscheck(ia->ia_iot, 0x2e)) { 282 iobase = 0x2e; 283 goto found; 284 } 285 if (nscheck(ia->ia_iot, 0x4e)) { 286 iobase = 0x4e; 287 goto found; 288 } 289 290 return 0; 291 292 found: 293 ia->ia_nio = 1; 294 ia->ia_io[0].ir_addr = iobase; 295 ia->ia_io[0].ir_size = 2; 296 ia->ia_niomem = 0; 297 ia->ia_nirq = 0; 298 ia->ia_ndrq = 0; 299 300 return 1; 301 } 302 303 static void 304 nsclpcsio_isa_attach(struct device *parent, struct device *self, void *aux) 305 { 306 struct nsclpcsio_softc *sc = device_private(self); 307 struct isa_attach_args *ia = aux; 308 #if NGPIO > 0 309 struct gpiobus_attach_args gba; 310 #endif 311 int i, iobase; 312 313 mutex_init(&sc->sc_lock, MUTEX_DRIVER, IPL_NONE); 314 315 sc->sc_iot = ia->ia_iot; 316 iobase = ia->ia_io[0].ir_addr; 317 318 if (bus_space_map(ia->ia_iot, iobase, 2, 0, &sc->sc_ioh)) { 319 aprint_error(": can't map i/o space\n"); 320 return; 321 } 322 323 aprint_normal(": NSC PC87366 rev. 0x%d ", 324 nsread(sc->sc_iot, sc->sc_ioh, SIO_REG_SRID)); 325 326 /* Configure all supported logical devices */ 327 for (i = 0; i < __arraycount(sio_ld); i++) { 328 sc->sc_ld_en[sio_ld[i].ld_num] = 0; 329 330 /* Select the device and check if it's activated */ 331 nswrite(sc->sc_iot, sc->sc_ioh, SIO_REG_LDN, sio_ld[i].ld_num); 332 if ((nsread(sc->sc_iot, sc->sc_ioh, 333 SIO_REG_ACTIVE) & SIO_ACTIVE_EN) == 0) 334 continue; 335 336 /* Map I/O space if necessary */ 337 if (sio_ld[i].ld_iosize != 0) { 338 iobase = (nsread(sc->sc_iot, sc->sc_ioh, 339 SIO_REG_IO_MSB) << 8); 340 iobase |= nsread(sc->sc_iot, sc->sc_ioh, 341 SIO_REG_IO_LSB); 342 if (bus_space_map(sc->sc_iot, iobase, 343 sio_ld[i].ld_iosize, 0, 344 &sc->sc_ld_ioh[sio_ld[i].ld_num])) 345 continue; 346 } 347 348 sc->sc_ld_en[sio_ld[i].ld_num] = 1; 349 aprint_normal("%s ", sio_ld[i].ld_name); 350 } 351 352 aprint_normal("\n"); 353 354 for (i = 0; i < SIO_NUM_SENSORS; i++) { 355 sc->sc_sensor[i].sensor = i; 356 sc->sc_sensor[i].state = ENVSYS_SVALID; 357 } 358 359 #if NGPIO > 0 360 nsclpcsio_gpio_init(sc); 361 #endif 362 nsclpcsio_tms_init(sc); 363 nsclpcsio_vlm_init(sc); 364 365 /* 366 * Hook into the System Monitor. 367 */ 368 sc->sc_sysmon.sme_name = device_xname(&sc->sc_dev); 369 sc->sc_sysmon.sme_sensor_data = sc->sc_sensor; 370 sc->sc_sysmon.sme_cookie = sc; 371 sc->sc_sysmon.sme_gtredata = nsclpcsio_gtredata; 372 sc->sc_sysmon.sme_nsensors = SIO_NUM_SENSORS; 373 374 if (sysmon_envsys_register(&sc->sc_sysmon)) 375 aprint_error("%s: unable to register with sysmon\n", 376 sc->sc_dev.dv_xname); 377 378 #if NGPIO > 0 379 /* attach GPIO framework */ 380 if (sc->sc_ld_en[SIO_LDN_GPIO]) { 381 gba.gba_gc = &sc->sc_gpio_gc; 382 gba.gba_pins = sc->sc_gpio_pins; 383 gba.gba_npins = SIO_GPIO_NPINS; 384 config_found_ia(&sc->sc_dev, "gpiobus", &gba, NULL); 385 } 386 #endif 387 } 388 389 static int 390 nsclpcsio_isa_detach(struct device *self, int flags) 391 { 392 struct nsclpcsio_softc *sc = device_private(self); 393 394 sysmon_envsys_unregister(&sc->sc_sysmon); 395 mutex_destroy(&sc->sc_lock); 396 397 bus_space_unmap(sc->sc_iot, sc->sc_ioh, 2); 398 399 return 0; 400 } 401 402 static void 403 nsclpcsio_tms_init(struct nsclpcsio_softc *sc) 404 { 405 int i; 406 407 /* Initialisation, PC87366.pdf, page 208 */ 408 TMS_WRITE(sc, 0x08, 0x00); 409 TMS_WRITE(sc, 0x09, 0x0f); 410 TMS_WRITE(sc, 0x0a, 0x08); 411 TMS_WRITE(sc, 0x0b, 0x04); 412 TMS_WRITE(sc, 0x0c, 0x35); 413 TMS_WRITE(sc, 0x0d, 0x05); 414 TMS_WRITE(sc, 0x0e, 0x05); 415 416 TMS_WRITE(sc, SIO_TMSCFG, 0x00); 417 418 for (i = 0; i < SIO_VLM_OFF; i++) { 419 TMS_WRITE(sc, SIO_TMSBS, i); 420 TMS_WRITE(sc, SIO_TCHCFST, 0x01); 421 sc->sc_sensor[i].units = ENVSYS_STEMP; 422 } 423 424 #define COPYDESCR(x, y) \ 425 do { \ 426 (void)strlcpy((x), (y), sizeof(x)); \ 427 } while (/* CONSTCOND */ 0) 428 429 COPYDESCR(sc->sc_sensor[0].desc, "TSENS1"); 430 COPYDESCR(sc->sc_sensor[1].desc, "TSENS2"); 431 COPYDESCR(sc->sc_sensor[2].desc, "TNSC"); 432 } 433 434 static void 435 nsclpcsio_vlm_init(struct nsclpcsio_softc *sc) 436 { 437 int i; 438 char tmp[16]; 439 440 for (i = SIO_VLM_OFF; i < SIO_NUM_SENSORS; i++) { 441 VLM_WRITE(sc, SIO_VLMBS, i - SIO_VLM_OFF); 442 VLM_WRITE(sc, SIO_VCHCFST, 0x01); 443 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC; 444 } 445 446 for (i = 0; i < 7; i++) { 447 (void)snprintf(tmp, sizeof(tmp), "VSENS%d", i); 448 COPYDESCR(sc->sc_sensor[i + SIO_VLM_OFF].desc, tmp); 449 } 450 451 i += SIO_VLM_OFF; 452 COPYDESCR(sc->sc_sensor[i + 1].desc, "VSB"); 453 COPYDESCR(sc->sc_sensor[i + 2].desc, "VDD"); 454 COPYDESCR(sc->sc_sensor[i + 3].desc, "VBAT"); 455 COPYDESCR(sc->sc_sensor[i + 4].desc, "AVDD"); 456 COPYDESCR(sc->sc_sensor[i + 5].desc, "TS1"); 457 COPYDESCR(sc->sc_sensor[i + 6].desc, "TS2"); 458 COPYDESCR(sc->sc_sensor[i + 7].desc, "TS3"); 459 } 460 461 462 static int 463 nsclpcsio_gtredata(struct sysmon_envsys *sme, envsys_data_t *edata) 464 { 465 struct nsclpcsio_softc *sc = sme->sme_cookie; 466 uint8_t status, data; 467 int8_t sdata = 0; 468 int scale, rfact; 469 470 scale = rfact = 0; 471 status = data = 0; 472 473 mutex_enter(&sc->sc_lock); 474 /* TMS */ 475 if (edata->sensor < SIO_VLM_OFF && sc->sc_ld_en[SIO_LDN_TMS]) { 476 TMS_WRITE(sc, SIO_TMSBS, edata->sensor); 477 status = TMS_READ(sc, SIO_TCHCFST); 478 if (!(status & 0x01)) 479 edata->state = ENVSYS_SINVALID; 480 481 sdata = TMS_READ(sc, SIO_RDCHT); 482 edata->value_cur = sdata * 1000000 + 273150000; 483 edata->state = ENVSYS_SVALID; 484 /* VLM */ 485 } else if (edata->sensor >= SIO_VLM_OFF && 486 edata->sensor < SIO_NUM_SENSORS && 487 sc->sc_ld_en[SIO_LDN_VLM]) { 488 VLM_WRITE(sc, SIO_VLMBS, edata->sensor - SIO_VLM_OFF); 489 status = VLM_READ(sc, SIO_VCHCFST); 490 if (!(status & 0x01)) { 491 edata->state = ENVSYS_SINVALID; 492 } else { 493 data = VLM_READ(sc, SIO_RDCHV); 494 scale = 1; 495 switch (edata->sensor - SIO_VLM_OFF) { 496 case 7: 497 case 8: 498 case 10: 499 scale = 2; 500 break; 501 } 502 /* Vi = (2.450.05)*VREF *RDCHVi / 256 */ 503 rfact = 10 * scale * ((245 * SIO_VREF) >> 8); 504 edata->value_cur = data * rfact; 505 edata->state = ENVSYS_SVALID; 506 } 507 } 508 mutex_exit(&sc->sc_lock); 509 510 return 0; 511 } 512 513 #if NGPIO > 0 514 static void 515 nsclpcsio_gpio_pin_select(struct nsclpcsio_softc *sc, int pin) 516 { 517 uint8_t v; 518 519 v = ((pin / 8) << 4) | (pin % 8); 520 521 nswrite(sc->sc_iot, sc->sc_ioh, SIO_REG_LDN, SIO_LDN_GPIO); 522 nswrite(sc->sc_iot, sc->sc_ioh, SIO_GPIO_PINSEL, v); 523 } 524 525 static void 526 nsclpcsio_gpio_init(struct nsclpcsio_softc *sc) 527 { 528 int i; 529 530 for (i = 0; i < SIO_GPIO_NPINS; i++) { 531 sc->sc_gpio_pins[i].pin_num = i; 532 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT | 533 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | 534 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 535 GPIO_PIN_PULLUP; 536 /* safe defaults */ 537 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE; 538 sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW; 539 nsclpcsio_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags); 540 nsclpcsio_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state); 541 } 542 543 /* create controller tag */ 544 sc->sc_gpio_gc.gp_cookie = sc; 545 sc->sc_gpio_gc.gp_pin_read = nsclpcsio_gpio_pin_read; 546 sc->sc_gpio_gc.gp_pin_write = nsclpcsio_gpio_pin_write; 547 sc->sc_gpio_gc.gp_pin_ctl = nsclpcsio_gpio_pin_ctl; 548 } 549 550 static int 551 nsclpcsio_gpio_pin_read(void *aux, int pin) 552 { 553 struct nsclpcsio_softc *sc = (struct nsclpcsio_softc *)aux; 554 int port, shift, reg; 555 uint8_t v; 556 557 port = pin / 8; 558 shift = pin % 8; 559 560 switch (port) { 561 case 0: 562 reg = SIO_GPDI0; 563 break; 564 case 1: 565 reg = SIO_GPDI1; 566 break; 567 case 2: 568 reg = SIO_GPDI2; 569 break; 570 case 3: 571 reg = SIO_GPDI3; 572 break; 573 default: 574 reg = SIO_GPDI0; 575 break; 576 } 577 578 v = GPIO_READ(sc, reg); 579 580 return ((v >> shift) & 0x1); 581 } 582 583 static void 584 nsclpcsio_gpio_pin_write(void *aux, int pin, int v) 585 { 586 struct nsclpcsio_softc *sc = (struct nsclpcsio_softc *)aux; 587 int port, shift, reg; 588 uint8_t d; 589 590 port = pin / 8; 591 shift = pin % 8; 592 593 switch (port) { 594 case 0: 595 reg = SIO_GPDO0; 596 break; 597 case 1: 598 reg = SIO_GPDO1; 599 break; 600 case 2: 601 reg = SIO_GPDO2; 602 break; 603 case 3: 604 reg = SIO_GPDO3; 605 break; 606 default: 607 reg = SIO_GPDO0; 608 break; /* shouldn't happen */ 609 } 610 611 d = GPIO_READ(sc, reg); 612 if (v == 0) 613 d &= ~(1 << shift); 614 else if (v == 1) 615 d |= (1 << shift); 616 GPIO_WRITE(sc, reg, d); 617 } 618 619 void 620 nsclpcsio_gpio_pin_ctl(void *aux, int pin, int flags) 621 { 622 struct nsclpcsio_softc *sc = (struct nsclpcsio_softc *)aux; 623 uint8_t conf; 624 625 mutex_enter(&sc->sc_lock); 626 627 nswrite(sc->sc_iot, sc->sc_ioh, SIO_REG_LDN, SIO_LDN_GPIO); 628 nsclpcsio_gpio_pin_select(sc, pin); 629 conf = nsread(sc->sc_iot, sc->sc_ioh, SIO_GPIO_PINCFG); 630 631 conf &= ~(SIO_GPIO_CONF_OUTPUTEN | SIO_GPIO_CONF_PUSHPULL | 632 SIO_GPIO_CONF_PULLUP); 633 if ((flags & GPIO_PIN_TRISTATE) == 0) 634 conf |= SIO_GPIO_CONF_OUTPUTEN; 635 if (flags & GPIO_PIN_PUSHPULL) 636 conf |= SIO_GPIO_CONF_PUSHPULL; 637 if (flags & GPIO_PIN_PULLUP) 638 conf |= SIO_GPIO_CONF_PULLUP; 639 640 nswrite(sc->sc_iot, sc->sc_ioh, SIO_GPIO_PINCFG, conf); 641 642 mutex_exit(&sc->sc_lock); 643 } 644 #endif /* NGPIO */ 645
Indexes created Mon Sep 29 21:09:56 GMT 2025