sb.c revision 1.8 1 /*
2 * Copyright (c) 1991-1993 Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the Computer Systems
16 * Engineering Group at Lawrence Berkeley Laboratory.
17 * 4. Neither the name of the University nor of the Laboratory may be used
18 * to endorse or promote products derived from this software without
19 * specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $Id: sb.c,v 1.8 1994/04/22 22:59:00 mycroft Exp $
34 */
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/errno.h>
39 #include <sys/ioctl.h>
40 #include <sys/syslog.h>
41 #include <sys/device.h>
42
43 #include <machine/cpu.h>
44 #include <machine/pio.h>
45
46 #include <i386/isa/isa.h>
47 #include <i386/isa/isavar.h>
48 #include <i386/isa/dmavar.h>
49 #include <i386/isa/icu.h>
50
51 #include "sbreg.h"
52
53 /*
54 * Software state, per SoundBlaster card.
55 * The soundblaster has multiple functionality, which we must demultiplex.
56 * One approach is to have one major device number for the soundblaster card,
57 * and use different minor numbers to indicate which hardware function
58 * we want. This would make for one large driver. Instead our approach
59 * is to partition the design into a set of drivers that share an underlying
60 * piece of hardware. Most things are hard to share, for example, the audio
61 * and midi ports. For audio, we might want to mix two processes' signals,
62 * and for midi we might want to merge streams (this is hard due to
63 * running status). Moreover, we should be able to re-use the high-level
64 * modules with other kinds of hardware. In this module, we only handle the
65 * most basic communications with the sb card.
66 */
67 struct sb_softc {
68 struct device sc_dev; /* base device */
69 struct isadev sc_id; /* ISA device */
70 struct intrhand sc_ih; /* interrupt vectoring */
71
72 u_short sc_open; /* reference count of open calls */
73 u_short sc_dmachan; /* dma channel */
74 u_short sc_locked; /* true when doing HS DMA */
75 u_short sc_iobase; /* I/O port base address */
76 u_short sc_adacmode; /* low/high speed mode indicator */
77 #define SB_ADAC_LS 0
78 #define SB_ADAC_HS 1
79 u_short sc_adactc; /* current adac time constant */
80 u_long sc_interrupts; /* number of interrupts taken */
81 void (*sc_intr)(void*); /* dma completion intr handler */
82 void (*sc_mintr)(void*, int);/* midi input intr handler */
83 void *sc_arg; /* arg for sc_intr() */
84 };
85
86 int sbreset __P((struct sb_softc *));
87 void sb_spkron __P((struct sb_softc *));
88 void sb_spkroff __P((struct sb_softc *));
89
90 static int wdsp(u_short iobase, int v);
91 static int rdsp(u_short iobase);
92
93 #define splsb splhigh /* XXX */
94 struct sb_softc *sb_softc; /* XXX */
95
96 #ifndef NEWCONFIG
97 #define at_dma(flags, ptr, cc, chan) isa_dmastart(flags, ptr, cc, chan)
98 #endif
99
100 struct {
101 int wdsp;
102 int rdsp;
103 int wmidi;
104 } sberr;
105
106 int sbintr __P((struct sb_softc *));
107 int sbprobe();
108 void sbattach();
109 #ifdef NEWCONFIG
110 void sbforceintr(void *);
111 #endif
112
113 struct cfdriver sbcd = {
114 NULL, "sb", sbprobe, sbattach, DV_DULL, sizeof(struct sb_softc)
115 };
116
117 int
118 sbprobe(parent, self, aux)
119 struct device *parent, *self;
120 void *aux;
121 {
122 register struct sb_softc *sc = (void *)self;
123 register struct isa_attach_args *ia = aux;
124 register u_short iobase = ia->ia_iobase;
125
126 if (!SB_BASE_VALID(ia->ia_iobase)) {
127 printf("sb: configured iobase %d invalid\n", ia->ia_iobase);
128 return 0;
129 }
130 sc->sc_iobase = iobase;
131 if (sbreset(sc) < 0) {
132 printf("sb: couldn't reset card\n");
133 return 0;
134 }
135 /*
136 * Cannot auto-discover DMA channel.
137 */
138 if (!SB_DRQ_VALID(ia->ia_drq)) {
139 printf("sb: configured dma chan %d invalid\n", ia->ia_drq);
140 return 0;
141 }
142 #ifdef NEWCONFIG
143 /*
144 * If the IRQ wasn't compiled in, auto-detect it.
145 */
146 if (ia->ia_irq == IRQUNK) {
147 ia->ia_irq = isa_discoverintr(sbforceintr, aux);
148 sbreset(iobase);
149 if (!SB_IRQ_VALID(ia->ia_irq)) {
150 printf("sb: couldn't auto-detect interrupt");
151 return 0;
152 }
153 } else
154 #endif
155 if (!SB_IRQ_VALID(ia->ia_irq)) {
156 int irq = ffs(ia->ia_irq) - 1;
157 printf("sb: configured irq %d invalid\n", irq);
158 return 0;
159 }
160 ia->ia_iosize = SB_NPORT;
161 return 1;
162 }
163
164 #ifdef NEWCONFIG
165 void
166 sbforceintr(aux)
167 void *aux;
168 {
169 static char dmabuf;
170 struct isa_attach_args *ia = aux;
171 u_short iobase = ia->ia_iobase;
172
173 /*
174 * Set up a DMA read of one byte.
175 * XXX Note that at this point we haven't called
176 * at_setup_dmachan(). This is okay because it just
177 * allocates a buffer in case it needs to make a copy,
178 * and it won't need to make a copy for a 1 byte buffer.
179 * (I think that calling at_setup_dmachan() should be optional;
180 * if you don't call it, it will be called the first time
181 * it is needed (and you pay the latency). Also, you might
182 * never need the buffer anyway.)
183 */
184 at_dma(1, &dmabuf, 1, ia->ia_drq);
185 if (wdsp(iobase, SB_DSP_RDMA) == 0) {
186 (void)wdsp(iobase, 0);
187 (void)wdsp(iobase, 0);
188 }
189 }
190 #endif
191
192 void
193 sbattach(parent, self, aux)
194 struct device *parent, *self;
195 void *aux;
196 {
197 register struct sb_softc *sc = (struct sb_softc *)self;
198 struct isa_attach_args *ia = (struct isa_attach_args *)aux;
199 register u_short iobase = ia->ia_iobase;
200 register int vers;
201
202 /* XXX */
203 sb_softc = sc;
204
205 sc->sc_iobase = iobase;
206 sc->sc_dmachan = ia->ia_drq;
207 sc->sc_locked = 0;
208
209 #ifdef NEWCONFIG
210 isa_establish(&sc->sc_id, &sc->sc_dev);
211 #endif
212 sc->sc_ih.ih_fun = sbintr;
213 sc->sc_ih.ih_arg = sc;
214 sc->sc_ih.ih_level = IPL_BIO;
215 intr_establish(ia->ia_irq, &sc->sc_ih);
216
217 #ifdef NEWCONFIG
218 /*
219 * We limit DMA transfers to a page, and use the generic DMA handling
220 * code in isa.c. This code can end up copying a buffer, but since
221 * the audio driver uses relative small buffers this isn't likely.
222 *
223 * This allocation scheme means that the maximum transfer is limited
224 * by the page size (rather than 64k). This is reasonable. For 4K
225 * pages, the transfer time at 48KHz is 4096 / 48000 = 85ms. This
226 * is plenty long enough to amortize any fixed time overhead.
227 */
228 at_setup_dmachan(sc->sc_dmachan, NBPG);
229 #endif
230
231 vers = sbversion(sc);
232 printf(": dsp v%d.%d\n", vers >> 8, vers & 0xff);
233 }
234
235 #define SBUNIT(x) (minor(x) & 0xf)
236
237 struct sb_softc *
238 sbopen()
239 {
240 /* XXXX */
241 struct sb_softc *sc = sb_softc;
242
243 if (sc == 0)
244 return 0;
245
246 if (sc->sc_open == 0 && sbreset(sc) == 0) {
247 sc->sc_open = 1;
248 sc->sc_mintr = 0;
249 sc->sc_intr = 0;
250 return sc;
251 }
252 return 0;
253 }
254
255 void
256 sbclose(sc)
257 struct sb_softc *sc;
258 {
259
260 sc->sc_open = 0;
261 sb_spkroff(sc);
262 sc->sc_intr = 0;
263 sc->sc_mintr = 0;
264 /* XXX this will turn off any dma */
265 sbreset(sc);
266 }
267
268 /*
269 * Write a byte to the dsp.
270 * XXX We are at the mercy of the card as we use a
271 * polling loop and wait until it can take the byte.
272 */
273 static int
274 wdsp(u_short iobase, int v)
275 {
276 register int i;
277
278 for (i = 100; --i >= 0; ) {
279 if ((inb(iobase + SBP_DSP_WSTAT) & SB_DSP_BUSY) != 0)
280 continue;
281 outb(iobase + SBP_DSP_WRITE, v);
282 return 0;
283 }
284 ++sberr.wdsp;
285 return -1;
286 }
287
288 /*
289 * Read a byte from the DSP, using polling.
290 */
291 int
292 rdsp(u_short iobase)
293 {
294 register int i;
295
296 for (i = 100; --i >= 0; ) {
297 if ((inb(iobase + SBP_DSP_RSTAT) & SB_DSP_READY) == 0)
298 continue;
299 return inb(iobase + SBP_DSP_READ);
300 }
301 ++sberr.rdsp;
302 return -1;
303 }
304
305 /*
306 * Reset the card.
307 * Return non-zero if the card isn't detected.
308 */
309 int
310 sbreset(sc)
311 struct sb_softc *sc;
312 {
313 register u_short iobase = sc->sc_iobase;
314 register int i;
315
316 /*
317 * See SBK, section 11.3.
318 * We pulse a reset signal into the card.
319 * Gee, what a brilliant hardware design.
320 */
321 outb(iobase + SBP_DSP_RESET, 1);
322 delay(3);
323 outb(iobase + SBP_DSP_RESET, 0);
324 if (rdsp(iobase) != SB_MAGIC)
325 return -1;
326 return 0;
327 }
328
329 /*
330 * Turn on the speaker. The SBK documention says this operation
331 * can take up to 1/10 of a second. Higher level layers should
332 * probably let the task sleep for this amount of time after
333 * calling here. Otherwise, things might not work (because
334 * wdsp() and rdsp() will probably timeout.)
335 *
336 * These engineers had their heads up their ass when
337 * they designed this card.
338 */
339 void
340 sb_spkron(sc)
341 struct sb_softc *sc;
342 {
343
344 (void)wdsp(sc->sc_iobase, SB_DSP_SPKR_ON);
345 /* XXX bogus */
346 delay(1000);
347 }
348
349 /*
350 * Turn off the speaker; see comment above.
351 */
352 void
353 sb_spkroff(sc)
354 struct sb_softc *sc;
355 {
356
357 (void)wdsp(sc->sc_iobase, SB_DSP_SPKR_OFF);
358 }
359
360 /*
361 * Read the version number out of the card. Return major code
362 * in high byte, and minor code in low byte.
363 */
364 int
365 sbversion(sc)
366 struct sb_softc *sc;
367 {
368 register u_short iobase = sc->sc_iobase;
369 int v;
370
371 if (wdsp(iobase, SB_DSP_VERSION) < 0)
372 return 0;
373 v = rdsp(iobase) << 8;
374 v |= rdsp(iobase);
375 return ((v >= 0) ? v : 0);
376 }
377
378 /*
379 * Halt a DMA in progress. A low-speed transfer can be
380 * resumed with sb_contdma().
381 */
382 void
383 sb_haltdma(sc)
384 struct sb_softc *sc;
385 {
386
387 if (sc->sc_locked)
388 sbreset(sc);
389 else
390 (void)wdsp(sc->sc_iobase, SB_DSP_HALT);
391 }
392
393 void
394 sb_contdma(sc)
395 struct sb_softc *sc;
396 {
397
398 (void)wdsp(sc->sc_iobase, SB_DSP_CONT);
399 }
400
401 /*
402 * Time constant routines follow. See SBK, section 12.
403 * Although they don't come out and say it (in the docs),
404 * the card clearly uses a 1MHz countdown timer, as the
405 * low-speed formula (p. 12-4) is:
406 * tc = 256 - 10^6 / sr
407 * In high-speed mode, the constant is the upper byte of a 16-bit counter,
408 * and a 256MHz clock is used:
409 * tc = 65536 - 256 * 10^ 6 / sr
410 * Since we can only use the upper byte of the HS TC, the two formulae
411 * are equivalent. (Why didn't they say so?) E.g.,
412 * (65536 - 256 * 10 ^ 6 / x) >> 8 = 256 - 10^6 / x
413 *
414 * The crossover point (from low- to high-speed modes) is different
415 * for the SBPRO and SB20. The table on p. 12-5 gives the following data:
416 *
417 * SBPRO SB20
418 * ----- --------
419 * input ls min 4 KHz 4 HJz
420 * input ls max 23 KHz 13 KHz
421 * input hs max 44.1 KHz 15 KHz
422 * output ls min 4 KHz 4 KHz
423 * output ls max 23 KHz 23 KHz
424 * output hs max 44.1 KHz 44.1 KHz
425 */
426 #define SB_LS_MIN 0x06 /* 4000 Hz */
427 #ifdef SBPRO
428 #define SB_ADC_LS_MAX 0xd4 /* 22727 Hz */
429 #define SB_ADC_HS_MAX 0xe9 /* 43478 Hz */
430 #else
431 #define SB_ADC_LS_MAX 0xb3 /* 12987 Hz */
432 #define SB_ADC_HS_MAX 0xbd /* 14925 Hz */
433 #endif
434 #define SB_DAC_LS_MAX 0xd4 /* 22727 Hz */
435 #define SB_DAC_HS_MAX 0xe9 /* 43478 Hz */
436
437 /*
438 * Convert a linear sampling rate into the DAC time constant.
439 * Set *mode to indicate the high/low-speed DMA operation.
440 * Because of limitations of the card, not all rates are possible.
441 * We return the time constant of the closest possible rate.
442 * The sampling rate limits are different for the DAC and ADC,
443 * so isdac indicates output, and !isdac indicates input.
444 */
445 int
446 sb_srtotc(sr, mode, isdac)
447 int sr;
448 int *mode;
449 int isdac;
450 {
451 register int tc = 256 - 1000000 / sr;
452
453 if (tc < SB_LS_MIN) {
454 tc = SB_LS_MIN;
455 *mode = SB_ADAC_LS;
456 } else if (isdac) {
457 if (tc < SB_DAC_LS_MAX)
458 *mode = SB_ADAC_LS;
459 else {
460 *mode = SB_ADAC_HS;
461 if (tc > SB_DAC_HS_MAX)
462 tc = SB_DAC_HS_MAX;
463 }
464 } else {
465 if (tc < SB_ADC_LS_MAX)
466 *mode = SB_ADAC_LS;
467 else {
468 *mode = SB_ADAC_HS;
469 if (tc > SB_ADC_HS_MAX)
470 tc = SB_ADC_HS_MAX;
471 }
472 }
473 return tc;
474 }
475
476 /*
477 * Convert a DAC time constant to a sampling rate.
478 * See SBK, section 12.
479 */
480 int
481 sb_tctosr(tc)
482 int tc;
483 {
484 return (1000000 / (256 - tc));
485 }
486
487 int
488 sb_set_sr(sc, sr, isdac)
489 register struct sb_softc *sc;
490 u_long *sr;
491 int isdac;
492 {
493 register int tc;
494 int mode;
495
496 tc = sb_srtotc(*sr, &mode, isdac);
497 if (wdsp(sc->sc_iobase, SB_DSP_TIMECONST) < 0 ||
498 wdsp(sc->sc_iobase, tc) < 0)
499 return -1;
500
501 *sr = sb_tctosr(tc);
502 sc->sc_adacmode = mode;
503 sc->sc_adactc = tc;
504
505 return 0;
506 }
507
508 int
509 sb_round_sr(sr, isdac)
510 u_long sr;
511 int isdac;
512 {
513 int mode, tc;
514
515 tc = sb_srtotc(sr, &mode, isdac);
516 return sb_tctosr(tc);
517 }
518
519 int
520 sb_dma_input(sc, p, cc, intr, arg)
521 struct sb_softc *sc;
522 void *p;
523 int cc;
524 void (*intr)();
525 void *arg;
526 {
527 register u_short iobase;
528
529 at_dma(1, p, cc, sc->sc_dmachan);
530 sc->sc_intr = intr;
531 sc->sc_arg = arg;
532 iobase = sc->sc_iobase;
533 --cc;
534 if (sc->sc_adacmode == SB_ADAC_LS) {
535 if (wdsp(iobase, SB_DSP_RDMA) < 0 ||
536 wdsp(iobase, cc) < 0 ||
537 wdsp(iobase, cc >> 8) < 0) {
538 sbreset(sc);
539 return EIO;
540 }
541 } else {
542 if (wdsp(iobase, SB_DSP_BLOCKSIZE) < 0 ||
543 wdsp(iobase, cc) < 0 ||
544 wdsp(iobase, cc >> 8) < 0 ||
545 wdsp(iobase, SB_DSP_HS_INPUT) < 0) {
546 sbreset(sc);
547 return EIO;
548 }
549 sc->sc_locked = 1;
550 }
551 return 0;
552 }
553
554 int
555 sb_dma_output(sc, p, cc, intr, arg)
556 struct sb_softc *sc;
557 void *p;
558 int cc;
559 void (*intr)();
560 void *arg;
561 {
562 register u_short iobase;
563
564 at_dma(0, p, cc, sc->sc_dmachan);
565 sc->sc_intr = intr;
566 sc->sc_arg = arg;
567 iobase = sc->sc_iobase;
568 --cc;
569 if (sc->sc_adacmode == SB_ADAC_LS) {
570 if (wdsp(iobase, SB_DSP_WDMA) < 0 ||
571 wdsp(iobase, cc) < 0 ||
572 wdsp(iobase, cc >> 8) < 0) {
573 sbreset(sc);
574 return EIO;
575 }
576 } else {
577 if (wdsp(iobase, SB_DSP_BLOCKSIZE) < 0 ||
578 wdsp(iobase, cc) < 0 ||
579 wdsp(iobase, cc >> 8) < 0 ||
580 wdsp(iobase, SB_DSP_HS_OUTPUT) < 0) {
581 sbreset(sc);
582 return EIO;
583 }
584 sc->sc_locked = 1;
585 }
586 return 0;
587 }
588
589 /*
590 * Only the DSP unit on the sound blaster generates interrupts.
591 * There are three cases of interrupt: reception of a midi byte
592 * (when mode is enabled), completion of dma transmission, or
593 * completion of a dma reception. The three modes are mutually
594 * exclusive so we know a priori which event has occurred.
595 */
596 int
597 sbintr(sc)
598 register struct sb_softc *sc;
599 {
600
601 sc->sc_locked = 0;
602 /* clear interrupt */
603 inb(sc->sc_iobase + SBP_DSP_RSTAT);
604 if (sc->sc_mintr != 0) {
605 int c = rdsp(sc->sc_iobase);
606 (*sc->sc_mintr)(sc->sc_arg, c);
607 } else if (sc->sc_intr != 0)
608 (*sc->sc_intr)(sc->sc_arg);
609 else
610 return 0;
611 return 1;
612 }
613
614 /*
615 * Enter midi uart mode and arrange for read interrupts
616 * to vector to `intr'. This puts the card in a mode
617 * which allows only midi I/O; the card must be reset
618 * to leave this mode. Unfortunately, the card does not
619 * use transmit interrupts, so bytes must be output
620 * using polling. To keep the polling overhead to a
621 * minimum, output should be driven off a timer.
622 * This is a little tricky since only 320us separate
623 * consecutive midi bytes.
624 */
625 void
626 sb_set_midi_mode(sc, intr, arg)
627 struct sb_softc *sc;
628 void (*intr)();
629 void *arg;
630 {
631
632 wdsp(sc->sc_iobase, SB_MIDI_UART_INTR);
633 sc->sc_mintr = intr;
634 sc->sc_intr = 0;
635 sc->sc_arg = arg;
636 }
637
638 /*
639 * Write a byte to the midi port, when in midi uart mode.
640 */
641 void
642 sb_midi_output(sc, v)
643 struct sb_softc *sc;
644 int v;
645 {
646
647 if (wdsp(sc->sc_iobase, v) < 0)
648 ++sberr.wmidi;
649 }
650