wdc_isa.c revision 1.23
1 /* $NetBSD: wdc_isa.c,v 1.23 2001/11/15 09:48:10 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdc_isa.c,v 1.23 2001/11/15 09:48:10 lukem Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/isa/isavar.h> 51 #include <dev/isa/isadmavar.h> 52 53 #include <dev/ata/atavar.h> 54 #include <dev/ic/wdcvar.h> 55 56 #define WDC_ISA_REG_NPORTS 8 57 #define WDC_ISA_AUXREG_OFFSET 0x206 58 #define WDC_ISA_AUXREG_NPORTS 1 /* XXX "fdc" owns ports 0x3f7/0x377 */ 59 60 /* options passed via the 'flags' config keyword */ 61 #define WDC_OPTIONS_32 0x01 /* try to use 32bit data I/O */ 62 #define WDC_OPTIONS_SINGLE_DRIVE 0x02 /* Don't probe second drive */ 63 #define WDC_OPTIONS_ATA_NOSTREAM 0x04 64 #define WDC_OPTIONS_ATAPI_NOSTREAM 0x08 65 66 struct wdc_isa_softc { 67 struct wdc_softc sc_wdcdev; 68 struct channel_softc *wdc_chanptr; 69 struct channel_softc wdc_channel; 70 isa_chipset_tag_t sc_ic; 71 void *sc_ih; 72 int sc_drq; 73 }; 74 75 int wdc_isa_probe __P((struct device *, struct cfdata *, void *)); 76 void wdc_isa_attach __P((struct device *, struct device *, void *)); 77 78 struct cfattach wdc_isa_ca = { 79 sizeof(struct wdc_isa_softc), wdc_isa_probe, wdc_isa_attach 80 }; 81 82 static void wdc_isa_dma_setup __P((struct wdc_isa_softc *)); 83 static int wdc_isa_dma_init __P((void*, int, int, void *, size_t, int)); 84 static void wdc_isa_dma_start __P((void*, int, int)); 85 static int wdc_isa_dma_finish __P((void*, int, int, int)); 86 87 int 88 wdc_isa_probe(parent, match, aux) 89 struct device *parent; 90 struct cfdata *match; 91 void *aux; 92 { 93 struct channel_softc ch; 94 struct isa_attach_args *ia = aux; 95 int result = 0; 96 97 memset(&ch, 0, sizeof(ch)); 98 99 ch.cmd_iot = ia->ia_iot; 100 if (bus_space_map(ch.cmd_iot, ia->ia_iobase, WDC_ISA_REG_NPORTS, 0, 101 &ch.cmd_ioh)) 102 goto out; 103 104 ch.ctl_iot = ia->ia_iot; 105 if (bus_space_map(ch.ctl_iot, ia->ia_iobase + WDC_ISA_AUXREG_OFFSET, 106 WDC_ISA_AUXREG_NPORTS, 0, &ch.ctl_ioh)) 107 goto outunmap; 108 109 result = wdcprobe(&ch); 110 if (result) { 111 ia->ia_iosize = WDC_ISA_REG_NPORTS; 112 ia->ia_msize = 0; 113 } 114 115 bus_space_unmap(ch.ctl_iot, ch.ctl_ioh, WDC_ISA_AUXREG_NPORTS); 116 outunmap: 117 bus_space_unmap(ch.cmd_iot, ch.cmd_ioh, WDC_ISA_REG_NPORTS); 118 out: 119 return (result); 120 } 121 122 void 123 wdc_isa_attach(parent, self, aux) 124 struct device *parent, *self; 125 void *aux; 126 { 127 struct wdc_isa_softc *sc = (void *)self; 128 struct isa_attach_args *ia = aux; 129 130 printf("\n"); 131 132 sc->wdc_channel.cmd_iot = ia->ia_iot; 133 sc->wdc_channel.ctl_iot = ia->ia_iot; 134 sc->sc_ic = ia->ia_ic; 135 if (bus_space_map(sc->wdc_channel.cmd_iot, ia->ia_iobase, 136 WDC_ISA_REG_NPORTS, 0, &sc->wdc_channel.cmd_ioh) || 137 bus_space_map(sc->wdc_channel.ctl_iot, 138 ia->ia_iobase + WDC_ISA_AUXREG_OFFSET, WDC_ISA_AUXREG_NPORTS, 139 0, &sc->wdc_channel.ctl_ioh)) { 140 printf("%s: couldn't map registers\n", 141 sc->sc_wdcdev.sc_dev.dv_xname); 142 } 143 sc->wdc_channel.data32iot = sc->wdc_channel.cmd_iot; 144 sc->wdc_channel.data32ioh = sc->wdc_channel.cmd_ioh; 145 146 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 147 IPL_BIO, wdcintr, &sc->wdc_channel); 148 149 if (ia->ia_drq != DRQUNK) { 150 sc->sc_drq = ia->ia_drq; 151 152 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 153 sc->sc_wdcdev.dma_arg = sc; 154 sc->sc_wdcdev.dma_init = wdc_isa_dma_init; 155 sc->sc_wdcdev.dma_start = wdc_isa_dma_start; 156 sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish; 157 wdc_isa_dma_setup(sc); 158 } 159 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_PREATA; 160 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_32) 161 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32; 162 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_SINGLE_DRIVE) 163 sc->sc_wdcdev.cap |= WDC_CAPABILITY_SINGLE_DRIVE; 164 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_ATA_NOSTREAM) 165 sc->sc_wdcdev.cap |= WDC_CAPABILITY_ATA_NOSTREAM; 166 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags 167 & WDC_OPTIONS_ATAPI_NOSTREAM) 168 sc->sc_wdcdev.cap |= WDC_CAPABILITY_ATAPI_NOSTREAM; 169 sc->sc_wdcdev.PIO_cap = 0; 170 sc->wdc_chanptr = &sc->wdc_channel; 171 sc->sc_wdcdev.channels = &sc->wdc_chanptr; 172 sc->sc_wdcdev.nchannels = 1; 173 sc->wdc_channel.channel = 0; 174 sc->wdc_channel.wdc = &sc->sc_wdcdev; 175 sc->wdc_channel.ch_queue = malloc(sizeof(struct channel_queue), 176 M_DEVBUF, M_NOWAIT); 177 if (sc->wdc_channel.ch_queue == NULL) { 178 printf("%s: can't allocate memory for command queue", 179 sc->sc_wdcdev.sc_dev.dv_xname); 180 return; 181 } 182 wdcattach(&sc->wdc_channel); 183 } 184 185 static void 186 wdc_isa_dma_setup(sc) 187 struct wdc_isa_softc *sc; 188 { 189 bus_size_t maxsize; 190 191 if ((maxsize = isa_dmamaxsize(sc->sc_ic, sc->sc_drq)) < MAXPHYS) { 192 printf("%s: max DMA size %lu is less than required %d\n", 193 sc->sc_wdcdev.sc_dev.dv_xname, (u_long)maxsize, MAXPHYS); 194 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA; 195 return; 196 } 197 198 if (isa_dmamap_create(sc->sc_ic, sc->sc_drq, 199 MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 200 printf("%s: can't create map for drq %d\n", 201 sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq); 202 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA; 203 } 204 } 205 206 static int 207 wdc_isa_dma_init(v, channel, drive, databuf, datalen, read) 208 void *v; 209 void *databuf; 210 size_t datalen; 211 int read; 212 { 213 struct wdc_isa_softc *sc = v; 214 215 isa_dmastart(sc->sc_ic, sc->sc_drq, databuf, datalen, NULL, 216 (read ? DMAMODE_READ : DMAMODE_WRITE) | DMAMODE_DEMAND, 217 BUS_DMA_NOWAIT); 218 return 0; 219 } 220 221 static void 222 wdc_isa_dma_start(v, channel, drive) 223 void *v; 224 int channel, drive; 225 { 226 /* nothing to do */ 227 } 228 229 static int 230 wdc_isa_dma_finish(v, channel, drive, read) 231 void *v; 232 int channel, drive; 233 int read; 234 { 235 struct wdc_isa_softc *sc = v; 236 237 isa_dmadone(sc->sc_ic, sc->sc_drq); 238 return 0; 239 } 240
Indexes created Tue Oct 14 06:10:07 GMT 2025