wdc_isa.c revision 1.6.2.1
1 /* $NetBSD: wdc_isa.c,v 1.6.2.1 1998/06/04 16:54:11 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved. 5 * 6 * DMA and multi-sector PIO handling are derived from code contributed by 7 * Onno van der Linden. 8 * 9 * ISA attachment created by Christopher G. Demetriou. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Charles M. Hannum. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/types.h> 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/isa/isavar.h> 47 #include <dev/isa/isadmavar.h> 48 49 #include <dev/ata/atavar.h> 50 #include <dev/ic/wdcvar.h> 51 52 #define WDC_ISA_REG_NPORTS 8 53 #define WDC_ISA_AUXREG_OFFSET 0x206 54 #define WDC_ISA_AUXREG_NPORTS 1 /* XXX "fdc" owns ports 0x3f7/0x377 */ 55 56 /* 57 * XXX This code currently doesn't even try to allow 32-bit data port use. 58 */ 59 60 struct wdc_isa_softc { 61 struct wdc_softc sc_wdcdev; 62 struct channel_softc wdc_channel; 63 void *sc_ih; 64 int sc_drq; 65 }; 66 67 #ifdef __BROKEN_INDIRECT_CONFIG 68 int wdc_isa_probe __P((struct device *, void *, void *)); 69 #else 70 int wdc_isa_probe __P((struct device *, struct cfdata *, void *)); 71 #endif 72 void wdc_isa_attach __P((struct device *, struct device *, void *)); 73 74 struct cfattach wdc_isa_ca = { 75 sizeof(struct wdc_isa_softc), wdc_isa_probe, wdc_isa_attach 76 }; 77 78 static void wdc_isa_dma_setup __P((struct wdc_isa_softc *)); 79 static int wdc_isa_dma_init __P((void*, int, int, void *, size_t, int)); 80 static void wdc_isa_dma_start __P((void*, int, int, int)); 81 static int wdc_isa_dma_finish __P((void*, int, int, int)); 82 83 int 84 wdc_isa_probe(parent, match, aux) 85 struct device *parent; 86 #ifdef __BROKEN_INDIRECT_CONFIG 87 void *match; 88 #else 89 struct cfdata *match; 90 #endif 91 void *aux; 92 { 93 #if 0 /* XXX memset */ 94 struct channel_softc ch = { 0 }; 95 #else /* XXX memset */ 96 struct channel_softc ch; 97 #endif /* XXX memset */ 98 struct isa_attach_args *ia = aux; 99 int result = 0; 100 101 #if 0 /* XXX memset */ 102 #else /* XXX memset */ 103 bzero(&ch, sizeof ch); 104 #endif /* XXX memset */ 105 ch.cmd_iot = ia->ia_iot; 106 if (bus_space_map(ch.cmd_iot, ia->ia_iobase, WDC_ISA_REG_NPORTS, 0, 107 &ch.cmd_ioh)) 108 goto out; 109 110 ch.ctl_iot = ia->ia_iot; 111 if (bus_space_map(ch.ctl_iot, ia->ia_iobase + WDC_ISA_AUXREG_OFFSET, 112 WDC_ISA_AUXREG_NPORTS, 0, &ch.ctl_ioh)) 113 goto outunmap; 114 115 result = wdcprobe(&ch); 116 if (result) { 117 ia->ia_iosize = WDC_ISA_REG_NPORTS; 118 ia->ia_msize = 0; 119 } 120 121 bus_space_unmap(ch.ctl_iot, ch.ctl_ioh, WDC_ISA_AUXREG_NPORTS); 122 outunmap: 123 bus_space_unmap(ch.cmd_iot, ch.cmd_ioh, WDC_ISA_REG_NPORTS); 124 out: 125 return (result); 126 } 127 128 void 129 wdc_isa_attach(parent, self, aux) 130 struct device *parent, *self; 131 void *aux; 132 { 133 struct wdc_isa_softc *sc = (void *)self; 134 struct isa_attach_args *ia = aux; 135 136 printf("\n"); 137 138 sc->wdc_channel.cmd_iot = ia->ia_iot; 139 sc->wdc_channel.ctl_iot = ia->ia_iot; 140 if (bus_space_map(sc->wdc_channel.cmd_iot, ia->ia_iobase, 141 WDC_ISA_REG_NPORTS, 0, &sc->wdc_channel.cmd_ioh) || 142 bus_space_map(sc->wdc_channel.ctl_iot, 143 ia->ia_iobase + WDC_ISA_AUXREG_OFFSET, WDC_ISA_AUXREG_NPORTS, 144 0, &sc->wdc_channel.ctl_ioh)) { 145 printf("%s: couldn't map registers\n", 146 sc->sc_wdcdev.sc_dev.dv_xname); 147 } 148 149 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 150 IPL_BIO, wdcintr, &sc->wdc_channel); 151 152 if (ia->ia_drq != DRQUNK) { 153 sc->sc_drq = ia->ia_drq; 154 155 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 156 sc->sc_wdcdev.dma_arg = sc; 157 sc->sc_wdcdev.dma_init = wdc_isa_dma_init; 158 sc->sc_wdcdev.dma_start = wdc_isa_dma_start; 159 sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish; 160 wdc_isa_dma_setup(sc); 161 } 162 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32; 163 sc->sc_wdcdev.pio_mode = 0; 164 sc->sc_wdcdev.channels = &sc->wdc_channel; 165 sc->sc_wdcdev.nchannels = 1; 166 sc->wdc_channel.channel = 0; 167 sc->wdc_channel.wdc = &sc->sc_wdcdev; 168 sc->wdc_channel.ch_queue = malloc(sizeof(struct channel_queue), 169 M_DEVBUF, M_NOWAIT); 170 if (sc->wdc_channel.ch_queue == NULL) { 171 printf("%s: can't allocate memory for command queue", 172 sc->sc_wdcdev.sc_dev.dv_xname); 173 return; 174 } 175 wdcattach(&sc->wdc_channel); 176 } 177 178 static void 179 wdc_isa_dma_setup(sc) 180 struct wdc_isa_softc *sc; 181 { 182 if (isa_dmamap_create(sc->sc_wdcdev.sc_dev.dv_parent, sc->sc_drq, 183 MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 184 printf("%s: can't create map for drq %d\n", 185 sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq); 186 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA; 187 } 188 } 189 190 static int 191 wdc_isa_dma_init(v, channel, drive, databuf, datalen, read) 192 void *v; 193 void *databuf; 194 size_t datalen; 195 int read; 196 { 197 struct wdc_isa_softc *sc = v; 198 199 isa_dmastart(sc->sc_wdcdev.sc_dev.dv_parent, sc->sc_drq, databuf, 200 datalen, NULL, read ? DMAMODE_READ : DMAMODE_WRITE, 201 BUS_DMA_NOWAIT); 202 return 0; 203 } 204 205 static void 206 wdc_isa_dma_start(v, channel, drive, read) 207 void *v; 208 int channel, drive; 209 { 210 /* nothing to do */ 211 } 212 213 static int 214 wdc_isa_dma_finish(v, channel, drive, read) 215 void *v; 216 int channel, drive; 217 int read; 218 { 219 struct wdc_isa_softc *sc = v; 220 221 isa_dmadone(sc->sc_wdcdev.sc_dev.dv_parent, sc->sc_drq); 222 return 0; 223 } 224
Indexes created Tue Oct 14 06:10:07 GMT 2025