wdc_isa.c revision 1.60
1 /* $NetBSD: wdc_isa.c,v 1.60 2017/10/07 16:05:32 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: wdc_isa.c,v 1.60 2017/10/07 16:05:32 jdolecek Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <dev/isa/isavar.h> 44 #include <dev/isa/isadmavar.h> 45 46 #include <dev/ic/wdcreg.h> 47 #include <dev/ata/atavar.h> 48 #include <dev/ic/wdcvar.h> 49 50 #define WDC_ISA_REG_NPORTS 8 51 #define WDC_ISA_AUXREG_OFFSET 0x206 52 #define WDC_ISA_AUXREG_NPORTS 1 /* XXX "fdc" owns ports 0x3f7/0x377 */ 53 54 /* options passed via the 'flags' config keyword */ 55 #define WDC_OPTIONS_32 0x01 /* try to use 32bit data I/O */ 56 #define WDC_OPTIONS_ATA_NOSTREAM 0x04 57 #define WDC_OPTIONS_ATAPI_NOSTREAM 0x08 58 59 struct wdc_isa_softc { 60 struct wdc_softc sc_wdcdev; 61 struct ata_channel *wdc_chanlist[1]; 62 struct ata_channel ata_channel; 63 struct wdc_regs wdc_regs; 64 isa_chipset_tag_t sc_ic; 65 void *sc_ih; 66 int sc_drq; 67 }; 68 69 static int wdc_isa_probe(device_t , cfdata_t, void *); 70 static void wdc_isa_attach(device_t, device_t, void *); 71 static int wdc_isa_detach(device_t, int); 72 73 CFATTACH_DECL3_NEW(wdc_isa, sizeof(struct wdc_isa_softc), 74 wdc_isa_probe, wdc_isa_attach, wdc_isa_detach, NULL, NULL, 75 wdc_childdetached, DVF_DETACH_SHUTDOWN); 76 77 #if 0 78 static void wdc_isa_dma_setup(struct wdc_isa_softc *); 79 static int wdc_isa_dma_init(void*, int, int, void *, size_t, int); 80 static void wdc_isa_dma_start(void*, int, int); 81 static int wdc_isa_dma_finish(void*, int, int, int); 82 #endif 83 84 static int 85 wdc_isa_probe(device_t parent, cfdata_t match, void *aux) 86 { 87 struct isa_attach_args *ia = aux; 88 struct wdc_regs wdr; 89 int result = 0, i; 90 91 if (ia->ia_nio < 1) 92 return (0); 93 if (ia->ia_nirq < 1) 94 return (0); 95 96 if (ISA_DIRECT_CONFIG(ia)) 97 return (0); 98 99 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 100 return (0); 101 if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ) 102 return (0); 103 if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq == ISA_UNKNOWN_DRQ) 104 ia->ia_ndrq = 0; 105 106 wdr.cmd_iot = ia->ia_iot; 107 108 if (bus_space_map(wdr.cmd_iot, ia->ia_io[0].ir_addr, 109 WDC_ISA_REG_NPORTS, 0, &wdr.cmd_baseioh)) 110 goto out; 111 112 for (i = 0; i < WDC_ISA_REG_NPORTS; i++) { 113 if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i, 114 i == 0 ? 4 : 1, &wdr.cmd_iohs[i]) != 0) 115 goto outunmap; 116 } 117 wdc_init_shadow_regs(&wdr); 118 119 wdr.ctl_iot = ia->ia_iot; 120 if (bus_space_map(wdr.ctl_iot, ia->ia_io[0].ir_addr + 121 WDC_ISA_AUXREG_OFFSET, WDC_ISA_AUXREG_NPORTS, 0, &wdr.ctl_ioh)) 122 goto outunmap; 123 124 result = wdcprobe(&wdr); 125 if (result) { 126 ia->ia_nio = 1; 127 ia->ia_io[0].ir_size = WDC_ISA_REG_NPORTS; 128 129 ia->ia_nirq = 1; 130 131 ia->ia_niomem = 0; 132 } 133 134 bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_ISA_AUXREG_NPORTS); 135 outunmap: 136 bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_ISA_REG_NPORTS); 137 out: 138 return (result); 139 } 140 141 static int 142 wdc_isa_detach(device_t self, int flags) 143 { 144 struct wdc_isa_softc *sc = device_private(self); 145 struct wdc_regs *wdr = &sc->wdc_regs; 146 int rc; 147 148 if ((rc = wdcdetach(self, flags)) != 0) 149 return rc; 150 151 isa_intr_disestablish(sc->sc_ic, sc->sc_ih); 152 153 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, WDC_ISA_AUXREG_NPORTS); 154 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, WDC_ISA_REG_NPORTS); 155 156 return 0; 157 } 158 159 static void 160 wdc_isa_attach(device_t parent, device_t self, void *aux) 161 { 162 struct wdc_isa_softc *sc = device_private(self); 163 struct wdc_regs *wdr; 164 struct isa_attach_args *ia = aux; 165 int wdc_cf_flags = device_cfdata(self)->cf_flags; 166 int i; 167 168 sc->sc_wdcdev.sc_atac.atac_dev = self; 169 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs; 170 wdr->cmd_iot = ia->ia_iot; 171 wdr->ctl_iot = ia->ia_iot; 172 sc->sc_ic = ia->ia_ic; 173 if (bus_space_map(wdr->cmd_iot, ia->ia_io[0].ir_addr, 174 WDC_ISA_REG_NPORTS, 0, &wdr->cmd_baseioh) || 175 bus_space_map(wdr->ctl_iot, 176 ia->ia_io[0].ir_addr + WDC_ISA_AUXREG_OFFSET, 177 WDC_ISA_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) { 178 aprint_error(": couldn't map registers\n"); 179 return; 180 } 181 182 for (i = 0; i < WDC_ISA_REG_NPORTS; i++) { 183 if (bus_space_subregion(wdr->cmd_iot, 184 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 185 &wdr->cmd_iohs[i]) != 0) { 186 aprint_error(": couldn't subregion registers\n"); 187 return; 188 } 189 } 190 191 wdr->data32iot = wdr->cmd_iot; 192 wdr->data32ioh = wdr->cmd_iohs[0]; 193 194 #if 0 195 if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ) { 196 sc->sc_drq = ia->ia_drq[0].ir_drq; 197 198 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 199 sc->sc_wdcdev.dma_arg = sc; 200 sc->sc_wdcdev.dma_init = wdc_isa_dma_init; 201 sc->sc_wdcdev.dma_start = wdc_isa_dma_start; 202 sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish; 203 wdc_isa_dma_setup(sc); 204 } 205 #endif 206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA; 207 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 208 if (wdc_cf_flags & WDC_OPTIONS_32) 209 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32; 210 if (wdc_cf_flags & WDC_OPTIONS_ATA_NOSTREAM) 211 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATA_NOSTREAM; 212 if (wdc_cf_flags & WDC_OPTIONS_ATAPI_NOSTREAM) 213 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATAPI_NOSTREAM; 214 215 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 216 sc->wdc_chanlist[0] = &sc->ata_channel; 217 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist; 218 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 219 sc->sc_wdcdev.wdc_maxdrives = 2; 220 sc->ata_channel.ch_channel = 0; 221 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 222 sc->ata_channel.ch_queue = ata_queue_alloc(1); 223 wdc_init_shadow_regs(wdr); 224 225 aprint_normal("\n"); 226 227 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 228 IST_EDGE, IPL_BIO, wdcintr, &sc->ata_channel); 229 230 wdcattach(&sc->ata_channel); 231 } 232 233 #if 0 234 static void 235 wdc_isa_dma_setup(struct wdc_isa_softc *sc) 236 { 237 bus_size_t maxsize; 238 239 if ((maxsize = isa_dmamaxsize(sc->sc_ic, sc->sc_drq)) < MAXPHYS) { 240 aprint_error_dev(sc_wdcdev.sc_atac.atac_dev, 241 "max DMA size %lu is less than required %d\n", 242 (u_long)maxsize, MAXPHYS); 243 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 244 return; 245 } 246 247 if (isa_drq_alloc(sc->sc_ic, sc->sc_drq) != 0) { 248 aprint_error_dev(sc_wdcdev.sc_atac.atac_dev, 249 "can't reserve drq %d\n", sc->sc_drq); 250 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 251 return; 252 } 253 254 if (isa_dmamap_create(sc->sc_ic, sc->sc_drq, 255 MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 256 aprint_error_dev(sc_wdcdev.sc_atac.atac_dev, 257 "can't create map for drq %d\n", sc->sc_drq); 258 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 259 } 260 } 261 262 static int 263 wdc_isa_dma_init(void *v, int channel, int drive, void *databuf, 264 size_t datalen, int read) 265 { 266 struct wdc_isa_softc *sc = v; 267 268 isa_dmastart(sc->sc_ic, sc->sc_drq, databuf, datalen, NULL, 269 (read ? DMAMODE_READ : DMAMODE_WRITE) | DMAMODE_DEMAND, 270 BUS_DMA_NOWAIT); 271 return 0; 272 } 273 274 static void 275 wdc_isa_dma_start(void *v, int channel, int drive) 276 { 277 /* nothing to do */ 278 } 279 280 static int 281 wdc_isa_dma_finish(void *v, int channel, int drive, int read) 282 { 283 struct wdc_isa_softc *sc = v; 284 285 isa_dmadone(sc->sc_ic, sc->sc_drq); 286 return 0; 287 } 288 #endif 289
Indexes created Tue Sep 30 20:09:53 GMT 2025