gt.c revision 1.22
1 /* $NetBSD: gt.c,v 1.22 2010/02/25 23:34:54 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gt.c -- GT system controller driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.22 2010/02/25 23:34:54 matt Exp $"); 46 47 #include "opt_marvell.h" 48 #include "locators.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/extent.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/malloc.h> 56 57 #define _BUS_SPACE_PRIVATE 58 #define _BUS_DMA_PRIVATE 59 #include <sys/bus.h> 60 61 #include <powerpc/spr.h> 62 #include <powerpc/oea/hid.h> 63 #include <powerpc/oea/spr.h> 64 65 #include <dev/marvell/gtreg.h> 66 #include <dev/marvell/gtintrreg.h> 67 #include <dev/marvell/gtvar.h> 68 #include <dev/marvell/gtethreg.h> 69 70 #ifdef DEBUG 71 #include <sys/systm.h> /* for Debugger() */ 72 #endif 73 74 #if ((GT_MPP_WATCHDOG & 0xf0f0f0f0) != 0) 75 # error /* unqualified: configuration botch! */ 76 #endif 77 #if ((GT_MPP_WATCHDOG & GT_MPP_INTERRUPTS) != 0) 78 # error /* conflict: configuration botch! */ 79 #endif 80 81 static void gt_comm_intr_enb(struct gt_softc *); 82 static void gt_devbus_intr_enb(struct gt_softc *); 83 #ifdef GT_ECC 84 static void gt_ecc_intr_enb(struct gt_softc *); 85 #endif 86 87 88 void gt_init_hostid (struct gt_softc *); 89 void gt_init_interrupt (struct gt_softc *); 90 static int gt_comm_intr (void *); 91 92 void gt_watchdog_init(struct gt_softc *); 93 void gt_watchdog_enable(void); 94 void gt_watchdog_disable(void); 95 void gt_watchdog_reset(void); 96 97 extern struct cfdriver gt_cd; 98 99 static int gtfound = 0; 100 101 static struct gt_softc *gt_watchdog_sc = 0; 102 static int gt_watchdog_state = 0; 103 104 int 105 gt_cfprint (void *aux, const char *pnp) 106 { 107 struct gt_attach_args *ga = aux; 108 109 if (pnp) { 110 aprint_normal("%s at %s", ga->ga_name, pnp); 111 } 112 113 aprint_normal(" unit %d", ga->ga_unit); 114 return (UNCONF); 115 } 116 117 118 static int 119 gt_cfsearch(device_t parent, cfdata_t cf, 120 const int *ldesc, void *aux) 121 { 122 struct gt_softc *gt = (struct gt_softc *) parent; 123 struct gt_attach_args ga; 124 125 ga.ga_name = cf->cf_name; 126 ga.ga_dmat = gt->gt_dmat; 127 ga.ga_memt = gt->gt_memt; 128 ga.ga_memh = gt->gt_memh; 129 ga.ga_unit = cf->cf_loc[GTCF_UNIT]; 130 131 if (config_match(parent, cf, &ga) > 0) 132 config_attach(parent, cf, &ga, gt_cfprint); 133 134 return (0); 135 } 136 137 void 138 gt_attach_common(struct gt_softc *gt) 139 { 140 uint32_t cpucfg, cpumode, cpumstr; 141 #ifdef DEBUG 142 uint32_t loaddr, hiaddr; 143 #endif 144 145 gtfound = 1; 146 147 cpumode = gt_read(gt, GT_CPU_Mode); 148 aprint_normal(": id %d", GT_CPUMode_MultiGTID_GET(cpumode)); 149 if (cpumode & GT_CPUMode_MultiGT) 150 aprint_normal (" (multi)"); 151 switch (GT_CPUMode_CPUType_GET(cpumode)) { 152 case 4: aprint_normal(", 60x bus"); break; 153 case 5: aprint_normal(", MPX bus"); break; 154 default: aprint_normal(", %#x(?) bus", GT_CPUMode_CPUType_GET(cpumode)); break; 155 } 156 157 cpumstr = gt_read(gt, GT_CPU_Master_Ctl); 158 cpumstr &= ~(GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock); 159 #if 0 160 cpumstr |= GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock; 161 #endif 162 gt_write(gt, GT_CPU_Master_Ctl, cpumstr); 163 164 switch (cpumstr & (GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock)) { 165 case 0: break; 166 case GT_CPUMstrCtl_CleanBlock: aprint_normal(", snoop=clean"); break; 167 case GT_CPUMstrCtl_FlushBlock: aprint_normal(", snoop=flush"); break; 168 case GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock: 169 aprint_normal(", snoop=clean&flush"); break; 170 } 171 aprint_normal(" wdog=%#x,%#x\n", 172 gt_read(gt, GT_WDOG_Config), 173 gt_read(gt, GT_WDOG_Value)); 174 175 #if DEBUG 176 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS0_Low_Decode)); 177 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS0_High_Decode)); 178 aprint_normal_dev(>->gt_dev, " scs[0]=%#10x-%#10x\n", loaddr, hiaddr); 179 180 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS1_Low_Decode)); 181 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS1_High_Decode)); 182 aprint_normal_dev(>->gt_dev, " scs[1]=%#10x-%#10x\n", loaddr, hiaddr); 183 184 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS2_Low_Decode)); 185 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS2_High_Decode)); 186 aprint_normal_dev(>->gt_dev, " scs[2]=%#10x-%#10x\n", loaddr, hiaddr); 187 188 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS3_Low_Decode)); 189 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS3_High_Decode)); 190 aprint_normal_dev(>->gt_dev, " scs[3]=%#10x-%#10x\n", loaddr, hiaddr); 191 192 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS0_Low_Decode)); 193 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS0_High_Decode)); 194 aprint_normal_dev(>->gt_dev, " cs[0]=%#10x-%#10x\n", loaddr, hiaddr); 195 196 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS1_Low_Decode)); 197 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS1_High_Decode)); 198 aprint_normal_dev(>->gt_dev, " cs[1]=%#10x-%#10x\n", loaddr, hiaddr); 199 200 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS2_Low_Decode)); 201 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS2_High_Decode)); 202 aprint_normal_dev(>->gt_dev, " cs[2]=%#10x-%#10x\n", loaddr, hiaddr); 203 204 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS3_Low_Decode)); 205 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS3_High_Decode)); 206 aprint_normal_dev(>->gt_dev, " cs[3]=%#10x-%#10x\n", loaddr, hiaddr); 207 208 loaddr = GT_LowAddr_GET(gt_read(gt, GT_BootCS_Low_Decode)); 209 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_BootCS_High_Decode)); 210 aprint_normal_dev(>->gt_dev, " bootcs=%#10x-%#10x\n", loaddr, hiaddr); 211 212 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_IO_Low_Decode)); 213 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_IO_High_Decode)); 214 aprint_normal_dev(>->gt_dev, " pci0io=%#10x-%#10x ", loaddr, hiaddr); 215 216 loaddr = gt_read(gt, GT_PCI0_IO_Remap); 217 aprint_normal("remap=%#010x\n", loaddr); 218 219 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode)); 220 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode)); 221 aprint_normal_dev(>->gt_dev, " pci0mem[0]=%#10x-%#10x ", loaddr, hiaddr); 222 223 loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low); 224 hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High); 225 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 226 227 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode)); 228 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode)); 229 aprint_normal_dev(>->gt_dev, " pci0mem[1]=%#10x-%#10x ", loaddr, hiaddr); 230 231 loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low); 232 hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High); 233 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 234 235 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode)); 236 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode)); 237 aprint_normal_dev(>->gt_dev, " pci0mem[2]=%#10x-%#10x ", loaddr, hiaddr); 238 239 loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low); 240 hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High); 241 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 242 243 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode)); 244 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode)); 245 aprint_normal_dev(>->gt_dev, " pci0mem[3]=%#10x-%#10x ", loaddr, hiaddr); 246 247 loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low); 248 hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High); 249 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 250 251 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_IO_Low_Decode)); 252 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_IO_High_Decode)); 253 aprint_normal_dev(>->gt_dev, " pci1io=%#10x-%#10x ", loaddr, hiaddr); 254 255 loaddr = gt_read(gt, GT_PCI1_IO_Remap); 256 aprint_normal("remap=%#010x\n", loaddr); 257 258 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode)); 259 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode)); 260 aprint_normal_dev(>->gt_dev, " pci1mem[0]=%#10x-%#10x ", loaddr, hiaddr); 261 262 loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low); 263 hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High); 264 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 265 266 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode)); 267 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode)); 268 aprint_normal_dev(>->gt_dev, " pci1mem[1]=%#10x-%#10x ", loaddr, hiaddr); 269 270 loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low); 271 hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High); 272 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 273 274 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode)); 275 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode)); 276 aprint_normal_dev(>->gt_dev, " pci1mem[2]=%#10x-%#10x ", loaddr, hiaddr); 277 278 loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low); 279 hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High); 280 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 281 282 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode)); 283 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode)); 284 aprint_normal_dev(>->gt_dev, " pci1mem[3]=%#10x-%#10x ", loaddr, hiaddr); 285 286 loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low); 287 hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High); 288 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 289 290 loaddr = GT_LowAddr_GET(gt_read(gt, GT_Internal_Decode)); 291 aprint_normal_dev(>->gt_dev, " internal=%#10x-%#10x\n", 292 loaddr, loaddr+256*1024); 293 294 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU0_Low_Decode)); 295 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU0_High_Decode)); 296 aprint_normal_dev(>->gt_dev, " cpu0=%#10x-%#10x\n", loaddr, hiaddr); 297 298 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU1_Low_Decode)); 299 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU1_High_Decode)); 300 aprint_normal_dev(>->gt_dev, " cpu1=%#10x-%#10x", loaddr, hiaddr); 301 #endif 302 303 aprint_normal_dev(>->gt_dev, ""); 304 305 cpucfg = gt_read(gt, GT_CPU_Cfg); 306 cpucfg |= GT_CPUCfg_ConfSBDis; /* per errata #46 */ 307 cpucfg |= GT_CPUCfg_AACKDelay; /* per restriction #18 */ 308 gt_write(gt, GT_CPU_Cfg, cpucfg); 309 if (cpucfg & GT_CPUCfg_Pipeline) 310 aprint_normal(" pipeline"); 311 if (cpucfg & GT_CPUCfg_AACKDelay) 312 aprint_normal(" aack-delay"); 313 if (cpucfg & GT_CPUCfg_RdOOO) 314 aprint_normal(" read-ooo"); 315 if (cpucfg & GT_CPUCfg_IOSBDis) 316 aprint_normal(" io-sb-dis"); 317 if (cpucfg & GT_CPUCfg_ConfSBDis) 318 aprint_normal(" conf-sb-dis"); 319 if (cpucfg & GT_CPUCfg_ClkSync) 320 aprint_normal(" clk-sync"); 321 aprint_normal("\n"); 322 323 gt_init_hostid(gt); 324 325 gt_watchdog_init(gt); 326 327 gt_init_interrupt(gt); 328 329 #ifdef GT_ECC 330 gt_ecc_intr_enb(gt); 331 #endif 332 333 gt_comm_intr_enb(gt); 334 gt_devbus_intr_enb(gt); 335 336 gt_watchdog_disable(); 337 config_search_ia(gt_cfsearch, >->gt_dev, "gt", NULL); 338 gt_watchdog_service(); 339 gt_watchdog_enable(); 340 } 341 342 void 343 gt_init_hostid(struct gt_softc *gt) 344 { 345 346 hostid = 1; /* XXX: Used by i2c; needs work -- AKB */ 347 } 348 349 void 350 gt_init_interrupt(struct gt_softc *gt) 351 { 352 u_int32_t mppirpts = GT_MPP_INTERRUPTS; /* from config */ 353 u_int32_t r; 354 u_int32_t mppbit; 355 u_int32_t mask; 356 u_int32_t mppsel; 357 u_int32_t regoff; 358 359 gt_write(gt, ICR_CIM_LO, 0); 360 gt_write(gt, ICR_CIM_HI, 0); 361 362 /* 363 * configure the GPP interrupts: 364 * - set the configured MPP pins in GPP mode 365 * - set the configured GPP pins to input, active low, interrupt enbl 366 */ 367 #ifdef DEBUG 368 printf("%s: mpp cfg ", device_xname(>->gt_dev)); 369 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) 370 printf("%#x ", gt_read(gt, regoff)); 371 printf(", mppirpts 0x%x\n", mppirpts); 372 #endif 373 mppbit = 0x1; 374 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 375 mask = 0; 376 for (mppsel = 0xf; mppsel; mppsel <<= 4) { 377 if (mppirpts & mppbit) 378 mask |= mppsel; 379 mppbit <<= 1; 380 } 381 if (mask) { 382 r = gt_read(gt, regoff); 383 r &= ~mask; 384 gt_write(gt, regoff, r); 385 } 386 } 387 388 r = gt_read(gt, GT_GPP_IO_Control); 389 r &= ~mppirpts; 390 gt_write(gt, GT_GPP_IO_Control, r); 391 392 r = gt_read(gt, GT_GPP_Level_Control); 393 r |= mppirpts; 394 gt_write(gt, GT_GPP_Level_Control, r); 395 396 r = gt_read(gt, GT_GPP_Interrupt_Mask); 397 r |= mppirpts; 398 gt_write(gt, GT_GPP_Interrupt_Mask, r); 399 } 400 401 uint32_t 402 gt_read_mpp (void) 403 { 404 struct gt_softc *sc = device_lookup_private(>_cd, 0); 405 return gt_read(sc, GT_GPP_Value); /* XXX */ 406 } 407 408 #if 0 409 int 410 gt_bs_extent_init(struct discovery_bus_space *bs, char *name) 411 { 412 u_long start, end; 413 int i, j, error; 414 415 if (bs->bs_nregion == 0) { 416 bs->bs_extent = extent_create(name, 0xffffffffUL, 0xffffffffUL, 417 M_DEVBUF, NULL, 0, EX_NOCOALESCE|EX_WAITOK); 418 KASSERT(bs->bs_extent != NULL); 419 return 0; 420 } 421 /* 422 * Find the top and bottoms of this bus space. 423 */ 424 start = bs->bs_regions[0].br_start; 425 end = bs->bs_regions[0].br_end; 426 #ifdef DEBUG 427 if (gtpci_debug > 1) 428 printf("gtpci_bs_extent_init: %s: region %d: %#lx-%#lx\n", 429 name, 0, bs->bs_regions[0].br_start, 430 bs->bs_regions[0].br_end); 431 #endif 432 for (i = 1; i < bs->bs_nregion; i++) { 433 if (bs->bs_regions[i].br_start < start) 434 start = bs->bs_regions[i].br_start; 435 if (bs->bs_regions[i].br_end > end) 436 end = bs->bs_regions[i].br_end; 437 #ifdef DEBUG 438 if (gtpci_debug > 1) 439 printf("gtpci_bs_extent_init: %s: region %d:" 440 " %#lx-%#lx\n", 441 name, i, bs->bs_regions[i].br_start, 442 bs->bs_regions[i].br_end); 443 #endif 444 } 445 /* 446 * Now that we have the top and bottom limits of this 447 * bus space, create the extent map that will manage this 448 * space for us. 449 */ 450 #ifdef DEBUG 451 if (gtpci_debug > 1) 452 printf("gtpci_bs_extent_init: %s: create: %#lx-%#lx\n", 453 name, start, end); 454 #endif 455 bs->bs_extent = extent_create(name, start, end, M_DEVBUF, 456 NULL, 0, EX_NOCOALESCE|EX_WAITOK); 457 KASSERT(bs->bs_extent != NULL); 458 459 /* If there was more than one bus space region, then there 460 * might gaps in between them. Allocate the gap so that 461 * they will not be legal addresses in the extent. 462 */ 463 for (i = 0; i < bs->bs_nregion && bs->bs_nregion > 1; i++) { 464 /* Initial start is "infinity" and the inital end is 465 * is the end of this bus region. 466 */ 467 start = ~0UL; 468 end = bs->bs_regions[i].br_end; 469 /* For each region, if it starts after this region but less 470 * than the saved start, use its start address. If the start 471 * address is one past the end address, then we're done 472 */ 473 for (j = 0; j < bs->bs_nregion && start > end + 1; j++) { 474 if (i == j) 475 continue; 476 if (bs->bs_regions[j].br_start > end && 477 bs->bs_regions[j].br_start < start) 478 start = bs->bs_regions[j].br_start; 479 } 480 /* 481 * If we found a gap, allocate it away. 482 */ 483 if (start != ~0UL && start != end + 1) { 484 #ifdef DEBUG 485 if (gtpci_debug > 1) 486 printf("gtpci_bs_extent_init: %s: alloc(hole): %#lx-%#lx\n", 487 name, end + 1, start - 1); 488 #endif 489 error = extent_alloc_region(bs->bs_extent, end + 1, 490 start - (end + 1), EX_NOWAIT); 491 KASSERT(error == 0); 492 } 493 } 494 return 1; 495 } 496 #endif 497 498 /* 499 * unknown board, enable everything 500 */ 501 # define GT_CommUnitIntr_DFLT GT_CommUnitIntr_S0|GT_CommUnitIntr_S1 \ 502 |GT_CommUnitIntr_E0|GT_CommUnitIntr_E1 \ 503 |GT_CommUnitIntr_E2 504 505 static const char * const gt_comm_subunit_name[8] = { 506 "ethernet 0", 507 "ethernet 1", 508 "ethernet 2", 509 "(reserved)", 510 "MPSC 0", 511 "MPSC 1", 512 "(reserved)", 513 "(sel)", 514 }; 515 516 static int 517 gt_comm_intr(void *arg) 518 { 519 struct gt_softc *gt = (struct gt_softc *)arg; 520 u_int32_t cause; 521 u_int32_t addr; 522 unsigned int mask; 523 int i; 524 525 cause = gt_read(gt, GT_CommUnitIntr_Cause); 526 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 527 addr = gt_read(gt, GT_CommUnitIntr_ErrAddr); 528 529 printf("%s: Comm Unit irpt, cause %#x addr %#x\n", 530 device_xname(>->gt_dev), cause, addr); 531 532 cause &= GT_CommUnitIntr_DFLT; 533 if (cause == 0) 534 return 0; 535 536 mask = 0x7; 537 for (i=0; i<7; i++) { 538 if (cause & mask) { 539 printf("%s: Comm Unit %s:", device_xname(>->gt_dev), 540 gt_comm_subunit_name[i]); 541 if (cause & 1) 542 printf(" AddrMiss"); 543 if (cause & 2) 544 printf(" AccProt"); 545 if (cause & 4) 546 printf(" WrProt"); 547 printf("\n"); 548 } 549 cause >>= 4; 550 } 551 return 1; 552 } 553 554 /* 555 * gt_comm_intr_init - enable GT-64260 Comm Unit interrupts 556 */ 557 static void 558 gt_comm_intr_enb(struct gt_softc *gt) 559 { 560 u_int32_t cause; 561 562 cause = gt_read(gt, GT_CommUnitIntr_Cause); 563 if (cause) 564 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 565 gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT); 566 (void)gt_read(gt, GT_CommUnitIntr_ErrAddr); 567 568 intr_establish(IRQ_COMM, IST_LEVEL, IPL_VM, gt_comm_intr, gt); 569 printf("%s: Comm Unit irpt at %d\n", device_xname(>->gt_dev), IRQ_COMM); 570 } 571 572 #ifdef GT_ECC 573 static char *gt_ecc_intr_str[4] = { 574 "(none)", 575 "single bit", 576 "double bit", 577 "(reserved)" 578 }; 579 580 static int 581 gt_ecc_intr(void *arg) 582 { 583 struct gt_softc *gt = (struct gt_softc *)arg; 584 u_int32_t addr; 585 u_int32_t dlo; 586 u_int32_t dhi; 587 u_int32_t rec; 588 u_int32_t calc; 589 u_int32_t count; 590 int err; 591 592 count = gt_read(gt, GT_ECC_Count); 593 dlo = gt_read(gt, GT_ECC_Data_Lo); 594 dhi = gt_read(gt, GT_ECC_Data_Hi); 595 rec = gt_read(gt, GT_ECC_Rec); 596 calc = gt_read(gt, GT_ECC_Calc); 597 addr = gt_read(gt, GT_ECC_Addr); /* read last! */ 598 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 599 600 err = addr & 0x3; 601 602 printf("%s: ECC error: %s: " 603 "addr %#x data %#x.%#x rec %#x calc %#x cnt %#x\n", 604 device_xname(>->gt_dev), gt_ecc_intr_str[err], 605 addr, dhi, dlo, rec, calc, count); 606 607 if (err == 2) 608 panic("ecc"); 609 610 return (err == 1); 611 } 612 613 /* 614 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 615 */ 616 static void 617 gt_ecc_intr_enb(struct gt_softc *gt) 618 { 619 u_int32_t ctl; 620 621 ctl = gt_read(gt, GT_ECC_Ctl); 622 ctl |= 1 << 16; /* XXX 1-bit threshold == 1 */ 623 gt_write(gt, GT_ECC_Ctl, ctl); 624 (void)gt_read(gt, GT_ECC_Data_Lo); 625 (void)gt_read(gt, GT_ECC_Data_Hi); 626 (void)gt_read(gt, GT_ECC_Rec); 627 (void)gt_read(gt, GT_ECC_Calc); 628 (void)gt_read(gt, GT_ECC_Addr); /* read last! */ 629 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 630 631 intr_establish(IRQ_ECC, IST_LEVEL, IPL_VM, gt_ecc_intr, gt); 632 printf("%s: ECC irpt at %d\n", device_xname(>->gt_dev), IRQ_ECC); 633 } 634 #endif /* GT_ECC */ 635 636 637 #ifndef GT_MPP_WATCHDOG 638 void 639 gt_watchdog_init(struct gt_softc *gt) 640 { 641 u_int32_t r; 642 unsigned int omsr; 643 644 omsr = extintr_disable(); 645 646 printf("%s: watchdog", device_xname(>->gt_dev)); 647 648 /* 649 * handle case where firmware started watchdog 650 */ 651 r = gt_read(gt, GT_WDOG_Config); 652 printf(" status %#x,%#x:", 653 r, gt_read(gt, GT_WDOG_Value)); 654 if ((r & 0x80000000) != 0) { 655 gt_watchdog_sc = gt; /* enabled */ 656 gt_watchdog_state = 1; 657 printf(" firmware-enabled\n"); 658 gt_watchdog_service(); 659 return; 660 } else { 661 printf(" firmware-disabled\n"); 662 } 663 664 extintr_restore(omsr); 665 } 666 667 #else /* GT_MPP_WATCHDOG */ 668 669 void 670 gt_watchdog_init(struct gt_softc *gt) 671 { 672 u_int32_t mpp_watchdog = GT_MPP_WATCHDOG; /* from config */ 673 u_int32_t r; 674 u_int32_t cfgbits; 675 u_int32_t mppbits; 676 u_int32_t mppmask=0; 677 u_int32_t regoff; 678 unsigned int omsr; 679 680 printf("%s: watchdog", device_xname(>->gt_dev)); 681 682 if (mpp_watchdog == 0) { 683 printf(" not configured\n"); 684 return; 685 } 686 687 #if 0 688 if (afw_wdog_ctl == 1) { 689 printf(" admin disabled\n"); 690 return; 691 } 692 #endif 693 694 omsr = extintr_disable(); 695 696 /* 697 * if firmware started watchdog, we disable and start 698 * from scratch to get it in a known state. 699 * 700 * on GT-64260A we always see 0xffffffff 701 * in both the GT_WDOG_Config_Enb and GT_WDOG_Value regsiters. 702 * Use AFW-supplied flag to determine run state. 703 */ 704 r = gt_read(gt, GT_WDOG_Config); 705 if (r != ~0) { 706 if ((r & GT_WDOG_Config_Enb) != 0) { 707 gt_write(gt, GT_WDOG_Config, 708 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 709 gt_write(gt, GT_WDOG_Config, 710 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 711 } 712 } else { 713 #if 0 714 if (afw_wdog_state == 1) { 715 gt_write(gt, GT_WDOG_Config, 716 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 717 gt_write(gt, GT_WDOG_Config, 718 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 719 } 720 #endif 721 } 722 723 /* 724 * "the watchdog timer can be activated only after 725 * configuring two MPP pins to act as WDE and WDNMI" 726 */ 727 mppbits = 0; 728 cfgbits = 0x3; 729 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 730 if ((mpp_watchdog & cfgbits) == cfgbits) { 731 mppbits = 0x99; 732 mppmask = 0xff; 733 break; 734 } 735 cfgbits <<= 2; 736 if ((mpp_watchdog & cfgbits) == cfgbits) { 737 mppbits = 0x9900; 738 mppmask = 0xff00; 739 break; 740 } 741 cfgbits <<= 6; /* skip unqualified bits */ 742 } 743 if (mppbits == 0) { 744 printf(" config error\n"); 745 extintr_restore(omsr); 746 return; 747 } 748 749 r = gt_read(gt, regoff); 750 r &= ~mppmask; 751 r |= mppbits; 752 gt_write(gt, regoff, r); 753 printf(" mpp %#x %#x", regoff, mppbits); 754 755 gt_write(gt, GT_WDOG_Value, GT_WDOG_NMI_DFLT); 756 757 gt_write(gt, GT_WDOG_Config, 758 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 759 gt_write(gt, GT_WDOG_Config, 760 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 761 762 763 r = gt_read(gt, GT_WDOG_Config), 764 printf(" status %#x,%#x: %s", 765 r, gt_read(gt, GT_WDOG_Value), 766 ((r & GT_WDOG_Config_Enb) != 0) ? "enabled" : "botch"); 767 768 if ((r & GT_WDOG_Config_Enb) != 0) { 769 register_t hid0; 770 771 gt_watchdog_sc = gt; /* enabled */ 772 gt_watchdog_state = 1; 773 774 /* 775 * configure EMCP in HID0 in case it's not already set 776 */ 777 __asm volatile("sync"); 778 hid0 = mfspr(SPR_HID0); 779 if ((hid0 & HID0_EMCP) == 0) { 780 hid0 |= HID0_EMCP; 781 __asm volatile("sync"); mtspr(SPR_HID0, hid0); 782 __asm volatile("sync"); hid0 = mfspr(SPR_HID0); 783 printf(", EMCP set"); 784 } 785 } 786 printf("\n"); 787 788 extintr_restore(omsr); 789 } 790 #endif /* GT_MPP_WATCHDOG */ 791 792 #ifdef DEBUG 793 u_int32_t hid0_print(void); 794 u_int32_t 795 hid0_print() 796 { 797 u_int32_t hid0; 798 __asm volatile("sync; mfspr %0,1008;" : "=r"(hid0)); 799 printf("hid0: %#x\n", hid0); 800 return hid0; 801 } 802 #endif 803 804 void 805 gt_watchdog_enable(void) 806 { 807 struct gt_softc *gt; 808 unsigned int omsr; 809 810 omsr = extintr_disable(); 811 gt = gt_watchdog_sc; 812 if ((gt != NULL) && (gt_watchdog_state == 0)) { 813 gt_watchdog_state = 1; 814 815 gt_write(gt, GT_WDOG_Config, 816 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 817 gt_write(gt, GT_WDOG_Config, 818 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 819 } 820 extintr_restore(omsr); 821 } 822 823 void 824 gt_watchdog_disable(void) 825 { 826 struct gt_softc *gt; 827 unsigned int omsr; 828 829 omsr = extintr_disable(); 830 gt = gt_watchdog_sc; 831 if ((gt != NULL) && (gt_watchdog_state != 0)) { 832 gt_watchdog_state = 0; 833 834 gt_write(gt, GT_WDOG_Config, 835 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 836 gt_write(gt, GT_WDOG_Config, 837 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 838 } 839 extintr_restore(omsr); 840 } 841 842 #ifdef DEBUG 843 int inhibit_watchdog_service = 0; 844 #endif 845 void 846 gt_watchdog_service(void) 847 { 848 struct gt_softc *gt = gt_watchdog_sc; 849 850 if ((gt == NULL) || (gt_watchdog_state == 0)) 851 return; /* not enabled */ 852 #ifdef DEBUG 853 if (inhibit_watchdog_service) 854 return; 855 #endif 856 857 gt_write(gt, GT_WDOG_Config, 858 (GT_WDOG_Config_Ctl2a | GT_WDOG_Preset_DFLT)); 859 gt_write(gt, GT_WDOG_Config, 860 (GT_WDOG_Config_Ctl2b | GT_WDOG_Preset_DFLT)); 861 } 862 863 /* 864 * gt_watchdog_reset - force a watchdog reset using Preset_VAL=0 865 */ 866 void 867 gt_watchdog_reset(void) 868 { 869 struct gt_softc *gt = gt_watchdog_sc; 870 u_int32_t r; 871 872 (void)extintr_disable(); 873 r = gt_read(gt, GT_WDOG_Config); 874 gt_write(gt, GT_WDOG_Config, (GT_WDOG_Config_Ctl1a | 0)); 875 gt_write(gt, GT_WDOG_Config, (GT_WDOG_Config_Ctl1b | 0)); 876 if ((r & GT_WDOG_Config_Enb) != 0) { 877 /* 878 * was enabled, we just toggled it off, toggle on again 879 */ 880 gt_write(gt, GT_WDOG_Config, 881 (GT_WDOG_Config_Ctl1a | 0)); 882 gt_write(gt, GT_WDOG_Config, 883 (GT_WDOG_Config_Ctl1b | 0)); 884 } 885 for(;;); 886 } 887 888 static int 889 gt_devbus_intr(void *arg) 890 { 891 struct gt_softc *gt = (struct gt_softc *)arg; 892 u_int32_t cause; 893 u_int32_t addr; 894 895 cause = gt_read(gt, GT_DEVBUS_ICAUSE); 896 addr = gt_read(gt, GT_DEVBUS_ERR_ADDR); 897 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear irpt */ 898 899 if (cause & GT_DEVBUS_DBurstErr) { 900 printf("%s: Device Bus error: burst violation", 901 device_xname(>->gt_dev)); 902 if ((cause & GT_DEVBUS_Sel) == 0) 903 printf(", addr %#x", addr); 904 printf("\n"); 905 } 906 if (cause & GT_DEVBUS_DRdyErr) { 907 printf("%s: Device Bus error: ready timer expired", 908 device_xname(>->gt_dev)); 909 if ((cause & GT_DEVBUS_Sel) != 0) 910 printf(", addr %#x\n", addr); 911 printf("\n"); 912 } 913 914 return (cause != 0); 915 } 916 917 /* 918 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 919 */ 920 static void 921 gt_devbus_intr_enb(struct gt_softc *gt) 922 { 923 gt_write(gt, GT_DEVBUS_IMASK, 924 GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr); 925 (void)gt_read(gt, GT_DEVBUS_ERR_ADDR); /* clear addr */ 926 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 927 928 intr_establish(IRQ_DEV, IST_LEVEL, IPL_VM, gt_devbus_intr, gt); 929 printf("%s: Device Bus Error irpt at %d\n", 930 device_xname(>->gt_dev), IRQ_DEV); 931 } 932 933 934 int 935 gt_mii_read( 936 device_t child, 937 device_t parent, 938 int phy, 939 int reg) 940 { 941 struct gt_softc * const gt = (struct gt_softc *) parent; 942 uint32_t data; 943 int count = 10000; 944 945 do { 946 DELAY(10); 947 data = gt_read(gt, ETH_ESMIR); 948 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 949 950 if (count == 0) { 951 printf("%s: mii read for phy %d reg %d busied out\n", 952 device_xname(child), phy, reg); 953 return ETH_ESMIR_Value_GET(data); 954 } 955 956 gt_write(gt, ETH_ESMIR, ETH_ESMIR_READ(phy, reg)); 957 958 count = 10000; 959 do { 960 DELAY(10); 961 data = gt_read(gt, ETH_ESMIR); 962 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 963 964 if (count == 0) 965 printf("%s: mii read for phy %d reg %d timed out\n", 966 device_xname(child), phy, reg); 967 #if defined(GTMIIDEBUG) 968 printf("%s: mii_read(%d, %d): %#x data %#x\n", 969 device_xname(child), phy, reg, 970 data, ETH_ESMIR_Value_GET(data)); 971 #endif 972 return ETH_ESMIR_Value_GET(data); 973 } 974 975 void 976 gt_mii_write ( 977 device_t child, 978 device_t parent, 979 int phy, int reg, 980 int value) 981 { 982 struct gt_softc * const gt = (struct gt_softc *) parent; 983 uint32_t data; 984 int count = 10000; 985 986 do { 987 DELAY(10); 988 data = gt_read(gt, ETH_ESMIR); 989 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 990 991 if (count == 0) { 992 printf("%s: mii write for phy %d reg %d busied out (busy)\n", 993 device_xname(child), phy, reg); 994 return; 995 } 996 997 gt_write(gt, ETH_ESMIR, 998 ETH_ESMIR_WRITE(phy, reg, value)); 999 1000 count = 10000; 1001 do { 1002 DELAY(10); 1003 data = gt_read(gt, ETH_ESMIR); 1004 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 1005 1006 if (count == 0) 1007 printf("%s: mii write for phy %d reg %d timed out\n", 1008 device_xname(child), phy, reg); 1009 #if defined(GTMIIDEBUG) 1010 printf("%s: mii_write(%d, %d, %#x)\n", 1011 device_xname(child), phy, reg, value); 1012 #endif 1013 } 1014 1015 /* 1016 * Since the memory and pci spaces are mapped 1:1 we just need 1017 * to return unity here 1018 */ 1019 bus_addr_t 1020 gt_dma_phys_to_bus_mem(bus_dma_tag_t t, bus_addr_t a) 1021 { 1022 return a; 1023 } 1024 bus_addr_t 1025 gt_dma_bus_mem_to_phys(bus_dma_tag_t t, bus_addr_t a) 1026 { 1027 return a; 1028 } 1029
Indexes created Sun Oct 19 16:10:00 GMT 2025