gt.c revision 1.24
1 /* $NetBSD: gt.c,v 1.24 2010/06/09 02:19:51 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gt.c -- GT system controller driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.24 2010/06/09 02:19:51 kiyohara Exp $"); 46 47 #include "opt_marvell.h" 48 #include "gtmpsc.h" 49 #include "opt_multiprocessor.h" 50 #include "locators.h" 51 52 #include <sys/param.h> 53 #include <sys/bus.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/types.h> 57 58 #include <dev/marvell/gtintrreg.h> 59 #include <dev/marvell/gtsdmareg.h> 60 #if NGTMPSC > 0 61 #include <dev/marvell/gtmpscreg.h> 62 #include <dev/marvell/gtmpscvar.h> 63 #endif 64 #include <dev/marvell/gtpcireg.h> 65 #include <dev/marvell/gtreg.h> 66 #include <dev/marvell/gtvar.h> 67 #include <dev/marvell/marvellreg.h> 68 #include <dev/marvell/marvellvar.h> 69 70 #include <dev/pci/pcireg.h> 71 72 #if ((GT_MPP_WATCHDOG & 0xf0f0f0f0) != 0) 73 # error /* unqualified: configuration botch! */ 74 #endif 75 76 #define gt_read(sc,r) bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (r)) 77 #define gt_write(sc,r,v) bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (v)) 78 79 80 static int gt_cfprint(void *, const char *); 81 static int gt_cfsearch(device_t, cfdata_t, const int *, void *); 82 static void gt_attach_peripherals(struct gt_softc *); 83 84 #ifdef GT_DEVBUS 85 static int gt_devbus_intr(void *); 86 static void gt_devbus_intr_enb(struct gt_softc *); 87 #endif 88 #ifdef GT_ECC 89 static int gt_ecc_intr(void *); 90 static void gt_ecc_intr_enb(struct gt_softc *); 91 #endif 92 #if NGTMPSC > 0 93 static void gt_sdma_intr_enb(struct gt_softc *); 94 #endif 95 #ifdef GT_COMM 96 static int gt_comm_intr(void *); 97 static void gt_comm_intr_enb(struct gt_softc *); 98 #endif 99 100 101 #ifdef GT_WATCHDOG 102 static void gt_watchdog_init(struct gt_softc *); 103 static void gt_watchdog_enable(struct gt_softc *); 104 #ifndef GT_MPP_WATCHDOG 105 static void gt_watchdog_disable(struct gt_softc *); 106 #endif 107 108 static struct gt_softc *gt_watchdog_sc = NULL; 109 static int gt_watchdog_state = 0; 110 #endif 111 112 113 #define OFFSET_DEFAULT GTCF_OFFSET_DEFAULT 114 #define IRQ_DEFAULT GTCF_IRQ_DEFAULT 115 static const struct gt_dev { 116 int model; 117 const char *name; 118 int unit; 119 bus_size_t offset; 120 int irq; 121 } gt_devs[] = { 122 { MARVELL_DISCOVERY, "gfec", 0, 0x0000, IRQ_DEFAULT }, 123 { MARVELL_DISCOVERY, "gtidmac", 0, 0x0000, 4 /*...7 */ }, 124 { MARVELL_DISCOVERY, "gtmpsc", 0, 0x8000, 40 }, 125 { MARVELL_DISCOVERY, "gtmpsc", 1, 0x9000, 42 }, 126 { MARVELL_DISCOVERY, "gtpci", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 127 { MARVELL_DISCOVERY, "gtpci", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 128 { MARVELL_DISCOVERY, "gttwsi", 0, 0xc000, 37 }, 129 { MARVELL_DISCOVERY, "obio", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 130 { MARVELL_DISCOVERY, "obio", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 131 { MARVELL_DISCOVERY, "obio", 2, OFFSET_DEFAULT, IRQ_DEFAULT }, 132 { MARVELL_DISCOVERY, "obio", 3, OFFSET_DEFAULT, IRQ_DEFAULT }, 133 { MARVELL_DISCOVERY, "obio", 4, OFFSET_DEFAULT, IRQ_DEFAULT }, 134 135 { MARVELL_DISCOVERY_II, "gtidmac", 0, 0x0000, 4 /*...7 */ }, 136 { MARVELL_DISCOVERY_II, "gtmpsc", 0, 0x8000, 40 }, 137 { MARVELL_DISCOVERY_II, "gtmpsc", 1, 0x9000, 42 }, 138 { MARVELL_DISCOVERY_II, "gtpci", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 139 { MARVELL_DISCOVERY_II, "gtpci", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 140 { MARVELL_DISCOVERY_II, "gttwsi", 0, 0xc000, 37 }, 141 { MARVELL_DISCOVERY_II, "mvgbec", 0, 0x0000, IRQ_DEFAULT }, 142 143 { MARVELL_DISCOVERY_III,"gtidmac", 0, 0x0000, 4 /*...7 */ }, 144 { MARVELL_DISCOVERY_III,"gtmpsc", 0, 0x8000, 40 }, 145 { MARVELL_DISCOVERY_III,"gtmpsc", 1, 0x9000, 42 }, 146 { MARVELL_DISCOVERY_III,"gtpci", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 147 { MARVELL_DISCOVERY_III,"gtpci", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 148 { MARVELL_DISCOVERY_III,"gttwsi", 0, 0xc000, 37 }, 149 { MARVELL_DISCOVERY_III,"mvgbec", 0, 0x0000, IRQ_DEFAULT }, 150 }; 151 152 153 static int 154 gt_cfprint(void *aux, const char *pnp) 155 { 156 struct marvell_attach_args *mva = aux; 157 158 if (pnp) 159 aprint_normal("%s at %s unit %d", 160 mva->mva_name, pnp, mva->mva_unit); 161 else { 162 if (mva->mva_unit != GTCF_UNIT_DEFAULT) 163 aprint_normal(" unit %d", mva->mva_unit); 164 if (mva->mva_offset != GTCF_OFFSET_DEFAULT) { 165 aprint_normal(" offset 0x%04x", mva->mva_offset); 166 if (mva->mva_size > 0) 167 aprint_normal("-0x%04x", 168 mva->mva_offset + mva->mva_size - 1); 169 } 170 if (mva->mva_irq != GTCF_IRQ_DEFAULT) 171 aprint_normal(" irq %d", mva->mva_irq); 172 } 173 174 return UNCONF; 175 } 176 177 178 /* ARGSUSED */ 179 static int 180 gt_cfsearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 181 { 182 struct marvell_attach_args *mva = aux; 183 184 if (cf->cf_loc[GTCF_IRQ] != GTCF_IRQ_DEFAULT) 185 mva->mva_irq = cf->cf_loc[GTCF_IRQ]; 186 187 return config_match(parent, cf, aux); 188 } 189 190 static void 191 gt_attach_peripherals(struct gt_softc *sc) 192 { 193 struct marvell_attach_args mva; 194 int i; 195 196 for (i = 0; i < __arraycount(gt_devs); i++) { 197 if (gt_devs[i].model != sc->sc_model) 198 continue; 199 200 mva.mva_name = gt_devs[i].name; 201 mva.mva_model = sc->sc_model; 202 mva.mva_revision = sc->sc_rev; 203 mva.mva_iot = sc->sc_iot; 204 mva.mva_ioh = sc->sc_ioh; 205 mva.mva_unit = gt_devs[i].unit; 206 mva.mva_addr = sc->sc_addr; 207 mva.mva_offset = gt_devs[i].offset; 208 mva.mva_size = 0; 209 mva.mva_dmat = sc->sc_dmat; 210 mva.mva_irq = gt_devs[i].irq; 211 212 config_found_sm_loc(sc->sc_dev, "gt", NULL, &mva, 213 gt_cfprint, gt_cfsearch); 214 } 215 } 216 217 void 218 gt_attach_common(struct gt_softc *gt) 219 { 220 uint32_t cpucfg, cpumode, cpumstr; 221 #ifdef GT_DEBUG 222 uint32_t loaddr, hiaddr; 223 #endif 224 225 gt_write(gt, GTPCI_CA(0), PCI_ID_REG); 226 gt->sc_model = PCI_PRODUCT(gt_read(gt, GTPCI_CD(0))); 227 gt_write(gt, GTPCI_CA(0), PCI_CLASS_REG); 228 gt->sc_rev = PCI_REVISION(gt_read(gt, GTPCI_CD(0))); 229 230 aprint_naive("\n"); 231 switch (gt->sc_model) { 232 case MARVELL_DISCOVERY: 233 aprint_normal(": GT-6426x%c Discovery\n", 234 (gt->sc_rev == MARVELL_DISCOVERY_REVA) ? 'A' : 'B'); 235 break; 236 case MARVELL_DISCOVERY_II: 237 aprint_normal(": MV6436x Discovery II\n"); 238 break; 239 240 case MARVELL_DISCOVERY_III: 241 aprint_normal(": MV6446x Discovery III\n"); 242 break; 243 #if 0 244 case MARVELL_DISCOVERY_LT: 245 case MARVELL_DISCOVERY_V: 246 case MARVELL_DISCOVERY_VI: 247 #endif 248 249 default: 250 aprint_normal(": type unknown\n"); break; 251 } 252 253 cpumode = gt_read(gt, GT_CPU_Mode); 254 aprint_normal_dev(gt->sc_dev, 255 "id %d", GT_CPUMode_MultiGTID_GET(cpumode)); 256 if (cpumode & GT_CPUMode_MultiGT) 257 aprint_normal (" (multi)"); 258 switch (GT_CPUMode_CPUType_GET(cpumode)) { 259 case 4: aprint_normal(", 60x bus"); break; 260 case 5: aprint_normal(", MPX bus"); break; 261 262 default: 263 aprint_normal(", %#x(?) bus", GT_CPUMode_CPUType_GET(cpumode)); 264 break; 265 } 266 267 cpumstr = gt_read(gt, GT_CPU_Master_Ctl); 268 switch (cpumstr & (GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock)) { 269 case 0: break; 270 case GT_CPUMstrCtl_CleanBlock: aprint_normal(", snoop=clean"); break; 271 case GT_CPUMstrCtl_FlushBlock: aprint_normal(", snoop=flush"); break; 272 case GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock: 273 aprint_normal(", snoop=clean&flush"); break; 274 } 275 aprint_normal(" wdog=%#x,%#x\n", 276 gt_read(gt, GT_WDOG_Config), gt_read(gt, GT_WDOG_Value)); 277 278 #ifdef GT_DEBUG 279 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS0_Low_Decode), gt->sc_model); 280 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS0_High_Decode), gt->sc_model); 281 aprint_normal_dev(gt->sc_dev, " scs[0]=%#10x-%#10x\n", 282 loaddr, hiaddr); 283 284 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS1_Low_Decode), gt->sc_model); 285 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS1_High_Decode), gt->sc_model); 286 aprint_normal_dev(gt->sc_dev, " scs[1]=%#10x-%#10x\n", 287 loaddr, hiaddr); 288 289 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS2_Low_Decode), gt->sc_model); 290 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS2_High_Decode), gt->sc_model); 291 aprint_normal_dev(gt->sc_dev, " scs[2]=%#10x-%#10x\n", 292 loaddr, hiaddr); 293 294 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS3_Low_Decode), gt->sc_model); 295 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS3_High_Decode), gt->sc_model); 296 aprint_normal_dev(gt->sc_dev, " scs[3]=%#10x-%#10x\n", 297 loaddr, hiaddr); 298 299 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS0_Low_Decode), gt->sc_model); 300 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS0_High_Decode), gt->sc_model); 301 aprint_normal_dev(gt->sc_dev, " cs[0]=%#10x-%#10x\n", 302 loaddr, hiaddr); 303 304 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS1_Low_Decode), gt->sc_model); 305 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS1_High_Decode), gt->sc_model); 306 aprint_normal_dev(gt->sc_dev, " cs[1]=%#10x-%#10x\n", 307 loaddr, hiaddr); 308 309 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS2_Low_Decode), gt->sc_model); 310 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS2_High_Decode), gt->sc_model); 311 aprint_normal_dev(gt->sc_dev, " cs[2]=%#10x-%#10x\n", 312 loaddr, hiaddr); 313 314 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS3_Low_Decode), gt->sc_model); 315 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS3_High_Decode), gt->sc_model); 316 aprint_normal_dev(gt->sc_dev, " cs[3]=%#10x-%#10x\n", 317 loaddr, hiaddr); 318 319 loaddr = GT_LADDR_GET(gt_read(gt, GT_BootCS_Low_Decode), gt->sc_model); 320 hiaddr = GT_HADDR_GET(gt_read(gt, GT_BootCS_High_Decode), gt->sc_model); 321 aprint_normal_dev(gt->sc_dev, " bootcs=%#10x-%#10x\n", 322 loaddr, hiaddr); 323 324 loaddr = GT_LADDR_GET(gt_read(gt, GT_PCI0_IO_Low_Decode), gt->sc_model); 325 hiaddr = 326 GT_HADDR_GET(gt_read(gt, GT_PCI0_IO_High_Decode), gt->sc_model); 327 aprint_normal_dev(gt->sc_dev, " pci0io=%#10x-%#10x ", 328 loaddr, hiaddr); 329 330 loaddr = gt_read(gt, GT_PCI0_IO_Remap); 331 aprint_normal("remap=%#010x\n", loaddr); 332 333 loaddr = 334 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode), gt->sc_model); 335 hiaddr = 336 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode), gt->sc_model); 337 aprint_normal_dev(gt->sc_dev, " pci0mem[0]=%#10x-%#10x ", 338 loaddr, hiaddr); 339 340 loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low); 341 hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High); 342 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 343 344 loaddr = 345 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode), gt->sc_model); 346 hiaddr = 347 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode), gt->sc_model); 348 aprint_normal_dev(gt->sc_dev, " pci0mem[1]=%#10x-%#10x ", 349 loaddr, hiaddr); 350 351 loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low); 352 hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High); 353 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 354 355 loaddr = 356 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode), gt->sc_model); 357 hiaddr = 358 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode), gt->sc_model); 359 aprint_normal_dev(gt->sc_dev, " pci0mem[2]=%#10x-%#10x ", 360 loaddr, hiaddr); 361 362 loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low); 363 hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High); 364 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 365 366 loaddr = 367 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode), gt->sc_model); 368 hiaddr = 369 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode), gt->sc_model); 370 aprint_normal_dev(gt->sc_dev, " pci0mem[3]=%#10x-%#10x ", 371 loaddr, hiaddr); 372 373 loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low); 374 hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High); 375 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 376 377 loaddr = GT_LADDR_GET(gt_read(gt, GT_PCI1_IO_Low_Decode), gt->sc_model); 378 hiaddr = 379 GT_HADDR_GET(gt_read(gt, GT_PCI1_IO_High_Decode), gt->sc_model); 380 aprint_normal_dev(gt->sc_dev, " pci1io=%#10x-%#10x ", 381 loaddr, hiaddr); 382 383 loaddr = gt_read(gt, GT_PCI1_IO_Remap); 384 aprint_normal("remap=%#010x\n", loaddr); 385 386 loaddr = 387 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode), gt->sc_model); 388 hiaddr = 389 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode), gt->sc_model); 390 aprint_normal_dev(gt->sc_dev, " pci1mem[0]=%#10x-%#10x ", 391 loaddr, hiaddr); 392 393 loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low); 394 hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High); 395 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 396 397 loaddr = 398 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode), gt->sc_model); 399 hiaddr = 400 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode), gt->sc_model); 401 aprint_normal_dev(gt->sc_dev, " pci1mem[1]=%#10x-%#10x ", 402 loaddr, hiaddr); 403 404 loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low); 405 hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High); 406 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 407 408 loaddr = 409 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode), gt->sc_model); 410 hiaddr = 411 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode), gt->sc_model); 412 aprint_normal_dev(gt->sc_dev, " pci1mem[2]=%#10x-%#10x ", 413 loaddr, hiaddr); 414 415 loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low); 416 hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High); 417 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 418 419 loaddr = 420 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode), gt->sc_model); 421 hiaddr = 422 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode), gt->sc_model); 423 aprint_normal_dev(gt->sc_dev, " pci1mem[3]=%#10x-%#10x ", 424 loaddr, hiaddr); 425 426 loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low); 427 hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High); 428 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 429 430 loaddr = GT_LADDR_GET(gt_read(gt, GT_Internal_Decode), gt->sc_model); 431 aprint_normal_dev(gt->sc_dev, " internal=%#10x-%#10x\n", 432 loaddr, loaddr + 256 * 1024); 433 434 loaddr = GT_LADDR_GET(gt_read(gt, GT_CPU0_Low_Decode), gt->sc_model); 435 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CPU0_High_Decode), gt->sc_model); 436 aprint_normal_dev(gt->sc_dev, " cpu0=%#10x-%#10x\n", 437 loaddr, hiaddr); 438 439 #ifdef MULTIPROCESSOR 440 loaddr = GT_LADDR_GET(gt_read(gt, GT_CPU1_Low_Decode), gt->sc_model); 441 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CPU1_High_Decode), gt->sc_model); 442 aprint_normal_dev(gt->sc_dev, " cpu1=%#10x-%#10x", 443 loaddr, hiaddr); 444 #endif 445 #endif 446 447 aprint_normal("%s:", device_xname(gt->sc_dev)); 448 449 cpucfg = gt_read(gt, GT_CPU_Cfg); 450 cpucfg |= GT_CPUCfg_ConfSBDis; /* per errata #46 */ 451 cpucfg |= GT_CPUCfg_AACKDelay; /* per restriction #18 */ 452 gt_write(gt, GT_CPU_Cfg, cpucfg); 453 if (cpucfg & GT_CPUCfg_Pipeline) 454 aprint_normal(" pipeline"); 455 if (cpucfg & GT_CPUCfg_AACKDelay) 456 aprint_normal(" aack-delay"); 457 if (cpucfg & GT_CPUCfg_RdOOO) 458 aprint_normal(" read-ooo"); 459 if (cpucfg & GT_CPUCfg_IOSBDis) 460 aprint_normal(" io-sb-dis"); 461 if (cpucfg & GT_CPUCfg_ConfSBDis) 462 aprint_normal(" conf-sb-dis"); 463 if (cpucfg & GT_CPUCfg_ClkSync) 464 aprint_normal(" clk-sync"); 465 aprint_normal("\n"); 466 467 #ifdef GT_WATCHDOG 468 gt_watchdog_init(gt); 469 #endif 470 471 #ifdef GT_DEVBUS 472 gt_devbus_intr_enb(gt); 473 #endif 474 #ifdef GT_ECC 475 gt_ecc_intr_enb(gt); 476 #endif 477 #if NGTMPSC > 0 478 gt_sdma_intr_enb(gt); 479 #endif 480 #ifdef GT_COMM 481 gt_comm_intr_enb(gt); 482 #endif 483 484 gt_attach_peripherals(gt); 485 486 #ifdef GT_WATCHDOG 487 gt_watchdog_service(); 488 gt_watchdog_enable(gt); 489 #endif 490 } 491 492 493 #ifdef GT_DEVBUS 494 static int 495 gt_devbus_intr(void *arg) 496 { 497 struct gt_softc *gt = (struct gt_softc *)arg; 498 u_int32_t cause; 499 u_int32_t addr; 500 501 cause = gt_read(gt, GT_DEVBUS_ICAUSE); 502 addr = gt_read(gt, GT_DEVBUS_ERR_ADDR); 503 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear intr */ 504 505 if (cause & GT_DEVBUS_DBurstErr) { 506 aprint_error_dev(gt->sc_dev, 507 "Device Bus error: burst violation"); 508 if ((cause & GT_DEVBUS_Sel) == 0) 509 aprint_error(", addr %#x", addr); 510 aprint_error("\n"); 511 } 512 if (cause & GT_DEVBUS_DRdyErr) { 513 aprint_error_dev(gt->sc_dev, 514 "Device Bus error: ready timer expired"); 515 if ((cause & GT_DEVBUS_Sel) != 0) 516 aprint_error(", addr %#x\n", addr); 517 aprint_error("\n"); 518 } 519 520 return cause != 0; 521 } 522 523 /* 524 * gt_devbus_intr_enb - enable GT-64260 Device Bus interrupts 525 */ 526 static void 527 gt_devbus_intr_enb(struct gt_softc *gt) 528 { 529 gt_write(gt, GT_DEVBUS_IMASK, 530 GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr); 531 (void)gt_read(gt, GT_DEVBUS_ERR_ADDR); /* clear addr */ 532 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear intr */ 533 534 (void)marvell_intr_establish(IRQ_DEV, IPL_VM, gt_devbus_intr, gt); 535 } 536 #endif /* GT_DEVBUS */ 537 538 #ifdef GT_ECC 539 const static char *gt_ecc_intr_str[4] = { 540 "(none)", 541 "single bit", 542 "double bit", 543 "(reserved)" 544 }; 545 546 static int 547 gt_ecc_intr(void *arg) 548 { 549 struct gt_softc *gt = (struct gt_softc *)arg; 550 uint32_t addr, dlo, dhi, rec, calc, count; 551 int err; 552 553 count = gt_read(gt, GT_ECC_Count); 554 dlo = gt_read(gt, GT_ECC_Data_Lo); 555 dhi = gt_read(gt, GT_ECC_Data_Hi); 556 rec = gt_read(gt, GT_ECC_Rec); 557 calc = gt_read(gt, GT_ECC_Calc); 558 addr = gt_read(gt, GT_ECC_Addr); /* read last! */ 559 gt_write(gt, GT_ECC_Addr, 0); /* clear intr */ 560 561 err = addr & 0x3; 562 563 aprint_error_dev(gt->sc_dev, 564 "ECC error: %s: addr %#x data %#x.%#x rec %#x calc %#x cnt %#x\n", 565 gt_ecc_intr_str[err], addr, dhi, dlo, rec, calc, count); 566 567 if (err == 2) 568 panic("ecc"); 569 570 return err == 1; 571 } 572 573 /* 574 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 575 */ 576 static void 577 gt_ecc_intr_enb(struct gt_softc *gt) 578 { 579 uint32_t ctl; 580 581 ctl = gt_read(gt, GT_ECC_Ctl); 582 ctl |= 1 << 16; /* XXX 1-bit threshold == 1 */ 583 gt_write(gt, GT_ECC_Ctl, ctl); 584 (void)gt_read(gt, GT_ECC_Data_Lo); 585 (void)gt_read(gt, GT_ECC_Data_Hi); 586 (void)gt_read(gt, GT_ECC_Rec); 587 (void)gt_read(gt, GT_ECC_Calc); 588 (void)gt_read(gt, GT_ECC_Addr); /* read last! */ 589 gt_write(gt, GT_ECC_Addr, 0); /* clear intr */ 590 591 (void)marvell_intr_establish(IRQ_ECC, IPL_VM, gt_ecc_intr, gt); 592 } 593 #endif /* GT_ECC */ 594 595 #if NGTMPSC > 0 596 /* 597 * gt_sdma_intr_enb - enable GT-64260 SDMA interrupts 598 */ 599 static void 600 gt_sdma_intr_enb(struct gt_softc *gt) 601 { 602 603 (void)marvell_intr_establish(IRQ_SDMA, IPL_SERIAL, gtmpsc_intr, gt); 604 } 605 #endif 606 607 #ifdef GT_COMM 608 /* 609 * unknown board, enable everything 610 */ 611 # define GT_CommUnitIntr_DFLT \ 612 GT_CommUnitIntr_S0 |\ 613 GT_CommUnitIntr_S1 |\ 614 GT_CommUnitIntr_E0 |\ 615 GT_CommUnitIntr_E1 |\ 616 GT_CommUnitIntr_E2 617 618 static const char * const gt_comm_subunit_name[8] = { 619 "ethernet 0", 620 "ethernet 1", 621 "ethernet 2", 622 "(reserved)", 623 "MPSC 0", 624 "MPSC 1", 625 "(reserved)", 626 "(sel)", 627 }; 628 629 static int 630 gt_comm_intr(void *arg) 631 { 632 struct gt_softc *gt = (struct gt_softc *)arg; 633 uint32_t cause, addr; 634 unsigned int mask; 635 int i; 636 637 cause = gt_read(gt, GT_CommUnitIntr_Cause); 638 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 639 addr = gt_read(gt, GT_CommUnitIntr_ErrAddr); 640 641 aprint_error_dev(gt->sc_dev, 642 "Communications Unit Controller interrupt, cause %#x addr %#x\n", 643 cause, addr); 644 645 cause &= GT_CommUnitIntr_DFLT; 646 if (cause == 0) 647 return 0; 648 649 mask = 0x7; 650 for (i=0; i<7; i++) { 651 if (cause & mask) { 652 printf("%s: Comm Unit %s:", device_xname(gt->sc_dev), 653 gt_comm_subunit_name[i]); 654 if (cause & 1) 655 printf(" AddrMiss"); 656 if (cause & 2) 657 printf(" AccProt"); 658 if (cause & 4) 659 printf(" WrProt"); 660 printf("\n"); 661 } 662 cause >>= 4; 663 } 664 return 1; 665 } 666 667 /* 668 * gt_comm_intr_init - enable GT-64260 Comm Unit interrupts 669 */ 670 static void 671 gt_comm_intr_enb(struct gt_softc *gt) 672 { 673 uint32_t cause; 674 675 cause = gt_read(gt, GT_CommUnitIntr_Cause); 676 if (cause) 677 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 678 gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT); 679 (void)gt_read(gt, GT_CommUnitIntr_ErrAddr); 680 681 (void)marvell_intr_establish(IRQ_COMM, IPL_VM, gt_comm_intr, gt); 682 } 683 #endif /* GT_COMM */ 684 685 686 #ifdef GT_WATCHDOG 687 #ifndef GT_MPP_WATCHDOG 688 static void 689 gt_watchdog_init(struct gt_softc *gt) 690 { 691 u_int32_t r; 692 693 aprint_normal_dev(gt->sc_dev, "watchdog"); 694 695 /* 696 * handle case where firmware started watchdog 697 */ 698 r = gt_read(gt, GT_WDOG_Config); 699 aprint_normal(" status %#x,%#x:", r, gt_read(gt, GT_WDOG_Value)); 700 if ((r & 0x80000000) != 0) { 701 gt_watchdog_sc = gt; /* enabled */ 702 gt_watchdog_state = 1; 703 aprint_normal(" firmware-enabled\n"); 704 gt_watchdog_disable(gt); 705 } else 706 aprint_normal(" firmware-disabled\n"); 707 } 708 709 #elif GT_MPP_WATCHDOG == 0 710 711 static void 712 gt_watchdog_init(struct gt_softc *gt) 713 { 714 715 aprint_normal_dev(gt->sc_dev, "watchdog not configured\n"); 716 return; 717 } 718 719 #else /* GT_MPP_WATCHDOG > 0 */ 720 721 static void 722 gt_watchdog_init(struct gt_softc *gt) 723 { 724 u_int32_t mpp_watchdog = GT_MPP_WATCHDOG; /* from config */ 725 u_int32_t cfgbits, mppbits, mppmask, regoff, r; 726 727 mppmask = 0; 728 729 aprint_normal_dev(gt->sc_dev, "watchdog"); 730 731 /* 732 * if firmware started watchdog, we disable and start 733 * from scratch to get it in a known state. 734 * 735 * on GT-64260A we always see 0xffffffff 736 * in both the GT_WDOG_Config_Enb and GT_WDOG_Value regsiters. 737 */ 738 r = gt_read(gt, GT_WDOG_Config); 739 if (r != ~0) { 740 if ((r & GT_WDOG_Config_Enb) != 0) { 741 gt_write(gt, GT_WDOG_Config, 742 GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT); 743 gt_write(gt, GT_WDOG_Config, 744 GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT); 745 } 746 } 747 748 /* 749 * "the watchdog timer can be activated only after 750 * configuring two MPP pins to act as WDE and WDNMI" 751 */ 752 mppbits = 0; 753 cfgbits = 0x3; 754 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 755 if ((mpp_watchdog & cfgbits) == cfgbits) { 756 mppbits = 0x99; 757 mppmask = 0xff; 758 break; 759 } 760 cfgbits <<= 2; 761 if ((mpp_watchdog & cfgbits) == cfgbits) { 762 mppbits = 0x9900; 763 mppmask = 0xff00; 764 break; 765 } 766 cfgbits <<= 6; /* skip unqualified bits */ 767 } 768 if (mppbits == 0) { 769 aprint_error(" config error\n"); 770 return; 771 } 772 773 r = gt_read(gt, regoff); 774 r &= ~mppmask; 775 r |= mppbits; 776 gt_write(gt, regoff, r); 777 aprint_normal(" mpp %#x %#x", regoff, mppbits); 778 779 gt_write(gt, GT_WDOG_Value, GT_WDOG_NMI_DFLT); 780 781 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a|GT_WDOG_Preset_DFLT); 782 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b|GT_WDOG_Preset_DFLT); 783 784 r = gt_read(gt, GT_WDOG_Config), 785 aprint_normal(" status %#x,%#x: %s\n", 786 r, gt_read(gt, GT_WDOG_Value), 787 ((r & GT_WDOG_Config_Enb) != 0) ? "enabled" : "botch"); 788 } 789 #endif /* GT_MPP_WATCHDOG */ 790 791 static void 792 gt_watchdog_enable(struct gt_softc *gt) 793 { 794 795 if (gt_watchdog_state == 0) { 796 gt_watchdog_state = 1; 797 798 gt_write(gt, GT_WDOG_Config, 799 GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT); 800 gt_write(gt, GT_WDOG_Config, 801 GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT); 802 } 803 } 804 805 #ifndef GT_MPP_WATCHDOG 806 static void 807 gt_watchdog_disable(struct gt_softc *gt) 808 { 809 810 if (gt_watchdog_state != 0) { 811 gt_watchdog_state = 0; 812 813 gt_write(gt, GT_WDOG_Config, 814 GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT); 815 gt_write(gt, GT_WDOG_Config, 816 GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT); 817 } 818 } 819 #endif 820 821 /* 822 * XXXX: gt_watchdog_service/reset functions need mutex lock... 823 */ 824 825 #ifdef GT_DEBUG 826 int inhibit_watchdog_service = 0; 827 #endif 828 void 829 gt_watchdog_service(void) 830 { 831 struct gt_softc *gt = gt_watchdog_sc; 832 833 if ((gt == NULL) || (gt_watchdog_state == 0)) 834 return; /* not enabled */ 835 #ifdef GT_DEBUG 836 if (inhibit_watchdog_service) 837 return; 838 #endif 839 840 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl2a|GT_WDOG_Preset_DFLT); 841 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl2b|GT_WDOG_Preset_DFLT); 842 } 843 844 /* 845 * gt_watchdog_reset - force a watchdog reset using Preset_VAL=0 846 */ 847 void 848 gt_watchdog_reset(void) 849 { 850 struct gt_softc *gt = gt_watchdog_sc; 851 u_int32_t r; 852 853 r = gt_read(gt, GT_WDOG_Config); 854 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a); 855 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b); 856 if ((r & GT_WDOG_Config_Enb) != 0) { 857 /* 858 * was enabled, we just toggled it off, toggle on again 859 */ 860 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a); 861 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b); 862 } 863 for(;;); 864 } 865 #endif 866 867 868 int 869 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attr, 870 uint64_t *base, uint32_t *size) 871 { 872 static const struct { 873 int tag; 874 uint32_t attribute; 875 uint32_t basereg; 876 uint32_t sizereg; 877 } tagtbl[] = { 878 { MARVELL_TAG_SDRAM_CS0, MARVELL_ATTR_SDRAM_CS0, 879 GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 880 { MARVELL_TAG_SDRAM_CS1, MARVELL_ATTR_SDRAM_CS1, 881 GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 882 { MARVELL_TAG_SDRAM_CS2, MARVELL_ATTR_SDRAM_CS2, 883 GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 884 { MARVELL_TAG_SDRAM_CS3, MARVELL_ATTR_SDRAM_CS3, 885 GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 886 887 { MARVELL_TAG_UNDEFINED, 0, 0 } 888 }; 889 struct gt_softc *sc = device_private(dev); 890 int i; 891 892 for (i = 0; tagtbl[i].tag != MARVELL_TAG_UNDEFINED; i++) 893 if (tag == tagtbl[i].tag) 894 break; 895 if (tagtbl[i].tag == MARVELL_TAG_UNDEFINED) 896 return -1; 897 898 if (target != NULL) 899 *target = 0; 900 if (attr != NULL) 901 *attr = tagtbl[i].attribute; 902 if (base != NULL) 903 *base = gt_read(sc, tagtbl[i].basereg) << 904 (sc->sc_model == MARVELL_DISCOVERY ? 20 : 16); 905 if (size != NULL) { 906 const uint32_t s = gt_read(sc, tagtbl[i].sizereg); 907 908 if (s != 0) 909 *size = (s + 1) << 910 (sc->sc_model == MARVELL_DISCOVERY ? 20 : 16); 911 else 912 *size = 0; 913 } 914 915 return 0; 916 } 917
Indexes created Wed Sep 24 05:09:52 GMT 2025