gt.c revision 1.28.32.1
1 /* $NetBSD: gt.c,v 1.28.32.1 2021/03/22 02:01:01 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gt.c -- GT system controller driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.28.32.1 2021/03/22 02:01:01 thorpej Exp $"); 46 47 #include "opt_marvell.h" 48 #include "gtmpsc.h" 49 #include "opt_multiprocessor.h" 50 #include "locators.h" 51 52 #include <sys/param.h> 53 #include <sys/bus.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/types.h> 57 58 #include <dev/marvell/gtintrreg.h> 59 #include <dev/marvell/gtsdmareg.h> 60 #if NGTMPSC > 0 61 #include <dev/marvell/gtmpscreg.h> 62 #include <dev/marvell/gtmpscvar.h> 63 #endif 64 #include <dev/marvell/gtpcireg.h> 65 #include <dev/marvell/gtreg.h> 66 #include <dev/marvell/gtvar.h> 67 #include <dev/marvell/marvellreg.h> 68 #include <dev/marvell/marvellvar.h> 69 70 #include <dev/pci/pcireg.h> 71 72 #if ((GT_MPP_WATCHDOG & 0xf0f0f0f0) != 0) 73 # error /* unqualified: configuration botch! */ 74 #endif 75 76 #define gt_read(sc,r) bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (r)) 77 #define gt_write(sc,r,v) bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (v)) 78 79 80 static int gt_cfprint(void *, const char *); 81 static int gt_cfsearch(device_t, cfdata_t, const int *, void *); 82 static void gt_attach_peripherals(struct gt_softc *); 83 84 #ifdef GT_DEVBUS 85 static int gt_devbus_intr(void *); 86 static void gt_devbus_intr_enb(struct gt_softc *); 87 #endif 88 #ifdef GT_ECC 89 static int gt_ecc_intr(void *); 90 static void gt_ecc_intr_enb(struct gt_softc *); 91 #endif 92 #if NGTMPSC > 0 93 static void gt_sdma_intr_enb(struct gt_softc *); 94 #endif 95 #ifdef GT_COMM 96 static int gt_comm_intr(void *); 97 static void gt_comm_intr_enb(struct gt_softc *); 98 #endif 99 100 101 #ifdef GT_WATCHDOG 102 static void gt_watchdog_init(struct gt_softc *); 103 static void gt_watchdog_enable(struct gt_softc *); 104 #ifndef GT_MPP_WATCHDOG 105 static void gt_watchdog_disable(struct gt_softc *); 106 #endif 107 108 static struct gt_softc *gt_watchdog_sc = NULL; 109 static int gt_watchdog_state = 0; 110 #endif 111 112 113 #define OFFSET_DEFAULT MVA_OFFSET_DEFAULT 114 #define IRQ_DEFAULT MVA_IRQ_DEFAULT 115 static const struct gt_dev { 116 int model; 117 const char *name; 118 int unit; 119 bus_size_t offset; 120 int irq; 121 } gt_devs[] = { 122 { MARVELL_DISCOVERY, "gfec", 0, 0x0000, IRQ_DEFAULT }, 123 { MARVELL_DISCOVERY, "gtidmac", 0, 0x0000, 4 /*...7 */ }, 124 { MARVELL_DISCOVERY, "gtmpsc", 0, 0x8000, 40 }, 125 { MARVELL_DISCOVERY, "gtmpsc", 1, 0x9000, 42 }, 126 { MARVELL_DISCOVERY, "gtpci", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 127 { MARVELL_DISCOVERY, "gtpci", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 128 { MARVELL_DISCOVERY, "gttwsi", 0, 0xc000, 37 }, 129 { MARVELL_DISCOVERY, "obio", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 130 { MARVELL_DISCOVERY, "obio", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 131 { MARVELL_DISCOVERY, "obio", 2, OFFSET_DEFAULT, IRQ_DEFAULT }, 132 { MARVELL_DISCOVERY, "obio", 3, OFFSET_DEFAULT, IRQ_DEFAULT }, 133 { MARVELL_DISCOVERY, "obio", 4, OFFSET_DEFAULT, IRQ_DEFAULT }, 134 135 { MARVELL_DISCOVERY_II, "gtidmac", 0, 0x0000, 4 /*...7 */ }, 136 { MARVELL_DISCOVERY_II, "gtmpsc", 0, 0x8000, 40 }, 137 { MARVELL_DISCOVERY_II, "gtmpsc", 1, 0x9000, 42 }, 138 { MARVELL_DISCOVERY_II, "gtpci", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 139 { MARVELL_DISCOVERY_II, "gtpci", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 140 { MARVELL_DISCOVERY_II, "gttwsi", 0, 0xc000, 37 }, 141 { MARVELL_DISCOVERY_II, "mvgbec", 0, 0x0000, IRQ_DEFAULT }, 142 143 { MARVELL_DISCOVERY_III,"gtidmac", 0, 0x0000, 4 /*...7 */ }, 144 { MARVELL_DISCOVERY_III,"gtmpsc", 0, 0x8000, 40 }, 145 { MARVELL_DISCOVERY_III,"gtmpsc", 1, 0x9000, 42 }, 146 { MARVELL_DISCOVERY_III,"gtpci", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 147 { MARVELL_DISCOVERY_III,"gtpci", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 148 { MARVELL_DISCOVERY_III,"gttwsi", 0, 0xc000, 37 }, 149 { MARVELL_DISCOVERY_III,"mvgbec", 0, 0x0000, IRQ_DEFAULT }, 150 151 #if 0 /* XXXXXX: from www.marvell.com */ 152 /* Discovery LT (Discovery Light) MV644[23]0 */ 153 { MARVELL_DISCOVERY_LT, "gtidmac", 0, 0x?000, ? /*...? */ }, 154 { MARVELL_DISCOVERY_LT, "gtmpsc", 0, 0x?000, ? }, 155 { MARVELL_DISCOVERY_LT, "gtmpsc", 1, 0x?000, ? }, 156 { MARVELL_DISCOVERY_LT, "gtpci", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 157 { MARVELL_DISCOVERY_LT, "gtpci", 1, OFFSET_DEFAULT, IRQ_DEFAULT }, 158 { MARVELL_DISCOVERY_LT, "gttwsi", 0, 0x?000, ? }, 159 { MARVELL_DISCOVERY_LT, "mvgbec", 0, 0x?000, IRQ_DEFAULT }, 160 161 /* Discovery V MV64560 */ 162 { MARVELL_DISCOVERY_V, "com", ?, 0x?0000, ? }, 163 { MARVELL_DISCOVERY_V, "ehci", 0, 0x?0000, ? }, 164 { MARVELL_DISCOVERY_V, "ehci", 1, 0x?0000, ? }, 165 { MARVELL_DISCOVERY_V, "gtidmac", 0, 0x?0000, ? /*...? */ }, 166 { MARVELL_DISCOVERY_V, "gtpci", 0, 0x?0000, IRQ_DEFAULT }, 167 { MARVELL_DISCOVERY_V, "gttwsi", 0, 0x?0000, ? }, 168 { MARVELL_DISCOVERY_V, "mvgbec", 0, 0x?0000, IRQ_DEFAULT }, 169 { MARVELL_DISCOVERY_V, "mvpex or gtpci?", 0, 0x?0000, IRQ_DEFAULT }, 170 { MARVELL_DISCOVERY_V, "obio", 0, OFFSET_DEFAULT, IRQ_DEFAULT }, 171 172 /* Discovery VI MV64660 */ 173 /* MV64560 + SATA? */ 174 { MARVELL_DISCOVERY_VI, "mvsata", 0, 0x?0000, ? }, 175 #endif 176 }; 177 178 179 static int 180 gt_cfprint(void *aux, const char *pnp) 181 { 182 struct marvell_attach_args *mva = aux; 183 184 if (pnp) 185 aprint_normal("%s at %s unit %d", 186 mva->mva_name, pnp, mva->mva_unit); 187 else { 188 if (mva->mva_unit != MVA_UNIT_DEFAULT) 189 aprint_normal(" unit %d", mva->mva_unit); 190 if (mva->mva_offset != MVA_OFFSET_DEFAULT) { 191 aprint_normal(" offset 0x%04x", mva->mva_offset); 192 if (mva->mva_size > 0) 193 aprint_normal("-0x%04x", 194 mva->mva_offset + mva->mva_size - 1); 195 } 196 if (mva->mva_irq != MVA_IRQ_DEFAULT) 197 aprint_normal(" irq %d", mva->mva_irq); 198 } 199 200 return UNCONF; 201 } 202 203 204 /* ARGSUSED */ 205 static int 206 gt_cfsearch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 207 { 208 struct marvell_attach_args *mva = aux; 209 210 if (cf->cf_loc[GTCF_IRQ] != MVA_IRQ_DEFAULT) 211 mva->mva_irq = cf->cf_loc[GTCF_IRQ]; 212 213 return config_match(parent, cf, aux); 214 } 215 216 static void 217 gt_attach_peripherals(struct gt_softc *sc) 218 { 219 struct marvell_attach_args mva; 220 int i; 221 222 for (i = 0; i < __arraycount(gt_devs); i++) { 223 if (gt_devs[i].model != sc->sc_model) 224 continue; 225 226 mva.mva_name = gt_devs[i].name; 227 mva.mva_model = sc->sc_model; 228 mva.mva_revision = sc->sc_rev; 229 mva.mva_iot = sc->sc_iot; 230 mva.mva_ioh = sc->sc_ioh; 231 mva.mva_unit = gt_devs[i].unit; 232 mva.mva_addr = sc->sc_addr; 233 mva.mva_offset = gt_devs[i].offset; 234 mva.mva_size = 0; 235 mva.mva_dmat = sc->sc_dmat; 236 mva.mva_irq = gt_devs[i].irq; 237 238 config_found(sc->sc_dev, &mva, gt_cfprint, 239 CFARG_SUBMATCH, gt_cfsearch, 240 CFARG_IATTR, "gt", 241 CFARG_EOL); 242 } 243 } 244 245 void 246 gt_attach_common(struct gt_softc *gt) 247 { 248 uint32_t cpucfg, cpumode, cpumstr; 249 #ifdef GT_DEBUG 250 uint32_t loaddr, hiaddr; 251 #endif 252 253 gt_write(gt, GTPCI_CA(0), PCI_ID_REG); 254 gt->sc_model = PCI_PRODUCT(gt_read(gt, GTPCI_CD(0))); 255 gt_write(gt, GTPCI_CA(0), PCI_CLASS_REG); 256 gt->sc_rev = PCI_REVISION(gt_read(gt, GTPCI_CD(0))); 257 258 aprint_naive("\n"); 259 switch (gt->sc_model) { 260 case MARVELL_DISCOVERY: 261 aprint_normal(": GT-6426x%c Discovery\n", 262 (gt->sc_rev == MARVELL_DISCOVERY_REVA) ? 'A' : 'B'); 263 break; 264 case MARVELL_DISCOVERY_II: 265 aprint_normal(": MV6436x Discovery II\n"); 266 break; 267 268 case MARVELL_DISCOVERY_III: 269 aprint_normal(": MV6446x Discovery III\n"); 270 break; 271 #if 0 272 case MARVELL_DISCOVERY_LT: 273 case MARVELL_DISCOVERY_V: 274 case MARVELL_DISCOVERY_VI: 275 #endif 276 277 default: 278 aprint_normal(": type unknown\n"); break; 279 } 280 281 cpumode = gt_read(gt, GT_CPU_Mode); 282 aprint_normal_dev(gt->sc_dev, 283 "id %d", GT_CPUMode_MultiGTID_GET(cpumode)); 284 if (cpumode & GT_CPUMode_MultiGT) 285 aprint_normal (" (multi)"); 286 switch (GT_CPUMode_CPUType_GET(cpumode)) { 287 case 4: aprint_normal(", 60x bus"); break; 288 case 5: aprint_normal(", MPX bus"); break; 289 290 default: 291 aprint_normal(", %#x(?) bus", GT_CPUMode_CPUType_GET(cpumode)); 292 break; 293 } 294 295 cpumstr = gt_read(gt, GT_CPU_Master_Ctl); 296 switch (cpumstr & (GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock)) { 297 case 0: break; 298 case GT_CPUMstrCtl_CleanBlock: aprint_normal(", snoop=clean"); break; 299 case GT_CPUMstrCtl_FlushBlock: aprint_normal(", snoop=flush"); break; 300 case GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock: 301 aprint_normal(", snoop=clean&flush"); break; 302 } 303 aprint_normal(" wdog=%#x,%#x\n", 304 gt_read(gt, GT_WDOG_Config), gt_read(gt, GT_WDOG_Value)); 305 306 #ifdef GT_DEBUG 307 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS0_Low_Decode), gt->sc_model); 308 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS0_High_Decode), gt->sc_model); 309 aprint_normal_dev(gt->sc_dev, " scs[0]=%#10x-%#10x\n", 310 loaddr, hiaddr); 311 312 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS1_Low_Decode), gt->sc_model); 313 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS1_High_Decode), gt->sc_model); 314 aprint_normal_dev(gt->sc_dev, " scs[1]=%#10x-%#10x\n", 315 loaddr, hiaddr); 316 317 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS2_Low_Decode), gt->sc_model); 318 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS2_High_Decode), gt->sc_model); 319 aprint_normal_dev(gt->sc_dev, " scs[2]=%#10x-%#10x\n", 320 loaddr, hiaddr); 321 322 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS3_Low_Decode), gt->sc_model); 323 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS3_High_Decode), gt->sc_model); 324 aprint_normal_dev(gt->sc_dev, " scs[3]=%#10x-%#10x\n", 325 loaddr, hiaddr); 326 327 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS0_Low_Decode), gt->sc_model); 328 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS0_High_Decode), gt->sc_model); 329 aprint_normal_dev(gt->sc_dev, " cs[0]=%#10x-%#10x\n", 330 loaddr, hiaddr); 331 332 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS1_Low_Decode), gt->sc_model); 333 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS1_High_Decode), gt->sc_model); 334 aprint_normal_dev(gt->sc_dev, " cs[1]=%#10x-%#10x\n", 335 loaddr, hiaddr); 336 337 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS2_Low_Decode), gt->sc_model); 338 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS2_High_Decode), gt->sc_model); 339 aprint_normal_dev(gt->sc_dev, " cs[2]=%#10x-%#10x\n", 340 loaddr, hiaddr); 341 342 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS3_Low_Decode), gt->sc_model); 343 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS3_High_Decode), gt->sc_model); 344 aprint_normal_dev(gt->sc_dev, " cs[3]=%#10x-%#10x\n", 345 loaddr, hiaddr); 346 347 loaddr = GT_LADDR_GET(gt_read(gt, GT_BootCS_Low_Decode), gt->sc_model); 348 hiaddr = GT_HADDR_GET(gt_read(gt, GT_BootCS_High_Decode), gt->sc_model); 349 aprint_normal_dev(gt->sc_dev, " bootcs=%#10x-%#10x\n", 350 loaddr, hiaddr); 351 352 loaddr = GT_LADDR_GET(gt_read(gt, GT_PCI0_IO_Low_Decode), gt->sc_model); 353 hiaddr = 354 GT_HADDR_GET(gt_read(gt, GT_PCI0_IO_High_Decode), gt->sc_model); 355 aprint_normal_dev(gt->sc_dev, " pci0io=%#10x-%#10x ", 356 loaddr, hiaddr); 357 358 loaddr = gt_read(gt, GT_PCI0_IO_Remap); 359 aprint_normal("remap=%#010x\n", loaddr); 360 361 loaddr = 362 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode), gt->sc_model); 363 hiaddr = 364 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode), gt->sc_model); 365 aprint_normal_dev(gt->sc_dev, " pci0mem[0]=%#10x-%#10x ", 366 loaddr, hiaddr); 367 368 loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low); 369 hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High); 370 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 371 372 loaddr = 373 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode), gt->sc_model); 374 hiaddr = 375 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode), gt->sc_model); 376 aprint_normal_dev(gt->sc_dev, " pci0mem[1]=%#10x-%#10x ", 377 loaddr, hiaddr); 378 379 loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low); 380 hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High); 381 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 382 383 loaddr = 384 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode), gt->sc_model); 385 hiaddr = 386 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode), gt->sc_model); 387 aprint_normal_dev(gt->sc_dev, " pci0mem[2]=%#10x-%#10x ", 388 loaddr, hiaddr); 389 390 loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low); 391 hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High); 392 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 393 394 loaddr = 395 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode), gt->sc_model); 396 hiaddr = 397 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode), gt->sc_model); 398 aprint_normal_dev(gt->sc_dev, " pci0mem[3]=%#10x-%#10x ", 399 loaddr, hiaddr); 400 401 loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low); 402 hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High); 403 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 404 405 loaddr = GT_LADDR_GET(gt_read(gt, GT_PCI1_IO_Low_Decode), gt->sc_model); 406 hiaddr = 407 GT_HADDR_GET(gt_read(gt, GT_PCI1_IO_High_Decode), gt->sc_model); 408 aprint_normal_dev(gt->sc_dev, " pci1io=%#10x-%#10x ", 409 loaddr, hiaddr); 410 411 loaddr = gt_read(gt, GT_PCI1_IO_Remap); 412 aprint_normal("remap=%#010x\n", loaddr); 413 414 loaddr = 415 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode), gt->sc_model); 416 hiaddr = 417 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode), gt->sc_model); 418 aprint_normal_dev(gt->sc_dev, " pci1mem[0]=%#10x-%#10x ", 419 loaddr, hiaddr); 420 421 loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low); 422 hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High); 423 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 424 425 loaddr = 426 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode), gt->sc_model); 427 hiaddr = 428 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode), gt->sc_model); 429 aprint_normal_dev(gt->sc_dev, " pci1mem[1]=%#10x-%#10x ", 430 loaddr, hiaddr); 431 432 loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low); 433 hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High); 434 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 435 436 loaddr = 437 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode), gt->sc_model); 438 hiaddr = 439 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode), gt->sc_model); 440 aprint_normal_dev(gt->sc_dev, " pci1mem[2]=%#10x-%#10x ", 441 loaddr, hiaddr); 442 443 loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low); 444 hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High); 445 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 446 447 loaddr = 448 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode), gt->sc_model); 449 hiaddr = 450 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode), gt->sc_model); 451 aprint_normal_dev(gt->sc_dev, " pci1mem[3]=%#10x-%#10x ", 452 loaddr, hiaddr); 453 454 loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low); 455 hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High); 456 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 457 458 loaddr = GT_LADDR_GET(gt_read(gt, GT_Internal_Decode), gt->sc_model); 459 aprint_normal_dev(gt->sc_dev, " internal=%#10x-%#10x\n", 460 loaddr, loaddr + 256 * 1024); 461 462 loaddr = GT_LADDR_GET(gt_read(gt, GT_CPU0_Low_Decode), gt->sc_model); 463 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CPU0_High_Decode), gt->sc_model); 464 aprint_normal_dev(gt->sc_dev, " cpu0=%#10x-%#10x\n", 465 loaddr, hiaddr); 466 467 #ifdef MULTIPROCESSOR 468 loaddr = GT_LADDR_GET(gt_read(gt, GT_CPU1_Low_Decode), gt->sc_model); 469 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CPU1_High_Decode), gt->sc_model); 470 aprint_normal_dev(gt->sc_dev, " cpu1=%#10x-%#10x", 471 loaddr, hiaddr); 472 #endif 473 #endif 474 475 aprint_normal("%s:", device_xname(gt->sc_dev)); 476 477 cpucfg = gt_read(gt, GT_CPU_Cfg); 478 cpucfg |= GT_CPUCfg_ConfSBDis; /* per errata #46 */ 479 cpucfg |= GT_CPUCfg_AACKDelay; /* per restriction #18 */ 480 gt_write(gt, GT_CPU_Cfg, cpucfg); 481 if (cpucfg & GT_CPUCfg_Pipeline) 482 aprint_normal(" pipeline"); 483 if (cpucfg & GT_CPUCfg_AACKDelay) 484 aprint_normal(" aack-delay"); 485 if (cpucfg & GT_CPUCfg_RdOOO) 486 aprint_normal(" read-ooo"); 487 if (cpucfg & GT_CPUCfg_IOSBDis) 488 aprint_normal(" io-sb-dis"); 489 if (cpucfg & GT_CPUCfg_ConfSBDis) 490 aprint_normal(" conf-sb-dis"); 491 if (cpucfg & GT_CPUCfg_ClkSync) 492 aprint_normal(" clk-sync"); 493 aprint_normal("\n"); 494 495 #ifdef GT_WATCHDOG 496 gt_watchdog_init(gt); 497 #endif 498 499 #ifdef GT_DEVBUS 500 gt_devbus_intr_enb(gt); 501 #endif 502 #ifdef GT_ECC 503 gt_ecc_intr_enb(gt); 504 #endif 505 #if NGTMPSC > 0 506 gt_sdma_intr_enb(gt); 507 #endif 508 #ifdef GT_COMM 509 gt_comm_intr_enb(gt); 510 #endif 511 512 gt_attach_peripherals(gt); 513 514 #ifdef GT_WATCHDOG 515 gt_watchdog_service(); 516 gt_watchdog_enable(gt); 517 #endif 518 } 519 520 521 #ifdef GT_DEVBUS 522 static int 523 gt_devbus_intr(void *arg) 524 { 525 struct gt_softc *gt = (struct gt_softc *)arg; 526 u_int32_t cause; 527 u_int32_t addr; 528 529 cause = gt_read(gt, GT_DEVBUS_ICAUSE); 530 addr = gt_read(gt, GT_DEVBUS_ERR_ADDR); 531 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear intr */ 532 533 if (cause & GT_DEVBUS_DBurstErr) { 534 aprint_error_dev(gt->sc_dev, 535 "Device Bus error: burst violation"); 536 if ((cause & GT_DEVBUS_Sel) == 0) 537 aprint_error(", addr %#x", addr); 538 aprint_error("\n"); 539 } 540 if (cause & GT_DEVBUS_DRdyErr) { 541 aprint_error_dev(gt->sc_dev, 542 "Device Bus error: ready timer expired"); 543 if ((cause & GT_DEVBUS_Sel) != 0) 544 aprint_error(", addr %#x\n", addr); 545 aprint_error("\n"); 546 } 547 548 return cause != 0; 549 } 550 551 /* 552 * gt_devbus_intr_enb - enable GT-64260 Device Bus interrupts 553 */ 554 static void 555 gt_devbus_intr_enb(struct gt_softc *gt) 556 { 557 gt_write(gt, GT_DEVBUS_IMASK, 558 GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr); 559 (void)gt_read(gt, GT_DEVBUS_ERR_ADDR); /* clear addr */ 560 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear intr */ 561 562 (void)marvell_intr_establish(IRQ_DEV, IPL_VM, gt_devbus_intr, gt); 563 } 564 #endif /* GT_DEVBUS */ 565 566 #ifdef GT_ECC 567 const static char *gt_ecc_intr_str[4] = { 568 "(none)", 569 "single bit", 570 "double bit", 571 "(reserved)" 572 }; 573 574 static int 575 gt_ecc_intr(void *arg) 576 { 577 struct gt_softc *gt = (struct gt_softc *)arg; 578 uint32_t addr, dlo, dhi, rec, calc, count; 579 int err; 580 581 count = gt_read(gt, GT_ECC_Count); 582 dlo = gt_read(gt, GT_ECC_Data_Lo); 583 dhi = gt_read(gt, GT_ECC_Data_Hi); 584 rec = gt_read(gt, GT_ECC_Rec); 585 calc = gt_read(gt, GT_ECC_Calc); 586 addr = gt_read(gt, GT_ECC_Addr); /* read last! */ 587 gt_write(gt, GT_ECC_Addr, 0); /* clear intr */ 588 589 err = addr & 0x3; 590 591 aprint_error_dev(gt->sc_dev, 592 "ECC error: %s: addr %#x data %#x.%#x rec %#x calc %#x cnt %#x\n", 593 gt_ecc_intr_str[err], addr, dhi, dlo, rec, calc, count); 594 595 if (err == 2) 596 panic("ecc"); 597 598 return err == 1; 599 } 600 601 /* 602 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 603 */ 604 static void 605 gt_ecc_intr_enb(struct gt_softc *gt) 606 { 607 uint32_t ctl; 608 609 ctl = gt_read(gt, GT_ECC_Ctl); 610 ctl |= 1 << 16; /* XXX 1-bit threshold == 1 */ 611 gt_write(gt, GT_ECC_Ctl, ctl); 612 (void)gt_read(gt, GT_ECC_Data_Lo); 613 (void)gt_read(gt, GT_ECC_Data_Hi); 614 (void)gt_read(gt, GT_ECC_Rec); 615 (void)gt_read(gt, GT_ECC_Calc); 616 (void)gt_read(gt, GT_ECC_Addr); /* read last! */ 617 gt_write(gt, GT_ECC_Addr, 0); /* clear intr */ 618 619 (void)marvell_intr_establish(IRQ_ECC, IPL_VM, gt_ecc_intr, gt); 620 } 621 #endif /* GT_ECC */ 622 623 #if NGTMPSC > 0 624 /* 625 * gt_sdma_intr_enb - enable GT-64260 SDMA interrupts 626 */ 627 static void 628 gt_sdma_intr_enb(struct gt_softc *gt) 629 { 630 631 (void)marvell_intr_establish(IRQ_SDMA, IPL_SERIAL, gtmpsc_intr, gt); 632 } 633 #endif 634 635 #ifdef GT_COMM 636 /* 637 * unknown board, enable everything 638 */ 639 # define GT_CommUnitIntr_DFLT \ 640 GT_CommUnitIntr_S0 |\ 641 GT_CommUnitIntr_S1 |\ 642 GT_CommUnitIntr_E0 |\ 643 GT_CommUnitIntr_E1 |\ 644 GT_CommUnitIntr_E2 645 646 static const char * const gt_comm_subunit_name[8] = { 647 "ethernet 0", 648 "ethernet 1", 649 "ethernet 2", 650 "(reserved)", 651 "MPSC 0", 652 "MPSC 1", 653 "(reserved)", 654 "(sel)", 655 }; 656 657 static int 658 gt_comm_intr(void *arg) 659 { 660 struct gt_softc *gt = (struct gt_softc *)arg; 661 uint32_t cause, addr; 662 unsigned int mask; 663 int i; 664 665 cause = gt_read(gt, GT_CommUnitIntr_Cause); 666 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 667 addr = gt_read(gt, GT_CommUnitIntr_ErrAddr); 668 669 aprint_error_dev(gt->sc_dev, 670 "Communications Unit Controller interrupt, cause %#x addr %#x\n", 671 cause, addr); 672 673 cause &= GT_CommUnitIntr_DFLT; 674 if (cause == 0) 675 return 0; 676 677 mask = 0x7; 678 for (i=0; i<7; i++) { 679 if (cause & mask) { 680 printf("%s: Comm Unit %s:", device_xname(gt->sc_dev), 681 gt_comm_subunit_name[i]); 682 if (cause & 1) 683 printf(" AddrMiss"); 684 if (cause & 2) 685 printf(" AccProt"); 686 if (cause & 4) 687 printf(" WrProt"); 688 printf("\n"); 689 } 690 cause >>= 4; 691 } 692 return 1; 693 } 694 695 /* 696 * gt_comm_intr_init - enable GT-64260 Comm Unit interrupts 697 */ 698 static void 699 gt_comm_intr_enb(struct gt_softc *gt) 700 { 701 uint32_t cause; 702 703 cause = gt_read(gt, GT_CommUnitIntr_Cause); 704 if (cause) 705 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 706 gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT); 707 (void)gt_read(gt, GT_CommUnitIntr_ErrAddr); 708 709 (void)marvell_intr_establish(IRQ_COMM, IPL_VM, gt_comm_intr, gt); 710 } 711 #endif /* GT_COMM */ 712 713 714 #ifdef GT_WATCHDOG 715 #ifndef GT_MPP_WATCHDOG 716 static void 717 gt_watchdog_init(struct gt_softc *gt) 718 { 719 u_int32_t r; 720 721 aprint_normal_dev(gt->sc_dev, "watchdog"); 722 723 /* 724 * handle case where firmware started watchdog 725 */ 726 r = gt_read(gt, GT_WDOG_Config); 727 aprint_normal(" status %#x,%#x:", r, gt_read(gt, GT_WDOG_Value)); 728 if ((r & 0x80000000) != 0) { 729 gt_watchdog_sc = gt; /* enabled */ 730 gt_watchdog_state = 1; 731 aprint_normal(" firmware-enabled\n"); 732 gt_watchdog_disable(gt); 733 } else 734 aprint_normal(" firmware-disabled\n"); 735 } 736 737 #elif GT_MPP_WATCHDOG == 0 738 739 static void 740 gt_watchdog_init(struct gt_softc *gt) 741 { 742 743 aprint_normal_dev(gt->sc_dev, "watchdog not configured\n"); 744 return; 745 } 746 747 #else /* GT_MPP_WATCHDOG > 0 */ 748 749 static void 750 gt_watchdog_init(struct gt_softc *gt) 751 { 752 u_int32_t mpp_watchdog = GT_MPP_WATCHDOG; /* from config */ 753 u_int32_t cfgbits, mppbits, mppmask, regoff, r; 754 755 mppmask = 0; 756 757 aprint_normal_dev(gt->sc_dev, "watchdog"); 758 759 /* 760 * if firmware started watchdog, we disable and start 761 * from scratch to get it in a known state. 762 * 763 * on GT-64260A we always see 0xffffffff 764 * in both the GT_WDOG_Config_Enb and GT_WDOG_Value registers. 765 */ 766 r = gt_read(gt, GT_WDOG_Config); 767 if (r != ~0) { 768 if ((r & GT_WDOG_Config_Enb) != 0) { 769 gt_write(gt, GT_WDOG_Config, 770 GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT); 771 gt_write(gt, GT_WDOG_Config, 772 GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT); 773 } 774 } 775 776 /* 777 * "the watchdog timer can be activated only after 778 * configuring two MPP pins to act as WDE and WDNMI" 779 */ 780 mppbits = 0; 781 cfgbits = 0x3; 782 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 783 if ((mpp_watchdog & cfgbits) == cfgbits) { 784 mppbits = 0x99; 785 mppmask = 0xff; 786 break; 787 } 788 cfgbits <<= 2; 789 if ((mpp_watchdog & cfgbits) == cfgbits) { 790 mppbits = 0x9900; 791 mppmask = 0xff00; 792 break; 793 } 794 cfgbits <<= 6; /* skip unqualified bits */ 795 } 796 if (mppbits == 0) { 797 aprint_error(" config error\n"); 798 return; 799 } 800 801 r = gt_read(gt, regoff); 802 r &= ~mppmask; 803 r |= mppbits; 804 gt_write(gt, regoff, r); 805 aprint_normal(" mpp %#x %#x", regoff, mppbits); 806 807 gt_write(gt, GT_WDOG_Value, GT_WDOG_NMI_DFLT); 808 809 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a|GT_WDOG_Preset_DFLT); 810 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b|GT_WDOG_Preset_DFLT); 811 812 r = gt_read(gt, GT_WDOG_Config); 813 aprint_normal(" status %#x,%#x: %s\n", 814 r, gt_read(gt, GT_WDOG_Value), 815 ((r & GT_WDOG_Config_Enb) != 0) ? "enabled" : "botch"); 816 } 817 #endif /* GT_MPP_WATCHDOG */ 818 819 static void 820 gt_watchdog_enable(struct gt_softc *gt) 821 { 822 823 if (gt_watchdog_state == 0) { 824 gt_watchdog_state = 1; 825 826 gt_write(gt, GT_WDOG_Config, 827 GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT); 828 gt_write(gt, GT_WDOG_Config, 829 GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT); 830 } 831 } 832 833 #ifndef GT_MPP_WATCHDOG 834 static void 835 gt_watchdog_disable(struct gt_softc *gt) 836 { 837 838 if (gt_watchdog_state != 0) { 839 gt_watchdog_state = 0; 840 841 gt_write(gt, GT_WDOG_Config, 842 GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT); 843 gt_write(gt, GT_WDOG_Config, 844 GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT); 845 } 846 } 847 #endif 848 849 /* 850 * XXXX: gt_watchdog_service/reset functions need mutex lock... 851 */ 852 853 #ifdef GT_DEBUG 854 int inhibit_watchdog_service = 0; 855 #endif 856 void 857 gt_watchdog_service(void) 858 { 859 struct gt_softc *gt = gt_watchdog_sc; 860 861 if ((gt == NULL) || (gt_watchdog_state == 0)) 862 return; /* not enabled */ 863 #ifdef GT_DEBUG 864 if (inhibit_watchdog_service) 865 return; 866 #endif 867 868 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl2a|GT_WDOG_Preset_DFLT); 869 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl2b|GT_WDOG_Preset_DFLT); 870 } 871 872 /* 873 * gt_watchdog_reset - force a watchdog reset using Preset_VAL=0 874 */ 875 void 876 gt_watchdog_reset(void) 877 { 878 struct gt_softc *gt = gt_watchdog_sc; 879 u_int32_t r; 880 881 r = gt_read(gt, GT_WDOG_Config); 882 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a); 883 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b); 884 if ((r & GT_WDOG_Config_Enb) != 0) { 885 /* 886 * was enabled, we just toggled it off, toggle on again 887 */ 888 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a); 889 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b); 890 } 891 for(;;); 892 } 893 #endif 894 895 896 int 897 marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attr, 898 uint64_t *base, uint32_t *size) 899 { 900 static const struct { 901 int tag; 902 uint32_t attribute; 903 uint32_t basereg; 904 uint32_t sizereg; 905 } tagtbl[] = { 906 { MARVELL_TAG_SDRAM_CS0, MARVELL_ATTR_SDRAM_CS0, 907 GT_SCS0_Low_Decode, GT_SCS0_High_Decode }, 908 { MARVELL_TAG_SDRAM_CS1, MARVELL_ATTR_SDRAM_CS1, 909 GT_SCS1_Low_Decode, GT_SCS1_High_Decode }, 910 { MARVELL_TAG_SDRAM_CS2, MARVELL_ATTR_SDRAM_CS2, 911 GT_SCS2_Low_Decode, GT_SCS2_High_Decode }, 912 { MARVELL_TAG_SDRAM_CS3, MARVELL_ATTR_SDRAM_CS3, 913 GT_SCS3_Low_Decode, GT_SCS3_High_Decode }, 914 915 { MARVELL_TAG_UNDEFINED, 0, 0 } 916 }; 917 struct gt_softc *sc = device_private(dev); 918 int i; 919 920 for (i = 0; tagtbl[i].tag != MARVELL_TAG_UNDEFINED; i++) 921 if (tag == tagtbl[i].tag) 922 break; 923 if (tagtbl[i].tag == MARVELL_TAG_UNDEFINED) 924 return -1; 925 926 if (target != NULL) 927 *target = 0; 928 if (attr != NULL) 929 *attr = tagtbl[i].attribute; 930 if (base != NULL) 931 *base = gt_read(sc, tagtbl[i].basereg) << 932 (sc->sc_model == MARVELL_DISCOVERY ? 20 : 16); 933 if (size != NULL) { 934 const uint32_t s = gt_read(sc, tagtbl[i].sizereg); 935 936 if (s != 0) 937 *size = (s + 1) << 938 (sc->sc_model == MARVELL_DISCOVERY ? 20 : 16); 939 else 940 *size = 0; 941 } 942 943 return 0; 944 } 945
Indexes created Sun Oct 19 21:10:07 GMT 2025