gt.c revision 1.4
1 /* $NetBSD: gt.c,v 1.4 2003/06/12 19:14:37 scw Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gt.c -- GT system controller driver 42 */ 43 44 #include "opt_marvell.h" 45 46 #include <sys/param.h> 47 #include <sys/types.h> 48 #include <sys/cdefs.h> 49 #include <sys/extent.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 54 #define _BUS_SPACE_PRIVATE 55 #define _BUS_DMA_PRIVATE 56 #include <machine/bus.h> 57 58 #include <powerpc/spr.h> 59 #include <powerpc/oea/hid.h> 60 61 #include <dev/marvell/gtreg.h> 62 #include <dev/marvell/gtintrreg.h> 63 #include <dev/marvell/gtvar.h> 64 #include <dev/marvell/gtethreg.h> 65 66 #ifdef DEBUG 67 #include <sys/systm.h> /* for Debugger() */ 68 #endif 69 70 #if ((GT_MPP_WATCHDOG & 0xf0f0f0f0) != 0) 71 # error /* unqualified: configuration botch! */ 72 #endif 73 #if ((GT_MPP_WATCHDOG & GT_MPP_INTERRUPTS) != 0) 74 # error /* conflict: configuration botch! */ 75 #endif 76 77 static void gt_comm_intr_enb(struct gt_softc *); 78 static void gt_devbus_intr_enb(struct gt_softc *); 79 #ifdef GT_ECC 80 static void gt_ecc_intr_enb(struct gt_softc *); 81 #endif 82 83 void gt_init_hostid (struct gt_softc *); 84 void gt_init_interrupt (struct gt_softc *); 85 static int gt_comm_intr (void *); 86 87 void gt_watchdog_init(struct gt_softc *); 88 void gt_watchdog_enable(void); 89 void gt_watchdog_disable(void); 90 void gt_watchdog_reset(void); 91 92 extern struct cfdriver gt_cd; 93 94 static int gtfound = 0; 95 96 static struct gt_softc *gt_watchdog_sc = 0; 97 static int gt_watchdog_state = 0; 98 99 int 100 gt_cfprint (void *aux, const char *pnp) 101 { 102 struct gt_attach_args *ga = aux; 103 104 if (pnp) { 105 aprint_normal("%s at %s", ga->ga_name, pnp); 106 } 107 108 aprint_normal(" unit %d", ga->ga_unit); 109 return (UNCONF); 110 } 111 112 113 static int 114 gt_cfsearch(struct device *parent, struct cfdata *cf, void *aux) 115 { 116 struct gt_softc *gt = (struct gt_softc *) parent; 117 struct gt_attach_args ga; 118 119 ga.ga_name = cf->cf_name; 120 ga.ga_dmat = gt->gt_dmat; 121 ga.ga_memt = gt->gt_memt; 122 ga.ga_memh = gt->gt_memh; 123 ga.ga_unit = cf->cf_loc[GTCF_UNIT]; 124 125 if (config_match(parent, cf, &ga) > 0) 126 config_attach(parent, cf, &ga, gt_cfprint); 127 128 return (0); 129 } 130 131 void 132 gt_attach_common(struct gt_softc *gt) 133 { 134 uint32_t cpucfg, cpumode, cpumstr; 135 #ifdef DEBUG 136 uint32_t loaddr, hiaddr; 137 #endif 138 139 gtfound = 1; 140 141 cpumode = gt_read(gt, GT_CPU_Mode); 142 aprint_normal(": id %d", GT_CPUMode_MultiGTID_GET(cpumode)); 143 if (cpumode & GT_CPUMode_MultiGT) 144 aprint_normal (" (multi)"); 145 switch (GT_CPUMode_CPUType_GET(cpumode)) { 146 case 4: aprint_normal(", 60x bus"); break; 147 case 5: aprint_normal(", MPX bus"); break; 148 default: aprint_normal(", %#x(?) bus", GT_CPUMode_CPUType_GET(cpumode)); break; 149 } 150 151 cpumstr = gt_read(gt, GT_CPU_Master_Ctl); 152 cpumstr &= ~(GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock); 153 #if 0 154 cpumstr |= GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock; 155 #endif 156 gt_write(gt, GT_CPU_Master_Ctl, cpumstr); 157 158 switch (cpumstr & (GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock)) { 159 case 0: break; 160 case GT_CPUMstrCtl_CleanBlock: aprint_normal(", snoop=clean"); break; 161 case GT_CPUMstrCtl_FlushBlock: aprint_normal(", snoop=flush"); break; 162 case GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock: 163 aprint_normal(", snoop=clean&flush"); break; 164 } 165 aprint_normal(" wdog=%#x,%#x\n", 166 gt_read(gt, GT_WDOG_Config), 167 gt_read(gt, GT_WDOG_Value)); 168 169 #if DEBUG 170 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS0_Low_Decode)); 171 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS0_High_Decode)); 172 aprint_normal("%s: scs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 173 174 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS1_Low_Decode)); 175 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS1_High_Decode)); 176 aprint_normal("%s: scs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 177 178 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS2_Low_Decode)); 179 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS2_High_Decode)); 180 aprint_normal("%s: scs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 181 182 loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS3_Low_Decode)); 183 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS3_High_Decode)); 184 aprint_normal("%s: scs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 185 186 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS0_Low_Decode)); 187 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS0_High_Decode)); 188 aprint_normal("%s: cs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 189 190 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS1_Low_Decode)); 191 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS1_High_Decode)); 192 aprint_normal("%s: cs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 193 194 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS2_Low_Decode)); 195 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS2_High_Decode)); 196 aprint_normal("%s: cs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 197 198 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS3_Low_Decode)); 199 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS3_High_Decode)); 200 aprint_normal("%s: cs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 201 202 loaddr = GT_LowAddr_GET(gt_read(gt, GT_BootCS_Low_Decode)); 203 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_BootCS_High_Decode)); 204 aprint_normal("%s: bootcs=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 205 206 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_IO_Low_Decode)); 207 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_IO_High_Decode)); 208 aprint_normal("%s: pci0io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 209 210 loaddr = gt_read(gt, GT_PCI0_IO_Remap); 211 aprint_normal("remap=%#010x\n", loaddr); 212 213 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode)); 214 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode)); 215 aprint_normal("%s: pci0mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 216 217 loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low); 218 hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High); 219 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 220 221 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode)); 222 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode)); 223 aprint_normal("%s: pci0mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 224 225 loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low); 226 hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High); 227 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 228 229 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode)); 230 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode)); 231 aprint_normal("%s: pci0mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 232 233 loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low); 234 hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High); 235 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 236 237 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode)); 238 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode)); 239 aprint_normal("%s: pci0mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 240 241 loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low); 242 hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High); 243 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 244 245 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_IO_Low_Decode)); 246 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_IO_High_Decode)); 247 aprint_normal("%s: pci1io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 248 249 loaddr = gt_read(gt, GT_PCI1_IO_Remap); 250 aprint_normal("remap=%#010x\n", loaddr); 251 252 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode)); 253 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode)); 254 aprint_normal("%s: pci1mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 255 256 loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low); 257 hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High); 258 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 259 260 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode)); 261 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode)); 262 aprint_normal("%s: pci1mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 263 264 loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low); 265 hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High); 266 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 267 268 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode)); 269 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode)); 270 aprint_normal("%s: pci1mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 271 272 loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low); 273 hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High); 274 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 275 276 loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode)); 277 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode)); 278 aprint_normal("%s: pci1mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr); 279 280 loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low); 281 hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High); 282 aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr); 283 284 loaddr = GT_LowAddr_GET(gt_read(gt, GT_Internal_Decode)); 285 aprint_normal("%s: internal=%#10x-%#10x\n", gt->gt_dev.dv_xname, 286 loaddr, loaddr+256*1024); 287 288 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU0_Low_Decode)); 289 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU0_High_Decode)); 290 aprint_normal("%s: cpu0=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr); 291 292 loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU1_Low_Decode)); 293 hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU1_High_Decode)); 294 aprint_normal("%s: cpu1=%#10x-%#10x", gt->gt_dev.dv_xname, loaddr, hiaddr); 295 #endif 296 297 aprint_normal("%s:", gt->gt_dev.dv_xname); 298 299 cpucfg = gt_read(gt, GT_CPU_Cfg); 300 cpucfg |= GT_CPUCfg_ConfSBDis; /* per errata #46 */ 301 cpucfg |= GT_CPUCfg_AACKDelay; /* per restriction #18 */ 302 gt_write(gt, GT_CPU_Cfg, cpucfg); 303 if (cpucfg & GT_CPUCfg_Pipeline) 304 aprint_normal(" pipeline"); 305 if (cpucfg & GT_CPUCfg_AACKDelay) 306 aprint_normal(" aack-delay"); 307 if (cpucfg & GT_CPUCfg_RdOOO) 308 aprint_normal(" read-ooo"); 309 if (cpucfg & GT_CPUCfg_IOSBDis) 310 aprint_normal(" io-sb-dis"); 311 if (cpucfg & GT_CPUCfg_ConfSBDis) 312 aprint_normal(" conf-sb-dis"); 313 if (cpucfg & GT_CPUCfg_ClkSync) 314 aprint_normal(" clk-sync"); 315 aprint_normal("\n"); 316 317 gt_init_hostid(gt); 318 319 gt_watchdog_init(gt); 320 321 gt_init_interrupt(gt); 322 323 #ifdef GT_ECC 324 gt_ecc_intr_enb(gt); 325 #endif 326 327 gt_comm_intr_enb(gt); 328 gt_devbus_intr_enb(gt); 329 330 gt_watchdog_disable(); 331 config_search(gt_cfsearch, >->gt_dev, NULL); 332 gt_watchdog_service(); 333 gt_watchdog_enable(); 334 } 335 336 void 337 gt_init_hostid(struct gt_softc *gt) 338 { 339 340 hostid = 1; /* XXX: Used by i2c; needs work -- AKB */ 341 } 342 343 void 344 gt_init_interrupt(struct gt_softc *gt) 345 { 346 u_int32_t mppirpts = GT_MPP_INTERRUPTS; /* from config */ 347 u_int32_t r; 348 u_int32_t mppbit; 349 u_int32_t mask; 350 u_int32_t mppsel; 351 u_int32_t regoff; 352 353 gt_write(gt, ICR_CIM_LO, 0); 354 gt_write(gt, ICR_CIM_HI, 0); 355 356 /* 357 * configure the GPP interrupts: 358 * - set the configured MPP pins in GPP mode 359 * - set the configured GPP pins to input, active low, interrupt enbl 360 */ 361 #ifdef DEBUG 362 printf("%s: mpp cfg ", gt->gt_dev.dv_xname); 363 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) 364 printf("%#x ", gt_read(gt, regoff)); 365 printf(", mppirpts 0x%x\n", mppirpts); 366 #endif 367 mppbit = 0x1; 368 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 369 mask = 0; 370 for (mppsel = 0xf; mppsel; mppsel <<= 4) { 371 if (mppirpts & mppbit) 372 mask |= mppsel; 373 mppbit <<= 1; 374 } 375 if (mask) { 376 r = gt_read(gt, regoff); 377 r &= ~mask; 378 gt_write(gt, regoff, r); 379 } 380 } 381 382 r = gt_read(gt, GT_GPP_IO_Control); 383 r &= ~mppirpts; 384 gt_write(gt, GT_GPP_IO_Control, r); 385 386 r = gt_read(gt, GT_GPP_Level_Control); 387 r |= mppirpts; 388 gt_write(gt, GT_GPP_Level_Control, r); 389 390 r = gt_read(gt, GT_GPP_Interrupt_Mask); 391 r |= mppirpts; 392 gt_write(gt, GT_GPP_Interrupt_Mask, r); 393 } 394 395 uint32_t 396 gt_read_mpp (void) 397 { 398 return gt_read((struct gt_softc *)gt_cd.cd_devs[0], GT_GPP_Value); 399 } 400 401 #if 0 402 int 403 gt_bs_extent_init(struct discovery_bus_space *bs, char *name) 404 { 405 u_long start, end; 406 int i, j, error; 407 408 if (bs->bs_nregion == 0) { 409 bs->bs_extent = extent_create(name, 0xffffffffUL, 0xffffffffUL, 410 M_DEVBUF, NULL, 0, EX_NOCOALESCE|EX_WAITOK); 411 KASSERT(bs->bs_extent != NULL); 412 return 0; 413 } 414 /* 415 * Find the top and bottoms of this bus space. 416 */ 417 start = bs->bs_regions[0].br_start; 418 end = bs->bs_regions[0].br_end; 419 #ifdef DEBUG 420 if (gtpci_debug > 1) 421 printf("gtpci_bs_extent_init: %s: region %d: %#lx-%#lx\n", 422 name, 0, bs->bs_regions[0].br_start, 423 bs->bs_regions[0].br_end); 424 #endif 425 for (i = 1; i < bs->bs_nregion; i++) { 426 if (bs->bs_regions[i].br_start < start) 427 start = bs->bs_regions[i].br_start; 428 if (bs->bs_regions[i].br_end > end) 429 end = bs->bs_regions[i].br_end; 430 #ifdef DEBUG 431 if (gtpci_debug > 1) 432 printf("gtpci_bs_extent_init: %s: region %d:" 433 " %#lx-%#lx\n", 434 name, i, bs->bs_regions[i].br_start, 435 bs->bs_regions[i].br_end); 436 #endif 437 } 438 /* 439 * Now that we have the top and bottom limits of this 440 * bus space, create the extent map that will manage this 441 * space for us. 442 */ 443 #ifdef DEBUG 444 if (gtpci_debug > 1) 445 printf("gtpci_bs_extent_init: %s: create: %#lx-%#lx\n", 446 name, start, end); 447 #endif 448 bs->bs_extent = extent_create(name, start, end, M_DEVBUF, 449 NULL, 0, EX_NOCOALESCE|EX_WAITOK); 450 KASSERT(bs->bs_extent != NULL); 451 452 /* If there was more than one bus space region, then there 453 * might gaps in between them. Allocate the gap so that 454 * they will not be legal addresses in the extent. 455 */ 456 for (i = 0; i < bs->bs_nregion && bs->bs_nregion > 1; i++) { 457 /* Initial start is "infinity" and the inital end is 458 * is the end of this bus region. 459 */ 460 start = ~0UL; 461 end = bs->bs_regions[i].br_end; 462 /* For each region, if it starts after this region but less 463 * than the saved start, use its start address. If the start 464 * address is one past the end address, then we're done 465 */ 466 for (j = 0; j < bs->bs_nregion && start > end + 1; j++) { 467 if (i == j) 468 continue; 469 if (bs->bs_regions[j].br_start > end && 470 bs->bs_regions[j].br_start < start) 471 start = bs->bs_regions[j].br_start; 472 } 473 /* 474 * If we found a gap, allocate it away. 475 */ 476 if (start != ~0UL && start != end + 1) { 477 #ifdef DEBUG 478 if (gtpci_debug > 1) 479 printf("gtpci_bs_extent_init: %s: alloc(hole): %#lx-%#lx\n", 480 name, end + 1, start - 1); 481 #endif 482 error = extent_alloc_region(bs->bs_extent, end + 1, 483 start - (end + 1), EX_NOWAIT); 484 KASSERT(error == 0); 485 } 486 } 487 return 1; 488 } 489 #endif 490 491 /* 492 * unknown board, enable everything 493 */ 494 # define GT_CommUnitIntr_DFLT GT_CommUnitIntr_S0|GT_CommUnitIntr_S1 \ 495 |GT_CommUnitIntr_E0|GT_CommUnitIntr_E1 \ 496 |GT_CommUnitIntr_E2 497 498 static const char * const gt_comm_subunit_name[8] = { 499 "ethernet 0", 500 "ethernet 1", 501 "ethernet 2", 502 "(reserved)", 503 "MPSC 0", 504 "MPSC 1", 505 "(reserved)", 506 "(sel)", 507 }; 508 509 static int 510 gt_comm_intr(void *arg) 511 { 512 struct gt_softc *gt = (struct gt_softc *)arg; 513 u_int32_t cause; 514 u_int32_t addr; 515 unsigned int mask; 516 int i; 517 518 cause = gt_read(gt, GT_CommUnitIntr_Cause); 519 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 520 addr = gt_read(gt, GT_CommUnitIntr_ErrAddr); 521 522 printf("%s: Comm Unit irpt, cause %#x addr %#x\n", 523 gt->gt_dev.dv_xname, cause, addr); 524 525 cause &= GT_CommUnitIntr_DFLT; 526 if (cause == 0) 527 return 0; 528 529 mask = 0x7; 530 for (i=0; i<7; i++) { 531 if (cause & mask) { 532 printf("%s: Comm Unit %s:", gt->gt_dev.dv_xname, 533 gt_comm_subunit_name[i]); 534 if (cause & 1) 535 printf(" AddrMiss"); 536 if (cause & 2) 537 printf(" AccProt"); 538 if (cause & 4) 539 printf(" WrProt"); 540 printf("\n"); 541 } 542 cause >>= 4; 543 } 544 return 1; 545 } 546 547 /* 548 * gt_comm_intr_init - enable GT-64260 Comm Unit interrupts 549 */ 550 static void 551 gt_comm_intr_enb(struct gt_softc *gt) 552 { 553 u_int32_t cause; 554 555 cause = gt_read(gt, GT_CommUnitIntr_Cause); 556 if (cause) 557 gt_write(gt, GT_CommUnitIntr_Cause, ~cause); 558 gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT); 559 (void)gt_read(gt, GT_CommUnitIntr_ErrAddr); 560 561 intr_establish(IRQ_COMM, IST_LEVEL, IPL_GTERR, gt_comm_intr, gt); 562 printf("%s: Comm Unit irpt at %d\n", gt->gt_dev.dv_xname, IRQ_COMM); 563 } 564 565 #ifdef GT_ECC 566 static char *gt_ecc_intr_str[4] = { 567 "(none)", 568 "single bit", 569 "double bit", 570 "(reserved)" 571 }; 572 573 static int 574 gt_ecc_intr(void *arg) 575 { 576 struct gt_softc *gt = (struct gt_softc *)arg; 577 u_int32_t addr; 578 u_int32_t dlo; 579 u_int32_t dhi; 580 u_int32_t rec; 581 u_int32_t calc; 582 u_int32_t count; 583 int err; 584 585 count = gt_read(gt, GT_ECC_Count); 586 dlo = gt_read(gt, GT_ECC_Data_Lo); 587 dhi = gt_read(gt, GT_ECC_Data_Hi); 588 rec = gt_read(gt, GT_ECC_Rec); 589 calc = gt_read(gt, GT_ECC_Calc); 590 addr = gt_read(gt, GT_ECC_Addr); /* read last! */ 591 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 592 593 err = addr & 0x3; 594 595 printf("%s: ECC error: %s: " 596 "addr %#x data %#x.%#x rec %#x calc %#x cnt %#x\n", 597 gt->gt_dev.dv_xname, gt_ecc_intr_str[err], 598 addr, dhi, dlo, rec, calc, count); 599 600 if (err == 2) 601 panic("ecc"); 602 603 return (err == 1); 604 } 605 606 /* 607 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 608 */ 609 static void 610 gt_ecc_intr_enb(struct gt_softc *gt) 611 { 612 u_int32_t ctl; 613 614 ctl = gt_read(gt, GT_ECC_Ctl); 615 ctl |= 1 << 16; /* XXX 1-bit threshold == 1 */ 616 gt_write(gt, GT_ECC_Ctl, ctl); 617 (void)gt_read(gt, GT_ECC_Data_Lo); 618 (void)gt_read(gt, GT_ECC_Data_Hi); 619 (void)gt_read(gt, GT_ECC_Rec); 620 (void)gt_read(gt, GT_ECC_Calc); 621 (void)gt_read(gt, GT_ECC_Addr); /* read last! */ 622 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 623 624 intr_establish(IRQ_ECC, IST_LEVEL, IPL_GTERR, gt_ecc_intr, gt); 625 printf("%s: ECC irpt at %d\n", gt->gt_dev.dv_xname, IRQ_ECC); 626 } 627 #endif /* GT_ECC */ 628 629 630 #ifndef GT_MPP_WATCHDOG 631 void 632 gt_watchdog_init(struct gt_softc *gt) 633 { 634 u_int32_t r; 635 unsigned int omsr; 636 637 omsr = extintr_disable(); 638 639 printf("%s: watchdog", gt->gt_dev.dv_xname); 640 641 /* 642 * handle case where firmware started watchdog 643 */ 644 r = gt_read(gt, GT_WDOG_Config); 645 printf(" status %#x,%#x:", 646 r, gt_read(gt, GT_WDOG_Value)); 647 if ((r & 0x80000000) != 0) { 648 gt_watchdog_sc = gt; /* enabled */ 649 gt_watchdog_state = 1; 650 printf(" firmware-enabled\n"); 651 gt_watchdog_service(); 652 return; 653 } else { 654 printf(" firmware-disabled\n"); 655 } 656 657 extintr_restore(omsr); 658 } 659 660 #else /* GT_MPP_WATCHDOG */ 661 662 void 663 gt_watchdog_init(struct gt_softc *gt) 664 { 665 u_int32_t mpp_watchdog = GT_MPP_WATCHDOG; /* from config */ 666 u_int32_t r; 667 u_int32_t cfgbits; 668 u_int32_t mppbits; 669 u_int32_t mppmask=0; 670 u_int32_t regoff; 671 unsigned int omsr; 672 673 printf("%s: watchdog", gt->gt_dev.dv_xname); 674 675 if (mpp_watchdog == 0) { 676 printf(" not configured\n"); 677 return; 678 } 679 680 #if 0 681 if (afw_wdog_ctl == 1) { 682 printf(" admin disabled\n"); 683 return; 684 } 685 #endif 686 687 omsr = extintr_disable(); 688 689 /* 690 * if firmware started watchdog, we disable and start 691 * from scratch to get it in a known state. 692 * 693 * on GT-64260A we always see 0xffffffff 694 * in both the GT_WDOG_Config_Enb and GT_WDOG_Value regsiters. 695 * Use AFW-supplied flag to determine run state. 696 */ 697 r = gt_read(gt, GT_WDOG_Config); 698 if (r != ~0) { 699 if ((r & GT_WDOG_Config_Enb) != 0) { 700 gt_write(gt, GT_WDOG_Config, 701 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 702 gt_write(gt, GT_WDOG_Config, 703 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 704 } 705 } else { 706 #if 0 707 if (afw_wdog_state == 1) { 708 gt_write(gt, GT_WDOG_Config, 709 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 710 gt_write(gt, GT_WDOG_Config, 711 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 712 } 713 #endif 714 } 715 716 /* 717 * "the watchdog timer can be activated only after 718 * configuring two MPP pins to act as WDE and WDNMI" 719 */ 720 mppbits = 0; 721 cfgbits = 0x3; 722 for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) { 723 if ((mpp_watchdog & cfgbits) == cfgbits) { 724 mppbits = 0x99; 725 mppmask = 0xff; 726 break; 727 } 728 cfgbits <<= 2; 729 if ((mpp_watchdog & cfgbits) == cfgbits) { 730 mppbits = 0x9900; 731 mppmask = 0xff00; 732 break; 733 } 734 cfgbits <<= 6; /* skip unqualified bits */ 735 } 736 if (mppbits == 0) { 737 printf(" config error\n"); 738 extintr_restore(omsr); 739 return; 740 } 741 742 r = gt_read(gt, regoff); 743 r &= ~mppmask; 744 r |= mppbits; 745 gt_write(gt, regoff, r); 746 printf(" mpp %#x %#x", regoff, mppbits); 747 748 gt_write(gt, GT_WDOG_Value, GT_WDOG_NMI_DFLT); 749 750 gt_write(gt, GT_WDOG_Config, 751 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 752 gt_write(gt, GT_WDOG_Config, 753 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 754 755 756 r = gt_read(gt, GT_WDOG_Config), 757 printf(" status %#x,%#x: %s", 758 r, gt_read(gt, GT_WDOG_Value), 759 ((r & GT_WDOG_Config_Enb) != 0) ? "enabled" : "botch"); 760 761 if ((r & GT_WDOG_Config_Enb) != 0) { 762 register_t hid0; 763 764 gt_watchdog_sc = gt; /* enabled */ 765 gt_watchdog_state = 1; 766 767 /* 768 * configure EMCP in HID0 in case it's not already set 769 */ 770 __asm __volatile("sync"); 771 hid0 = mfspr(SPR_HID0); 772 if ((hid0 & HID0_EMCP) == 0) { 773 hid0 |= HID0_EMCP; 774 __asm __volatile("sync"); mtspr(SPR_HID0, hid0); 775 __asm __volatile("sync"); hid0 = mfspr(SPR_HID0); 776 printf(", EMCP set"); 777 } 778 } 779 printf("\n"); 780 781 extintr_restore(omsr); 782 } 783 #endif /* GT_MPP_WATCHDOG */ 784 785 #ifdef DEBUG 786 u_int32_t hid0_print(void); 787 u_int32_t 788 hid0_print() 789 { 790 u_int32_t hid0; 791 __asm __volatile("sync; mfspr %0,1008;" : "=r"(hid0)); 792 printf("hid0: %#x\n", hid0); 793 return hid0; 794 } 795 #endif 796 797 void 798 gt_watchdog_enable(void) 799 { 800 struct gt_softc *gt; 801 unsigned int omsr; 802 803 omsr = extintr_disable(); 804 gt = gt_watchdog_sc; 805 if ((gt != NULL) && (gt_watchdog_state == 0)) { 806 gt_watchdog_state = 1; 807 808 gt_write(gt, GT_WDOG_Config, 809 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 810 gt_write(gt, GT_WDOG_Config, 811 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 812 } 813 extintr_restore(omsr); 814 } 815 816 void 817 gt_watchdog_disable(void) 818 { 819 struct gt_softc *gt; 820 unsigned int omsr; 821 822 omsr = extintr_disable(); 823 gt = gt_watchdog_sc; 824 if ((gt != NULL) && (gt_watchdog_state != 0)) { 825 gt_watchdog_state = 0; 826 827 gt_write(gt, GT_WDOG_Config, 828 (GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT)); 829 gt_write(gt, GT_WDOG_Config, 830 (GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT)); 831 } 832 extintr_restore(omsr); 833 } 834 835 #ifdef DEBUG 836 int inhibit_watchdog_service = 0; 837 #endif 838 void 839 gt_watchdog_service(void) 840 { 841 struct gt_softc *gt = gt_watchdog_sc; 842 843 if ((gt == NULL) || (gt_watchdog_state == 0)) 844 return; /* not enabled */ 845 #ifdef DEBUG 846 if (inhibit_watchdog_service) 847 return; 848 #endif 849 850 gt_write(gt, GT_WDOG_Config, 851 (GT_WDOG_Config_Ctl2a | GT_WDOG_Preset_DFLT)); 852 gt_write(gt, GT_WDOG_Config, 853 (GT_WDOG_Config_Ctl2b | GT_WDOG_Preset_DFLT)); 854 } 855 856 /* 857 * gt_watchdog_reset - force a watchdog reset using Preset_VAL=0 858 */ 859 void 860 gt_watchdog_reset() 861 { 862 struct gt_softc *gt = gt_watchdog_sc; 863 u_int32_t r; 864 865 (void)extintr_disable(); 866 r = gt_read(gt, GT_WDOG_Config); 867 gt_write(gt, GT_WDOG_Config, (GT_WDOG_Config_Ctl1a | 0)); 868 gt_write(gt, GT_WDOG_Config, (GT_WDOG_Config_Ctl1b | 0)); 869 if ((r & GT_WDOG_Config_Enb) != 0) { 870 /* 871 * was enabled, we just toggled it off, toggle on again 872 */ 873 gt_write(gt, GT_WDOG_Config, 874 (GT_WDOG_Config_Ctl1a | 0)); 875 gt_write(gt, GT_WDOG_Config, 876 (GT_WDOG_Config_Ctl1b | 0)); 877 } 878 for(;;); 879 } 880 881 static int 882 gt_devbus_intr(void *arg) 883 { 884 struct gt_softc *gt = (struct gt_softc *)arg; 885 u_int32_t cause; 886 u_int32_t addr; 887 888 cause = gt_read(gt, GT_DEVBUS_ICAUSE); 889 addr = gt_read(gt, GT_DEVBUS_ERR_ADDR); 890 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear irpt */ 891 892 if (cause & GT_DEVBUS_DBurstErr) { 893 printf("%s: Device Bus error: burst violation", 894 gt->gt_dev.dv_xname); 895 if ((cause & GT_DEVBUS_Sel) == 0) 896 printf(", addr %#x", addr); 897 printf("\n"); 898 } 899 if (cause & GT_DEVBUS_DRdyErr) { 900 printf("%s: Device Bus error: ready timer expired", 901 gt->gt_dev.dv_xname); 902 if ((cause & GT_DEVBUS_Sel) != 0) 903 printf(", addr %#x\n", addr); 904 printf("\n"); 905 } 906 907 return (cause != 0); 908 } 909 910 /* 911 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts 912 */ 913 static void 914 gt_devbus_intr_enb(struct gt_softc *gt) 915 { 916 gt_write(gt, GT_DEVBUS_IMASK, 917 GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr); 918 (void)gt_read(gt, GT_DEVBUS_ERR_ADDR); /* clear addr */ 919 gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */ 920 921 intr_establish(IRQ_DEV, IST_LEVEL, IPL_GTERR, gt_devbus_intr, gt); 922 printf("%s: Device Bus Error irpt at %d\n", 923 gt->gt_dev.dv_xname, IRQ_DEV); 924 } 925 926 927 int 928 gt_mii_read( 929 struct device *child, 930 struct device *parent, 931 int phy, 932 int reg) 933 { 934 struct gt_softc * const gt = (struct gt_softc *) parent; 935 uint32_t data; 936 int count = 10000; 937 938 do { 939 DELAY(10); 940 data = gt_read(gt, ETH_ESMIR); 941 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 942 943 if (count == 0) { 944 printf("%s: mii read for phy %d reg %d busied out\n", 945 child->dv_xname, phy, reg); 946 return ETH_ESMIR_Value_GET(data); 947 } 948 949 gt_write(gt, ETH_ESMIR, ETH_ESMIR_READ(phy, reg)); 950 951 count = 10000; 952 do { 953 DELAY(10); 954 data = gt_read(gt, ETH_ESMIR); 955 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 956 957 if (count == 0) 958 printf("%s: mii read for phy %d reg %d timed out\n", 959 child->dv_xname, phy, reg); 960 #if defined(GTMIIDEBUG) 961 printf("%s: mii_read(%d, %d): %#x data %#x\n", 962 child->dv_xname, phy, reg, 963 data, ETH_ESMIR_Value_GET(data)); 964 #endif 965 return ETH_ESMIR_Value_GET(data); 966 } 967 968 void 969 gt_mii_write ( 970 struct device *child, 971 struct device *parent, 972 int phy, int reg, 973 int value) 974 { 975 struct gt_softc * const gt = (struct gt_softc *) parent; 976 uint32_t data; 977 int count = 10000; 978 979 do { 980 DELAY(10); 981 data = gt_read(gt, ETH_ESMIR); 982 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 983 984 if (count == 0) { 985 printf("%s: mii write for phy %d reg %d busied out (busy)\n", 986 child->dv_xname, phy, reg); 987 return; 988 } 989 990 gt_write(gt, ETH_ESMIR, 991 ETH_ESMIR_WRITE(phy, reg, value)); 992 993 count = 10000; 994 do { 995 DELAY(10); 996 data = gt_read(gt, ETH_ESMIR); 997 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 998 999 if (count == 0) 1000 printf("%s: mii write for phy %d reg %d timed out\n", 1001 child->dv_xname, phy, reg); 1002 #if defined(GTMIIDEBUG) 1003 printf("%s: mii_write(%d, %d, %#x)\n", 1004 child->dv_xname, phy, reg, value); 1005 #endif 1006 } 1007 1008
Indexes created Thu Sep 25 06:09:39 GMT 2025