gtethreg.h revision 1.1
1 /* $NetBSD: gtethreg.h,v 1.1 2003/03/05 22:08:20 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DEV_GTETHREG_H_ 41 #define _DEV_GTETHREG_H_ 42 43 #define ETH__BIT(bit) (1U << (bit)) 44 #define ETH__LLBIT(bit) (1LLU << (bit)) 45 #define ETH__MASK(bit) (ETH__BIT(bit) - 1) 46 #define ETH__LLMASK(bit) (ETH__LLBIT(bit) - 1) 47 #define ETH__GEN(n, off) (0x2400+((n) << 10)+(off)) 48 #define ETH__EXT(data, bit, len) (((data) >> (bit)) & ETH__MASK(len)) 49 #define ETH__LLEXT(data, bit, len) (((data) >> (bit)) & ETH__LLMASK(len)) 50 #define ETH__CLR(data, bit, len) ((data) &= ~(ETH__MASK(len) << (bit))) 51 #define ETH__INS(new, bit) ((new) << (bit)) 52 #define ETH__LLINS(new, bit) ((uint64_t)(new) << (bit)) 53 54 /* 55 * Descriptors used for both receive & transmit data. Note that the descriptor 56 * must start on a 4LW boundary. Since the GT accesses the descriptor as 57 * two 64-bit quantities, we must present them 32bit quantities in the right 58 * order based on endianess. 59 */ 60 61 struct gt_eth_desc { 62 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 63 u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ 64 u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */ 65 u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */ 66 u_int32_t ed_bufptr; /* pointer to packet buffer */ 67 #endif 68 #if defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN 69 u_int32_t ed_cmdsts; /* command (hi16)/status (lo16) bits */ 70 u_int32_t ed_lencnt; /* length is hi 16 bits; count (rx) is lo 16 */ 71 u_int32_t ed_bufptr; /* pointer to packet buffer */ 72 u_int32_t ed_nxtptr; /* next descriptor (must be 4LW aligned) */ 73 #endif 74 }; 75 76 /* Table 578: Ethernet TX Descriptor - Command/Status word 77 * All bits except F, EI, AM, O are only valid if TX_CMD_L is also set, 78 * otherwise should be 0 (tx). 79 */ 80 #define TX_STS_LC ETH__BIT(5) /* Late Collision */ 81 #define TX_STS_UR ETH__BIT(6) /* Underrun error */ 82 #define TX_STS_RL ETH__BIT(8) /* Retransmit Limit (excession coll) */ 83 #define TX_STS_COL ETH__BIT(9) /* Collision Occurred */ 84 #define TX_STS_RC(v) ETH__GETBITS(v, 10, 4) /* Retransmit Count */ 85 #define TX_STS_ES ETH__BIT(15) /* Error Summary (LC|UR|RL) */ 86 #define TX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ 87 #define TX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ 88 #define TX_CMD_P ETH__BIT(18) /* Pad Packet */ 89 #define TX_CMD_GC ETH__BIT(22) /* Generate CRC */ 90 #define TX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ 91 #define TX_CMD_AM ETH__BIT(30) /* Auto Mode */ 92 #define TX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ 93 94 #define TX_CMD_FIRST (TX_CMD_F|TX_CMD_O) 95 #define TX_CMD_LAST (TX_CMD_L|TX_CMD_GC|TX_CMD_P|TX_CMD_O) 96 97 /* Table 582: Ethernet RX Descriptor - Command/Status Word 98 * All bits except F, EI, AM, O are only valid if RX_CMD_L is also set, 99 * otherwise should be ignored (rx). 100 */ 101 #define RX_STS_CE ETH__BIT(0) /* CRC Error */ 102 #define RX_STS_COL ETH__BIT(1) /* Collision sensed during reception */ 103 #define RX_STS_LC ETH__BIT(5) /* Late Collision (Reserved) */ 104 #define RX_STS_OR ETH__BIT(6) /* Overrun Error */ 105 #define RX_STS_MFL ETH__BIT(7) /* Max Frame Len Error */ 106 #define RX_STS_SF ETH__BIT(8) /* Short Frame Error (< 64 bytes) */ 107 #define RX_STS_FT ETH__BIT(11) /* Frame Type (1 = 802.3) */ 108 #define RX_STS_M ETH__BIT(12) /* Missed Frame */ 109 #define RX_STS_HE ETH__BIT(13) /* Hash Expired (manual match) */ 110 #define RX_STS_IGMP ETH__BIT(14) /* IGMP Packet */ 111 #define RX_STS_ES ETH__BIT(15) /* Error Summary (CE|COL|LC|OR|MFL|SF) */ 112 #define RX_CMD_L ETH__BIT(16) /* Last - End Of Packet */ 113 #define RX_CMD_F ETH__BIT(17) /* First - Start Of Packet */ 114 #define RX_CMD_EI ETH__BIT(23) /* Enable Interrupt */ 115 #define RX_CMD_AM ETH__BIT(30) /* Auto Mode */ 116 #define RX_CMD_O ETH__BIT(31) /* Ownership (1=GT 0=CPU) */ 117 118 /* Table 586: Hash Table Entry Fields 119 */ 120 #define HSH_V ETH__LLBIT(0) /* Entry is valid */ 121 #define HSH_S ETH__LLBIT(1) /* Skip this entry */ 122 #define HSH_RD ETH__LLBIT(2) /* Receive(1) / Discard (0) */ 123 #define HSH_R ETH__LLBIT(2) /* Receive(1) */ 124 #define HSH_PRIO_GET(v) ETH__LLEXT(v, 51, 2) 125 #define HSH_PRIO_INS(v) ETH__LLINS(v, 51) 126 #define HSH_ADDR_MASK 0x7fffff8LLU 127 #define HSH_LIMIT 12 128 129 130 #define ETH_EPAR 0x2000 /* PHY Address Register */ 131 #define ETH_ESMIR 0x2010 /* SMI Register */ 132 133 #define ETH_BASE_ETH0 0x2400 /* Ethernet0 Register Base */ 134 #define ETH_BASE_ETH1 0x2800 /* Ethernet1 Register Base */ 135 #define ETH_BASE_ETH2 0x2c00 /* Ethernet2 Register Base */ 136 137 #define ETH_EPCR(n) ETH__GEN(n, 0x0000) /* Port Config. Register */ 138 #define ETH_EPCXR(n) ETH__GEN(n, 0x0008) /* Port Config. Extend Reg */ 139 #define ETH_EPCMR(n) ETH__GEN(n, 0x0010) /* Port Command Register */ 140 #define ETH_EPSR(n) ETH__GEN(n, 0x0018) /* Port Status Register */ 141 #define ETH_ESPR(n) ETH__GEN(n, 0x0020) /* Port Serial Parameters Reg */ 142 #define ETH_EHTPR(n) ETH__GEN(n, 0x0028) /* Port Hash Table Pointer Reg*/ 143 #define ETH_EFCSAL(n) ETH__GEN(n, 0x0030) /* Flow Control Src Addr Low */ 144 #define ETH_EFCSAH(n) ETH__GEN(n, 0x0038) /* Flow Control Src Addr High */ 145 #define ETH_ESDCR(n) ETH__GEN(n, 0x0040) /* SDMA Configuration Reg */ 146 #define ETH_ESDCMR(n) ETH__GEN(n, 0x0048) /* SDMA Command Register */ 147 #define ETH_EICR(n) ETH__GEN(n, 0x0050) /* Interrupt Cause Register */ 148 #define ETH_EIMR(n) ETH__GEN(n, 0x0058) /* Interrupt Mask Register */ 149 #define ETH_EFRDP0(n) ETH__GEN(n, 0x0080) /* First Rx Desc Pointer 0 */ 150 #define ETH_EFRDP1(n) ETH__GEN(n, 0x0084) /* First Rx Desc Pointer 1 */ 151 #define ETH_EFRDP2(n) ETH__GEN(n, 0x0088) /* First Rx Desc Pointer 2 */ 152 #define ETH_EFRDP3(n) ETH__GEN(n, 0x008c) /* First Rx Desc Pointer 3 */ 153 #define ETH_ECRDP0(n) ETH__GEN(n, 0x00a0) /* Current Rx Desc Pointer 0 */ 154 #define ETH_ECRDP1(n) ETH__GEN(n, 0x00a4) /* Current Rx Desc Pointer 1 */ 155 #define ETH_ECRDP2(n) ETH__GEN(n, 0x00a8) /* Current Rx Desc Pointer 2 */ 156 #define ETH_ECRDP3(n) ETH__GEN(n, 0x00ac) /* Current Rx Desc Pointer 3 */ 157 #define ETH_ECTDP0(n) ETH__GEN(n, 0x00e0) /* Current Tx Desc Pointer 0 */ 158 #define ETH_ECTDP1(n) ETH__GEN(n, 0x00e4) /* Current Tx Desc Pointer 1 */ 159 #define ETH_EDSCP2P0L(n) ETH__GEN(n, 0x0060) /* IP Differentiated Services 160 CodePoint to Priority0 low */ 161 #define ETH_EDSCP2P0H(n) ETH__GEN(n, 0x0064) /* IP Differentiated Services 162 CodePoint to Priority0 high*/ 163 #define ETH_EDSCP2P1L(n) ETH__GEN(n, 0x0068) /* IP Differentiated Services 164 CodePoint to Priority1 low */ 165 #define ETH_EDSCP2P1H(n) ETH__GEN(n, 0x006c) /* IP Differentiated Services 166 CodePoint to Priority1 high*/ 167 #define ETH_EVPT2P(n) ETH__GEN(n, 0x0068) /* VLAN Prio. Tag to Priority */ 168 #define ETH_EMIBCTRS(n) ETH__GEN(n, 0x0100) /* MIB Counters */ 169 170 #define ETH_EPAR_PhyAD_GET(v, n) (((v) >> ((n) * 5)) & 0x1f) 171 172 #define ETH_ESMIR_READ(phy, reg) (ETH__INS(phy, 16)|\ 173 ETH__INS(reg, 21)|\ 174 ETH_ESMIR_ReadOpcode) 175 #define ETH_ESMIR_WRITE(phy, reg, val) (ETH__INS(phy, 16)|\ 176 ETH__INS(reg, 21)|\ 177 ETH__INS(val, 0)|\ 178 ETH_ESMIR_WriteOpcode) 179 #define ETH_ESMIR_Value_GET(v) ETH__EXT(v, 0, 16) 180 #define ETH_ESMIR_WriteOpcode 0 181 #define ETH_ESMIR_ReadOpcode ETH__BIT(26) 182 #define ETH_ESMIR_ReadValid ETH__BIT(27) 183 #define ETH_ESMIR_Busy ETH__BIT(28) 184 185 /* 186 * Table 597: Port Configuration Register (PCR) 187 * 00:00 PM Promiscuous mode 188 * 0: Normal mode (Frames are only received if the 189 * destination address is found in the hash 190 * table) 191 * 1: Promiscuous mode (Frames are received 192 * regardless of their destination address. 193 * Errored frames are discarded unless the Port 194 * Configuration register's PBF bit is set) 195 * 01:01 RBM Reject Broadcast Mode 196 * 0: Receive broadcast address 197 * 1: Reject frames with broadcast address 198 * Overridden by the promiscuous mode. 199 * 02:02 PBF Pass Bad Frames 200 * (0: Normal mode, 1: Pass bad Frames) 201 * The Ethernet receiver passes to the CPU errored 202 * frames (like fragments and collided packets) 203 * that are normally rejected. 204 * NOTE: Frames are only passed if they 205 * successfully pass address filtering. 206 * 06:03 Reserved 207 * 07:07 EN Enable (0: Disabled, 1: Enable) 208 * When enabled, the ethernet port is ready to 209 * transmit/receive. 210 * 09:08 LPBK Loop Back Mode 211 * 00: Normal mode 212 * 01: Internal loop back mode (TX data is looped 213 * back to the RX lines. No transition is seen 214 * on the interface pins) 215 * 10: External loop back mode (TX data is looped 216 * back to the RX lines and also transmitted 217 * out to the MII interface pins) 218 * 11: Reserved 219 * 10:10 FC Force Collision 220 * 0: Normal mode. 221 * 1: Force Collision on any TX frame. 222 * For RXM test (in Loopback mode). 223 * 11:11 Reserved. 224 * 12:12 HS Hash Size 225 * 0: 8K address filtering 226 * (256KB of memory space required). 227 * 1: 512 address filtering 228 * ( 16KB of memory space required). 229 * 13:13 HM Hash Mode (0: Hash Func. 0; 1: Hash Func. 1) 230 * 14:14 HDM Hash Default Mode 231 * 0: Discard addresses not found in address table 232 * 1: Pass addresses not found in address table 233 * 15:15 HD Duplex Mode (0: Half Duplex, 1: Full Duplex) 234 * NOTE: Valid only when auto-negotiation for 235 * duplex mode is disabled. 236 * 30:16 Reserved 237 * 31:31 ACCS Accelerate Slot Time 238 * (0: Normal mode, 1: Reserved) 239 */ 240 #define ETH_EPCR_PM ETH__BIT(0) 241 #define ETH_EPCR_RBM ETH__BIT(1) 242 #define ETH_EPCR_PBF ETH__BIT(2) 243 #define ETH_EPCR_EN ETH__BIT(7) 244 #define ETH_EPCR_LPBK_GET(v) ETH__BIT(v, 8, 2) 245 #define ETH_EPCR_LPBK_Normal 0 246 #define ETH_EPCR_LPBK_Internal 1 247 #define ETH_EPCR_LPBK_External 2 248 #define ETH_EPCR_FC ETH__BIT(10) 249 250 #define ETH_EPCR_HS ETH__BIT(12) 251 #define ETH_EPCR_HS_8K 0 252 #define ETH_EPCR_HS_512 ETH_EPCR_HS 253 254 #define ETH_EPCR_HM ETH__BIT(13) 255 #define ETH_EPCR_HM_0 0 256 #define ETH_EPCR_HM_1 ETH_EPCR_HM 257 258 #define ETH_EPCR_HDM ETH__BIT(14) 259 #define ETH_EPCR_HDM_Discard 0 260 #define ETH_EPCR_HDM_Pass ETH_EPCR_HDM 261 262 #define ETH_EPCR_HD_Half 0 263 #define ETH_EPCR_HD_Full ETH_EPCR_HD_Full 264 265 #define ETH_EPCR_ACCS ETH__BIT(31) 266 267 268 269 /* 270 * Table 598: Port Configuration Extend Register (PCXR) 271 * 00:00 IGMP IGMP Packets Capture Enable 272 * 0: IGMP packets are treated as normal Multicast 273 * packets. 274 * 1: IGMP packets on IPv4/Ipv6 over Ethernet/802.3 275 * are trapped and sent to high priority RX 276 * queue. 277 * 01:01 SPAN Spanning Tree Packets Capture Enable 278 * 0: BPDU (Bridge Protocol Data Unit) packets are 279 * treated as normal Multicast packets. 280 * 1: BPDU packets are trapped and sent to high 281 * priority RX queue. 282 * 02:02 PAR Partition Enable (0: Normal, 1: Partition) 283 * When more than 61 collisions occur while 284 * transmitting, the port enters Partition mode. 285 * It waits for the first good packet from the 286 * wire and then goes back to Normal mode. Under 287 * Partition mode it continues transmitting, but 288 * it does not receive. 289 * 05:03 PRIOtx Priority weight in the round-robin between high 290 * and low priority TX queues. 291 * 000: 1 pkt from HIGH, 1 pkt from LOW. 292 * 001: 2 pkt from HIGH, 1 pkt from LOW. 293 * 010: 4 pkt from HIGH, 1 pkt from LOW. 294 * 011: 6 pkt from HIGH, 1 pkt from LOW. 295 * 100: 8 pkt from HIGH, 1 pkt from LOW. 296 * 101: 10 pkt from HIGH, 1 pkt from LOW. 297 * 110: 12 pkt from HIGH, 1 pkt from LOW. 298 * 111: All pkt from HIGH, 0 pkt from LOW. LOW is 299 * served only if HIGH is empty. 300 * NOTE: If the HIGH queue is emptied before 301 * finishing the count, the count is reset 302 * until the next first HIGH comes in. 303 * 07:06 PRIOrx Default Priority for Packets Received on this 304 * Port (00: Lowest priority, 11: Highest priority) 305 * 08:08 PRIOrx_Override Override Priority for Packets Received on this 306 * Port (0: Do not override, 1: Override with 307 * <PRIOrx> field) 308 * 09:09 DPLXen Enable Auto-negotiation for Duplex Mode 309 * (0: Enable, 1: Disable) 310 * 11:10 FCTLen Enable Auto-negotiation for 802.3x Flow-control 311 * 0: Enable; When enabled, 1 is written (through 312 * SMI access) to the PHY's register 4 bit 10 313 * to advertise flow-control capability. 314 * 1: Disable; Only enables flow control after the 315 * PHY address is set by the CPU. When changing 316 * the PHY address the flow control 317 * auto-negotiation must be disabled. 318 * 11:11 FLP Force Link Pass 319 * (0: Force Link Pass, 1: Do NOT Force Link pass) 320 * 12:12 FCTL 802.3x Flow-Control Mode (0: Enable, 1: Disable) 321 * NOTE: Only valid when auto negotiation for flow 322 * control is disabled. 323 * 13:13 Reserved 324 * 15:14 MFL Max Frame Length 325 * Maximum packet allowed for reception (including 326 * CRC): 00: 1518 bytes, 01: 1536 bytes, 327 * 10: 2048 bytes, 11: 64K bytes 328 * 16:16 MIBclrMode MIB Counters Clear Mode (0: Clear, 1: No effect) 329 * 17:17 MIBctrMode Reserved. (MBZ) 330 * 18:18 Speed Port Speed (0: 10Mbit/Sec, 1: 100Mbit/Sec) 331 * NOTE: Only valid if SpeedEn bit is set. 332 * 19:19 SpeedEn Enable Auto-negotiation for Speed 333 * (0: Enable, 1: Disable) 334 * 20:20 RMIIen RMII enable 335 * 0: Port functions as MII port 336 * 1: Port functions as RMII port 337 * 21:21 DSCPen DSCP enable 338 * 0: IP DSCP field decoding is disabled. 339 * 1: IP DSCP field decoding is enabled. 340 * 31:22 Reserved 341 */ 342 #define ETH_EPCXR_IGMP ETH__BIT(0) 343 #define ETH_EPCXR_SPAN ETH__BIT(1) 344 #define ETH_EPCXR_PAR ETH__BIT(2) 345 #define ETH_EPCXR_PRIOtx_GET(v) ETH__EXT(v, 3, 3) 346 #define ETH_EPCXR_PRIOrx_GET(v) ETH__EXT(v, 3, 3) 347 #define ETH_EPCXR_PRIOrx_Override ETH__BIT(8) 348 #define ETH_EPCXR_DLPXen ETH__BIT(9) 349 #define ETH_EPCXR_FCTLen ETH__BIT(10) 350 #define ETH_EPCXR_FLP ETH__BIT(11) 351 #define ETH_EPCXR_FCTL ETH__BIT(12) 352 #define ETH_EPCXR_MFL_GET(v) ETH__EXT(v, 14, 2) 353 #define ETH_EPCXR_MFL_1518 0 354 #define ETH_EPCXR_MFL_1536 1 355 #define ETH_EPCXR_MFL_2084 2 356 #define ETH_EPCXR_MFL_64K 3 357 #define ETH_EPCXR_MIBclrMode ETH__BIT(16) 358 #define ETH_EPCXR_MIBctrMode ETH__BIT(17) 359 #define ETH_EPCXR_Speed ETH__BIT(18) 360 #define ETH_EPCXR_SpeedEn ETH__BIT(19) 361 #define ETH_EPCXR_RMIIEn ETH__BIT(20) 362 #define ETH_EPCXR_DSCPEn ETH__BIT(21) 363 364 365 366 /* 367 * Table 599: Port Command Register (PCMR) 368 * 14:00 Reserved 369 * 15:15 FJ Force Jam / Flow Control 370 * When in half-duplex mode, the CPU uses this bit 371 * to force collisions on the Ethernet segment. 372 * When the CPU recognizes that it is going to run 373 * out of receive buffers, it can force the 374 * transmitter to send jam frames, forcing 375 * collisions on the wire. To allow transmission 376 * on the Ethernet segment, the CPU must clear the 377 * FJ bit when more resources are available. When 378 * in full-duplex and flow-control is enabled, this 379 * bit causes the port's transmitter to send 380 * flow-control PAUSE packets. The CPU must reset 381 * this bit when more resources are available. 382 * 31:16 Reserved 383 */ 384 385 #define ETH_EPCMR_FJ ETH__BIT(15) 386 387 388 /* 389 * Table 600: Port Status Register (PSR) -- Read Only 390 * 00:00 Speed Indicates Port Speed (0: 10Mbs, 1: 100Mbs) 391 * 01:01 Duplex Indicates Port Duplex Mode (0: Half, 1: Full) 392 * 02:02 Fctl Indicates Flow-control Mode 393 * (0: enabled, 1: disabled) 394 * 03:03 Link Indicates Link Status (0: down, 1: up) 395 * 04:04 Pause Indicates that the port is in flow-control 396 * disabled state. This bit is set when an IEEE 397 * 802.3x flow-control PAUSE (XOFF) packet is 398 * received (assuming that flow-control is 399 * enabled and the port is in full-duplex mode). 400 * Reset when XON is received, or when the XOFF 401 * timer has expired. 402 * 05:05 TxLow Tx Low Priority Status 403 * Indicates the status of the low priority 404 * transmit queue: (0: Stopped, 1: Running) 405 * 06:06 TxHigh Tx High Priority Status 406 * Indicates the status of the high priority 407 * transmit queue: (0: Stopped, 1: Running) 408 * 07:07 TXinProg TX in Progress 409 * Indicates that the port's transmitter is in an 410 * active transmission state. 411 * 31:08 Reserved 412 */ 413 #define ETH_EPSR_Speed ETH__BIT(0) 414 #define ETH_EPSR_Duplex ETH__BIT(1) 415 #define ETH_EPSR_Fctl ETH__BIT(2) 416 #define ETH_EPSR_Link ETH__BIT(3) 417 #define ETH_EPSR_Pause ETH__BIT(4) 418 #define ETH_EPSR_TxLow ETH__BIT(5) 419 #define ETH_EPSR_TxHigh ETH__BIT(6) 420 #define ETH_EPSR_TXinProg ETH__BIT(7) 421 422 423 /* 424 * Table 601: Serial Parameters Register (SPR) 425 * 01:00 JAM_LENGTH Two bits to determine the JAM Length 426 * (in Backpressure) as follows: 427 * 00 = 12K bit-times 428 * 01 = 24K bit-times 429 * 10 = 32K bit-times 430 * 11 = 48K bit-times 431 * 06:02 JAM_IPG Five bits to determine the JAM IPG. 432 * The step is four bit-times. The value may vary 433 * between 4 bit time to 124. 434 * 11:07 IPG_JAM_TO_DATA Five bits to determine the IPG JAM to DATA. 435 * The step is four bit-times. The value may vary 436 * between 4 bit time to 124. 437 * 16:12 IPG_DATA Inter-Packet Gap (IPG) 438 * The step is four bit-times. The value may vary 439 * between 12 bit time to 124. 440 * NOTE: These bits may be changed only when the 441 * Ethernet ports is disabled. 442 * 21:17 Data_Blind Data Blinder 443 * The number of nibbles from the beginning of the 444 * IPG, in which the IPG counter is restarted when 445 * detecting a carrier activity. Following this 446 * value, the port enters the Data Blinder zone and 447 * does not reset the IPG counter. This ensures 448 * fair access to the medium. 449 * The default is 10 hex (64 bit times - 2/3 of the 450 * default IPG). The step is 4 bit-times. Valid 451 * range is 3 to 1F hex nibbles. 452 * NOTE: These bits may be only changed when the 453 * Ethernet port is disabled. 454 * 22:22 Limit4 The number of consecutive packet collisions that 455 * occur before the collision counter is reset. 456 * 0: The port resets its collision counter after 457 * 16 consecutive retransmit trials and 458 * restarts the Backoff algorithm. 459 * 1: The port resets its collision counter and 460 * restarts the Backoff algorithm after 4 461 * consecutive transmit trials. 462 * 31:23 Reserved 463 */ 464 #define ETH_ESPR_JAM_LENGTH_GET(v) ETH__EXT(v, 0, 2) 465 #define ETH_ESPR_JAM_IPG_GET(v) ETH__EXT(v, 2, 5) 466 #define ETH_ESPR_IPG_JAM_TO_DATA_GET(v) ETH__EXT(v, 7, 5) 467 #define ETH_ESPR_IPG_DATA_GET(v) ETH__EXT(v, 12, 5) 468 #define ETH_ESPR_Data_Bilnd_GET(v) ETH__EXT(v, 17, 5) 469 #define ETH_ESPR_Limit4(v) ETH__BIT(22) 470 471 /* 472 * Table 602: Hash Table Pointer Register (HTPR) 473 * 31:00 HTP 32-bit pointer to the address table. 474 * Bits [2:0] must be set to zero. 475 */ 476 477 /* 478 * Table 603: Flow Control Source Address Low (FCSAL) 479 * 15:0 SA[15:0] Source Address 480 * The least significant bits of the source 481 * address for the port. This address is used for 482 * Flow Control. 483 * 31:16 Reserved 484 */ 485 486 /* 487 * Table 604: Flow Control Source Address High (FCSAH) 488 * 31:0 SA[47:16] Source Address 489 * The most significant bits of the source address 490 * for the port. This address is used for Flow 491 * Control. 492 */ 493 494 495 /* 496 * Table 605: SDMA Configuration Register (SDCR) 497 * 01:00 Reserved 498 * 05:02 RC Retransmit Count 499 * Sets the maximum number of retransmits per 500 * packet. After executing retransmit for RC 501 * times, the TX SDMA closes the descriptor with a 502 * Retransmit Limit error indication and processes 503 * the next packet. When RC is set to 0, the 504 * number of retransmits is unlimited. In this 505 * case, the retransmit process is only terminated 506 * if CPU issues an Abort command. 507 * 06:06 BLMR Big/Little Endian Receive Mode 508 * The DMA supports Big or Little Endian 509 * configurations on a per channel basis. The BLMR 510 * bit only affects data transfer to memory. 511 * 0: Big Endian 512 * 1: Little Endian 513 * 07:07 BLMT Big/Little Endian Transmit Mode 514 * The DMA supports Big or Little Endian 515 * configurations on a per channel basis. The BLMT 516 * bit only affects data transfer from memory. 517 * 0: Big Endian 518 * 1: Little Endian 519 * 08:08 POVR PCI Override 520 * When set, causes the SDMA to direct all its 521 * accesses in PCI_0 direction and overrides 522 * normal address decoding process. 523 * 09:09 RIFB Receive Interrupt on Frame Boundaries 524 * When set, the SDMA Rx generates interrupts only 525 * on frame boundaries (i.e. after writing the 526 * frame status to the descriptor). 527 * 11:10 Reserved 528 * 13:12 BSZ Burst Size 529 * Sets the maximum burst size for SDMA 530 * transactions: 531 * 00: Burst is limited to 1 64bit words. 532 * 01: Burst is limited to 2 64bit words. 533 * 10: Burst is limited to 4 64bit words. 534 * 11: Burst is limited to 8 64bit words. 535 * 31:14 Reserved 536 */ 537 #define ETH_ESDCR_RC_GET(v) ETH__EXT(v, 2, 4) 538 #define ETH_ESDCR_BLMR ETH__BIT(6) 539 #define ETH_ESDCR_BLMT ETH__BIT(7) 540 #define ETH_ESDCR_POVR ETH__BIT(8) 541 #define ETH_ESDCR_RIFB ETH__BIT(9) 542 #define ETH_ESDCR_BSZ_GET(v) ETH__EXT(v, 12, 2) 543 #define ETH_ESDCR_BSZ_SET(v, n) (ETH__CLR(v, 12, 2),\ 544 (v) |= ETH__INS(n, 12)) 545 #define ETH_ESDCR_BSZ_1 0 546 #define ETH_ESDCR_BSZ_2 1 547 #define ETH_ESDCR_BSZ_4 2 548 #define ETH_ESDCR_BSZ_8 3 549 550 #define ETH_ESDCR_BSZ_Strings { "1 64-bit word", "2 64-bit words", \ 551 "4 64-bit words", "8 64-bit words" } 552 553 /* 554 * Table 606: SDMA Command Register (SDCMR) 555 * 06:00 Reserved 556 * 07:07 ERD Enable RX DMA. 557 * Set to 1 by the CPU to cause the SDMA to start 558 * a receive process. Cleared when the CPU issues 559 * an Abort Receive command. 560 * 14:08 Reserved 561 * 15:15 AR Abort Receive 562 * Set to 1 by the CPU to abort a receive SDMA 563 * operation. When the AR bit is set, the SDMA 564 * aborts its current operation and moves to IDLE. 565 * No descriptor is closed. The AR bit is cleared 566 * upon entering IDLE. After setting the AR bit, 567 * the CPU must poll the bit to verify that the 568 * abort sequence is completed. 569 * 16:16 STDH Stop TX High 570 * Set to 1 by the CPU to stop the transmission 571 * process from the high priority queue at the end 572 * of the current frame. An interrupt is generated 573 * when the stop command has been executed. 574 * Writing 1 to STDH resets TXDH bit. 575 * Writing 0 to this bit has no effect. 576 * 17:17 STDL Stop TX Low 577 * Set to 1 by the CPU to stop the transmission 578 * process from the low priority queue at the end 579 * of the current frame. An interrupt is generated 580 * when the stop command has been executed. 581 * Writing 1 to STDL resets TXDL bit. 582 * Writing 0 to this bit has no effect. 583 * 22:18 Reserved 584 * 23:23 TXDH Start Tx High 585 * Set to 1 by the CPU to cause the SDMA to fetch 586 * the first descriptor and start a transmit 587 * process from the high priority Tx queue. 588 * Writing 1 to TXDH resets STDH bit. 589 * Writing 0 to this bit has no effect. 590 * 24:24 TXDL Start Tx Low 591 * Set to 1 by the CPU to cause the SDMA to fetch 592 * the first descriptor and start a transmit 593 * process from the low priority Tx queue. 594 * Writing 1 to TXDL resets STDL bit. 595 * Writing 0 to this bit has no effect. 596 * 30:25 Reserved 597 * 31:31 AT Abort Transmit 598 * Set to 1 by the CPU to abort a transmit DMA 599 * operation. When the AT bit is set, the SDMA 600 * aborts its current operation and moves to IDLE. 601 * No descriptor is closed. Cleared upon entering 602 * IDLE. After setting AT bit, the CPU must poll 603 * it in order to verify that the abort sequence 604 * is completed. 605 */ 606 #define ETH_ESDCMR_ERD ETH__BIT(7) 607 #define ETH_ESDCMR_AR ETH__BIT(15) 608 #define ETH_ESDCMR_STDH ETH__BIT(16) 609 #define ETH_ESDCMR_STDL ETH__BIT(17) 610 #define ETH_ESDCMR_TXDH ETH__BIT(23) 611 #define ETH_ESDCMR_TXDL ETH__BIT(24) 612 #define ETH_ESDCMR_AT ETH__BIT(31) 613 614 /* 615 * Table 607: Interrupt Cause Register (ICR) 616 * 00:00 RxBuffer Rx Buffer Return 617 * Indicates an Rx buffer returned to CPU ownership 618 * or that the port finished reception of a Rx 619 * frame in either priority queues. 620 * NOTE: In order to get a Rx Buffer return per 621 * priority queue, use bit 19:16. This bit is 622 * set upon closing any Rx descriptor which 623 * has its EI bit set. To limit the 624 * interrupts to frame (rather than buffer) 625 * boundaries, the user must set SDMA 626 * Configuration register's RIFB bit. When 627 * the RIFB bit is set, an interrupt 628 * generates only upon closing the first 629 * descriptor of a received packet, if this 630 * descriptor has it EI bit set. 631 * 01:01 Reserved 632 * 02:02 TxBufferHigh Tx Buffer for High priority Queue 633 * Indicates a Tx buffer returned to CPU ownership 634 * or that the port finished transmission of a Tx 635 * frame. 636 * NOTE: This bit is set upon closing any Tx 637 * descriptor which has its EI bit set. To 638 * limit the interrupts to frame (rather than 639 * buffer) boundaries, the user must set EI 640 * only in the last descriptor. 641 * 03:03 TxBufferLow Tx Buffer for Low Priority Queue 642 * Indicates a Tx buffer returned to CPU ownership 643 * or that the port finished transmission of a Tx 644 * frame. 645 * NOTE: This bit is set upon closing any Tx 646 * descriptor which has its EI bit set. To 647 * limit the interrupts to frame (rather than 648 * buffer) boundaries, the user must set EI 649 * only in the last descriptor. 650 * 05:04 Reserved 651 * 06:06 TxEndHigh Tx End for High Priority Queue 652 * Indicates that the Tx DMA stopped processing the 653 * high priority queue after stop command, or that 654 * it reached the end of the high priority 655 * descriptor chain. 656 * 07:07 TxEndLow Tx End for Low Priority Queue 657 * Indicates that the Tx DMA stopped processing the 658 * low priority queue after stop command, or that 659 * it reached the end of the low priority 660 * descriptor chain. 661 * 08:08 RxError Rx Resource Error 662 * Indicates a Rx resource error event in one of 663 * the priority queues. 664 * NOTE: To get a Rx Resource Error Indication per 665 * priority queue, use bit 23:20. 666 * 09:09 Reserved 667 * 10:10 TxErrorHigh Tx Resource Error for High Priority Queue 668 * Indicates a Tx resource error event during 669 * packet transmission from the high priority queue 670 * 11:11 TxErrorLow Tx Resource Error for Low Priority Queue 671 * Indicates a Tx resource error event during 672 * packet transmission from the low priority queue 673 * 12:12 RxOVR Rx Overrun 674 * Indicates an overrun event that occurred during 675 * reception of a packet. 676 * 13:13 TxUdr Tx Underrun 677 * Indicates an underrun event that occurred during 678 * transmission of packet from either queue. 679 * 15:14 Reserved 680 * 16:16 RxBuffer-Queue[0] Rx Buffer Return in Priority Queue[0] 681 * Indicates a Rx buffer returned to CPU ownership 682 * or that the port completed reception of a Rx 683 * frame in a receive priority queue[0] 684 * 17:17 RxBuffer-Queue[1] Rx Buffer Return in Priority Queue[1] 685 * Indicates a Rx buffer returned to CPU ownership 686 * or that the port completed reception of a Rx 687 * frame in a receive priority queue[1]. 688 * 18:18 RxBuffer-Queue[2] Rx Buffer Return in Priority Queue[2] 689 * Indicates a Rx buffer returned to CPU ownership 690 * or that the port completed reception of a Rx 691 * frame in a receive priority queue[2]. 692 * 19:19 RxBuffer-Queue[3] Rx Buffer Return in Priority Queue[3] 693 * Indicates a Rx buffer returned to CPU ownership 694 * or that the port completed reception of a Rx 695 * frame in a receive priority queue[3]. 696 * 20:20 RxError-Queue[0] Rx Resource Error in Priority Queue[0] 697 * Indicates a Rx resource error event in receive 698 * priority queue[0]. 699 * 21:21 RxError-Queue[1] Rx Resource Error in Priority Queue[1] 700 * Indicates a Rx resource error event in receive 701 * priority queue[1]. 702 * 22:22 RxError-Queue[2] Rx Resource Error in Priority Queue[2] 703 * Indicates a Rx resource error event in receive 704 * priority queue[2]. 705 * 23:23 RxError-Queue[3] Rx Resource Error in Priority Queue[3] 706 * Indicates a Rx resource error event in receive 707 * priority queue[3]. 708 * 27:24 Reserved 709 * 28:29 MIIPhySTC MII PHY Status Change 710 * Indicates a status change reported by the PHY 711 * connected to this port. Set when the MII 712 * management interface block identifies a change 713 * in PHY's register 1. 714 * 29:29 SMIdone SMI Command Done 715 * Indicates that the SMI completed a MII 716 * management command (either read or write) that 717 * was initiated by the CPU writing to the SMI 718 * register. 719 * 30:30 Reserved 720 * 31:31 EtherIntSum Ethernet Interrupt Summary 721 * This bit is a logical OR of the (unmasked) bits 722 * [30:04] in the Interrupt Cause register. 723 */ 724 725 #define ETH_IR_RxBuffer ETH__BIT(0) 726 #define ETH_IR_TxBufferHigh ETH__BIT(2) 727 #define ETH_IR_TxBufferLow ETH__BIT(3) 728 #define ETH_IR_TxEndHigh ETH__BIT(6) 729 #define ETH_IR_TxEndLow ETH__BIT(7) 730 #define ETH_IR_RxError ETH__BIT(8) 731 #define ETH_IR_TxErrorHigh ETH__BIT(10) 732 #define ETH_IR_TxErrorLow ETH__BIT(11) 733 #define ETH_IR_RxOVR ETH__BIT(12) 734 #define ETH_IR_TxUdr ETH__BIT(13) 735 #define ETH_IR_RxBuffer_0 ETH__BIT(16) 736 #define ETH_IR_RxBuffer_1 ETH__BIT(17) 737 #define ETH_IR_RxBuffer_2 ETH__BIT(18) 738 #define ETH_IR_RxBuffer_3 ETH__BIT(19) 739 #define ETH_IR_RxBuffer_GET(v) ETH__EXT(v, 16, 4) 740 #define ETH_IR_RxError_0 ETH__BIT(20) 741 #define ETH_IR_RxError_1 ETH__BIT(21) 742 #define ETH_IR_RxError_2 ETH__BIT(22) 743 #define ETH_IR_RxError_3 ETH__BIT(23) 744 #define ETH_IR_RxError_GET(v) ETH__EXT(v, 20, 4) 745 #define ETH_IR_RxBits (ETH_IR_RxBuffer_0|\ 746 ETH_IR_RxBuffer_1|\ 747 ETH_IR_RxBuffer_2|\ 748 ETH_IR_RxBuffer_3|\ 749 ETH_IR_RxError_0|\ 750 ETH_IR_RxError_1|\ 751 ETH_IR_RxError_2|\ 752 ETH_IR_RxError_3) 753 #define ETH_IR_MIIPhySTC ETH__BIT(28) 754 #define ETH_IR_SMIdone ETH__BIT(29) 755 #define ETH_IR_EtherIntSum ETH__BIT(31) 756 #define ETH_IR_Summary ETH__BIT(31) 757 758 /* 759 * Table 608: Interrupt Mask Register (IMR) 760 * 31:00 Various Mask bits for the Interrupt Cause register. 761 */ 762 763 /* 764 * Table 609: IP Differentiated Services CodePoint to Priority0 low (DSCP2P0L), 765 * 31:00 Priority0_low The LSB priority bits for DSCP[31:0] entries. 766 */ 767 768 /* 769 * Table 610: IP Differentiated Services CodePoint to Priority0 high (DSCP2P0H) 770 * 31:00 Priority0_high The LSB priority bits for DSCP[63:32] entries. 771 */ 772 773 /* 774 * Table 611: IP Differentiated Services CodePoint to Priority1 low (DSCP2P1L) 775 * 31:00 Priority1_low The MSB priority bits for DSCP[31:0] entries. 776 */ 777 778 /* 779 * Table 612: IP Differentiated Services CodePoint to Priority1 high (DSCP2P1H) 780 * 31:00 Priority1_high The MSB priority bit for DSCP[63:32] entries. 781 */ 782 783 /* 784 * Table 613: VLAN Priority Tag to Priority (VPT2P) 785 * 07:00 Priority0 The LSB priority bits for VLAN Priority[7:0] 786 * entries. 787 * 15:08 Priority1 The MSB priority bits for VLAN Priority[7:0] 788 * entries. 789 * 31:16 Reserved 790 */ 791 #endif /* _DEV_GTETHREG_H_ */ 792
Indexes created Sun Sep 28 16:09:52 GMT 2025