Home | History | Annotate | Line # | Download | only in marvell
      1  1.5   msaitoh /*	$NetBSD: gtidmacreg.h,v 1.5 2021/11/10 17:19:30 msaitoh Exp $	*/
      2  1.1  kiyohara /*
      3  1.1  kiyohara  * Copyright (c) 2008, 2009 KIYOHARA Takashi
      4  1.1  kiyohara  * All rights reserved.
      5  1.1  kiyohara  *
      6  1.1  kiyohara  * Redistribution and use in source and binary forms, with or without
      7  1.1  kiyohara  * modification, are permitted provided that the following conditions
      8  1.1  kiyohara  * are met:
      9  1.1  kiyohara  * 1. Redistributions of source code must retain the above copyright
     10  1.1  kiyohara  *    notice, this list of conditions and the following disclaimer.
     11  1.1  kiyohara  * 2. Redistributions in binary form must reproduce the above copyright
     12  1.1  kiyohara  *    notice, this list of conditions and the following disclaimer in the
     13  1.1  kiyohara  *    documentation and/or other materials provided with the distribution.
     14  1.1  kiyohara  *
     15  1.1  kiyohara  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  1.1  kiyohara  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  1.1  kiyohara  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  1.1  kiyohara  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  1.1  kiyohara  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  1.1  kiyohara  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  1.1  kiyohara  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  1.1  kiyohara  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  1.1  kiyohara  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  1.1  kiyohara  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  1.1  kiyohara  * POSSIBILITY OF SUCH DAMAGE.
     26  1.1  kiyohara  */
     27  1.1  kiyohara 
     28  1.1  kiyohara #ifndef _GTIDMACREG_H_
     29  1.1  kiyohara #define _GTIDMACREG_H_
     30  1.1  kiyohara 
     31  1.1  kiyohara /*
     32  1.1  kiyohara  * IDMA Controller Interface Registers / XOR Engine Control Registers
     33  1.1  kiyohara  */
     34  1.1  kiyohara 
     35  1.1  kiyohara #define GTIDMAC_SIZE		0x1000
     36  1.1  kiyohara 
     37  1.1  kiyohara 
     38  1.1  kiyohara #define GTIDMAC_NWINDOW		8
     39  1.1  kiyohara #define GTIDMAC_NREMAP		4
     40  1.1  kiyohara #define GTIDMAC_NACCPROT	4			/* Num Access Protect */
     41  1.1  kiyohara #define GTIDMAC_NINTRRUPT	4
     42  1.1  kiyohara #define GTIDMAC_MAXXFER		(16 * 1024 * 1024 - 1)	/* 16M - 1 Byte */
     43  1.1  kiyohara 
     44  1.1  kiyohara #define MVXORE_NWINDOW		8
     45  1.1  kiyohara #define MVXORE_NREMAP		4
     46  1.1  kiyohara #define MVXORE_MAXXFER		(16 * 1024 * 1024 - 1)	/* 16M - 1 Byte */
     47  1.1  kiyohara #define MVXORE_NSRC		8
     48  1.1  kiyohara 
     49  1.1  kiyohara 
     50  1.1  kiyohara #define GTIDMAC_CHAN2BASE(c)	((((c) & 0x4) << 6) + (((c) & 0x3) << 2))
     51  1.3  kiyohara #define MVXORE_PORT2BASE(sc, p)	\
     52  1.3  kiyohara     (((sc)->sc_gtidmac_nchan == 0 && (p) == 0) ? -0x100 : 0x000)
     53  1.3  kiyohara #define MVXORE_CHAN2BASE(sc, c)	\
     54  1.4  kiyohara     (MVXORE_PORT2BASE(sc, (c) & 0xe) + (((c) & 0x1) << 2))
     55  1.3  kiyohara 
     56  1.1  kiyohara 
     57  1.1  kiyohara /* IDMA Descriptor Register Map */
     58  1.1  kiyohara #define GTIDMAC_CIDMABCR(c)	/* Chan IDMA Byte Count */ \
     59  1.1  kiyohara 				(GTIDMAC_CHAN2BASE(c) + 0x0800)
     60  1.1  kiyohara #define GTIDMAC_CIDMABCR_BYTECNT_MASK 0x00ffffff
     61  1.1  kiyohara #define GTIDMAC_CIDMABCR_BCLEFT		(1 << 30)	/* Left Byte Count */
     62  1.1  kiyohara #define GTIDMAC_CIDMABCR_OWN		(1 << 31)	/* Ownership Bit */
     63  1.1  kiyohara #define GTIDMAC_CIDMASAR(c)	/* Chan IDMA Source Address */ \
     64  1.1  kiyohara 				(GTIDMAC_CHAN2BASE(c) + 0x0810)
     65  1.1  kiyohara #define GTIDMAC_CIDMADAR(c)	/* Chan IDMA Destination Address */ \
     66  1.1  kiyohara 				(GTIDMAC_CHAN2BASE(c) + 0x0820)
     67  1.1  kiyohara #define GTIDMAC_CNDPR(c)	/* Chan Next Descriptor Pointer */ \
     68  1.1  kiyohara 				(GTIDMAC_CHAN2BASE(c) + 0x0830)
     69  1.1  kiyohara #define GTIDMAC_CCDPR(c)	/* Chan Current Descriptor Pointer */ \
     70  1.1  kiyohara 				(GTIDMAC_CHAN2BASE(c) + 0x0870)
     71  1.1  kiyohara /* IDMA Control Register Map */
     72  1.1  kiyohara #define GTIDMAC_CCLR(c)		/* Chan Control Low */ \
     73  1.1  kiyohara 				(GTIDMAC_CHAN2BASE(c) + 0x0840)
     74  1.1  kiyohara #define GTIDMAC_CCLR_DBL_MASK		(7 << 0)	/* DstBurstLimit */
     75  1.1  kiyohara #define GTIDMAC_CCLR_DBL_8B		(0 << 0)
     76  1.1  kiyohara #define GTIDMAC_CCLR_DBL_16B		(1 << 0)
     77  1.1  kiyohara #define GTIDMAC_CCLR_DBL_32B		(3 << 0)
     78  1.1  kiyohara #define GTIDMAC_CCLR_DBL_64B		(7 << 0)
     79  1.1  kiyohara #define GTIDMAC_CCLR_DBL_128B		(4 << 0)
     80  1.1  kiyohara #define GTIDMAC_CCLR_SRCHOLD		(1 << 3)	/* Source Hold */
     81  1.1  kiyohara #define GTIDMAC_CCLR_DESTHOLD		(1 << 5)	/* Destination Hold */
     82  1.1  kiyohara #define GTIDMAC_CCLR_SBL_MASK		(7 << 6)	/* SrcBurstLimit */
     83  1.1  kiyohara #define GTIDMAC_CCLR_SBL_8B		(0 << 6)
     84  1.1  kiyohara #define GTIDMAC_CCLR_SBL_16B		(1 << 6)
     85  1.1  kiyohara #define GTIDMAC_CCLR_SBL_32B		(3 << 6)
     86  1.1  kiyohara #define GTIDMAC_CCLR_SBL_64B		(7 << 6)
     87  1.1  kiyohara #define GTIDMAC_CCLR_SBL_128B		(4 << 6)
     88  1.1  kiyohara #define GTIDMAC_CCLR_CHAINMODE_C	(0 << 9)	/* Chained Mode */
     89  1.1  kiyohara #define GTIDMAC_CCLR_CHAINMODE_NC	(1 << 9)	/* Non-Chained Mode */
     90  1.1  kiyohara #define GTIDMAC_CCLR_INTMODE		(1 << 10)	/* Interrupt Mode */
     91  1.1  kiyohara #define GTIDMAC_CCLR_INTMODE_NULL	(1 << 10)	/*   Next Desc NULL */
     92  1.1  kiyohara #define GTIDMAC_CCLR_TRANSFERMODE_D	(0 << 11)	/* Transfer Mode */
     93  1.1  kiyohara #define GTIDMAC_CCLR_TRANSFERMODE_B	(1 << 11)	/*   Demand/Block */
     94  1.1  kiyohara #define GTIDMAC_CCLR_CHANEN		(1 << 12)	/* Channel Enable */
     95  1.1  kiyohara #define GTIDMAC_CCLR_FETCHND		(1 << 13)	/* Fetch Next Desc */
     96  1.1  kiyohara #define GTIDMAC_CCLR_CHANACT		(1 << 14)	/* IDMA Chan Active */
     97  1.1  kiyohara #define GTIDMAC_CCLR_CDEN		(1 << 17)	/* Close Desc Enable */
     98  1.1  kiyohara #define GTIDMAC_CCLR_ABR		(1 << 20)	/* Channel Abort */
     99  1.1  kiyohara #define GTIDMAC_CCLR_SADDROVR_MASK	(3 << 21)	/* Override Src Addr */
    100  1.1  kiyohara #define GTIDMAC_CCLR_SADDROVR_NO	(0 << 21)
    101  1.1  kiyohara #define GTIDMAC_CCLR_SADDROVR_BAR1	(1 << 21)
    102  1.1  kiyohara #define GTIDMAC_CCLR_SADDROVR_BAR2	(2 << 21)
    103  1.1  kiyohara #define GTIDMAC_CCLR_SADDROVR_BAR3	(3 << 21)
    104  1.1  kiyohara #define GTIDMAC_CCLR_NADDROVR_MASK	(3 << 21)	/* Override Next Addr */
    105  1.1  kiyohara #define GTIDMAC_CCLR_NADDROVR_NO	(0 << 21)
    106  1.1  kiyohara #define GTIDMAC_CCLR_NADDROVR_BAR1	(1 << 21)
    107  1.1  kiyohara #define GTIDMAC_CCLR_NADDROVR_BAR2	(2 << 21)
    108  1.1  kiyohara #define GTIDMAC_CCLR_NADDROVR_BAR3	(3 << 21)
    109  1.1  kiyohara #define GTIDMAC_CCLR_DESCMODE_64K	(0 << 31)
    110  1.1  kiyohara #define GTIDMAC_CCLR_DESCMODE_16M	(1 << 31)
    111  1.1  kiyohara #define GTIDMAC_CCHR(c)		/* Chan Control High */ \
    112  1.1  kiyohara 				(GTIDMAC_CHAN2BASE(c) + 0x0880)
    113  1.1  kiyohara #define GTIDMAC_CCHR_ENDIAN_BE		(0 << 0)	/* big endian */
    114  1.1  kiyohara #define GTIDMAC_CCHR_ENDIAN_LE		(1 << 0)	/* little endian */
    115  1.1  kiyohara #define GTIDMAC_CCHR_DESCBYTESWAP	(1 << 1)	/* Desc Byte Swap */
    116  1.1  kiyohara #define GTIDMAC_ARBR(c)		(0x0860 + (((c) & 0x04) << 6)) /* Arbitrate ??*/
    117  1.1  kiyohara #define GTIDMAC_XTOR(c)		(0x08d0 + (((c) & 0x04) << 6)) /* x-bar t/o?? */
    118  1.1  kiyohara /* IDMA Interrupt Register Map */
    119  1.1  kiyohara #define GTIDMAC_ICR(c)		(0x08c0 + (((c) & 0x04) << 6)) /* Intr Cause */
    120  1.1  kiyohara #define GTIDMAC_IMR(c)		(0x08c4 + (((c) & 0x04) << 6)) /* Intr Mask */
    121  1.1  kiyohara #define GTIDMAC_I_BITS			8
    122  1.1  kiyohara #define GTIDMAC_I(c, b)			((b) << (GTIDMAC_I_BITS * ((c) & 0x3)))
    123  1.1  kiyohara #define GTIDMAC_I_COMP			(1 << 0)	/* Completion */
    124  1.1  kiyohara #define GTIDMAC_I_ADDRMISS		(1 << 1)	/* Address Miss */
    125  1.1  kiyohara #define GTIDMAC_I_ACCPROT		(1 << 2)	/* Acc Prot Violation */
    126  1.1  kiyohara #define GTIDMAC_I_WRPROT		(1 << 3)	/* Write Protect */
    127  1.1  kiyohara #define GTIDMAC_I_OWN			(1 << 4)	/* Ownership Violation*/
    128  1.1  kiyohara #define GTIDMAC_EAR(c)		(0x08c8 + (((c) & 0x04) << 6)) /* Err Address */
    129  1.1  kiyohara #define GTIDMAC_ESR(c)		(0x08cc + (((c) & 0x04) << 6)) /* Err Select */
    130  1.1  kiyohara #define GTIDMAC_ESR_SEL			0x1f
    131  1.1  kiyohara 
    132  1.1  kiyohara /* XOR Engine Control Registers */
    133  1.3  kiyohara #define MVXORE_XECHAR(sc, p)	/* Channel Arbiter */ \
    134  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0900)
    135  1.1  kiyohara #define MVXORE_XECHAR_SLICEOWN(s, c)	((c) << (s))
    136  1.3  kiyohara #define MVXORE_XEXCR(sc, x)	/* Configuration */ \
    137  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0910)
    138  1.1  kiyohara #define MVXORE_XEXCR_OM_MASK		(7 << 0)	/* Operation Mode */
    139  1.1  kiyohara #define MVXORE_XEXCR_OM_XOR		(0 << 0)
    140  1.1  kiyohara #define MVXORE_XEXCR_OM_CRC32		(1 << 0)
    141  1.1  kiyohara #define MVXORE_XEXCR_OM_DMA		(2 << 0)
    142  1.1  kiyohara #define MVXORE_XEXCR_OM_ECC		(3 << 0)	/* ECC cleanup ope */
    143  1.1  kiyohara #define MVXORE_XEXCR_OM_MEMINIT		(4 << 0)
    144  1.1  kiyohara #define MVXORE_XEXCR_SBL_MASK		(7 << 4)	/* SrcBurstLimit */
    145  1.1  kiyohara #define MVXORE_XEXCR_SBL_32B		(2 << 4)
    146  1.1  kiyohara #define MVXORE_XEXCR_SBL_64B		(3 << 4)
    147  1.1  kiyohara #define MVXORE_XEXCR_SBL_128B		(4 << 4)
    148  1.1  kiyohara #define MVXORE_XEXCR_DBL_MASK		(7 << 8)	/* SrcBurstLimit */
    149  1.1  kiyohara #define MVXORE_XEXCR_DBL_32B		(2 << 8)
    150  1.1  kiyohara #define MVXORE_XEXCR_DBL_64B		(3 << 8)
    151  1.1  kiyohara #define MVXORE_XEXCR_DBL_128B		(4 << 8)
    152  1.5   msaitoh #define MVXORE_XEXCR_DRDRESSWP		(1 << 12)	/* Endianness Swap */
    153  1.1  kiyohara #define MVXORE_XEXCR_DWRREQSWP		(1 << 13)	/*  ReadReq/WriteRes */
    154  1.1  kiyohara #define MVXORE_XEXCR_DESSWP		(1 << 14)	/*  Desc read/write */
    155  1.1  kiyohara #define MVXORE_XEXCR_REGACCPROTECT	(1 << 15)	/* Reg Access protect */
    156  1.3  kiyohara #define MVXORE_XEXACTR(sc, x)	/* Activation */ \
    157  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0920)
    158  1.1  kiyohara #define MVXORE_XEXACTR_XESTART		(1 << 0)
    159  1.1  kiyohara #define MVXORE_XEXACTR_XESTOP		(1 << 1)
    160  1.1  kiyohara #define MVXORE_XEXACTR_XEPAUSE		(1 << 2)
    161  1.1  kiyohara #define MVXORE_XEXACTR_XERESTART	(1 << 3)
    162  1.1  kiyohara #define MVXORE_XEXACTR_XESTATUS_MASK	(3 << 4)
    163  1.1  kiyohara #define MVXORE_XEXACTR_XESTATUS_NA	(0 << 4)	/* not active */
    164  1.1  kiyohara #define MVXORE_XEXACTR_XESTATUS_ACT	(1 << 4)	/* active */
    165  1.1  kiyohara #define MVXORE_XEXACTR_XESTATUS_P	(2 << 4)	/* paused */
    166  1.1  kiyohara /* XOR Engine Interrupt Registers */
    167  1.3  kiyohara #define MVXORE_XEICR(sc, p)	/* Interrupt Cause */ \
    168  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0930)
    169  1.3  kiyohara #define MVXORE_XEIMR(sc, p)	/* Interrupt Mask */ \
    170  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0940)
    171  1.1  kiyohara #define MVXORE_I_BITS			16
    172  1.1  kiyohara #define MVXORE_I(c, b)			((b) << (MVXORE_I_BITS * (c)))
    173  1.1  kiyohara #define MVXORE_I_EOD			(1 << 0)	/* End of Descriptor */
    174  1.1  kiyohara #define MVXORE_I_EOC			(1 << 1)	/* End of Chain */
    175  1.1  kiyohara #define MVXORE_I_STOPPED		(1 << 2)
    176  1.1  kiyohara #define MVXORE_I_PAUSED			(1 << 3)
    177  1.1  kiyohara #define MVXORE_I_ADDRDECODE		(1 << 4)
    178  1.1  kiyohara #define MVXORE_I_ACCPROT		(1 << 5)	/* Access Protect */
    179  1.1  kiyohara #define MVXORE_I_WRPROT			(1 << 6)	/* Write Protect */
    180  1.1  kiyohara #define MVXORE_I_OWN			(1 << 7)	/* Ownership */
    181  1.1  kiyohara #define MVXORE_I_INTPARITY		(1 << 8)	/* Parity error */
    182  1.1  kiyohara #define MVXORE_I_XBAR			(1 << 9)	/* Crossbar Parity E */
    183  1.3  kiyohara #define MVXORE_XEECR(sc, p)	/* Error Cause */ \
    184  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0950)
    185  1.1  kiyohara #define MVXORE_XEECR_ERRORTYPE_MASK	0x0000001f
    186  1.3  kiyohara #define MVXORE_XEEAR(sc, p)	/* Error Address */ \
    187  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0960)
    188  1.1  kiyohara 
    189  1.1  kiyohara /* IDMA Address Decoding Registers Map */
    190  1.1  kiyohara #define GTIDMAC_BARX(r)		(0x0a00 + ((r) << 3))	/* Base Address x */
    191  1.1  kiyohara #define GTIDMAC_BARX_TARGET(t)		((t) & 0xf)
    192  1.1  kiyohara #define GTIDMAC_BARX_ATTR(a)		(((a) & 0xff) << 8)
    193  1.1  kiyohara #define GTIDMAC_BARX_BASE(b)		((b) & 0xffff0000)
    194  1.1  kiyohara #define GTIDMAC_SRX(r)		(0x0a04 + ((r) << 3))	/* Size x */
    195  1.1  kiyohara #define GTIDMAC_SRX_SIZE(s)		(((s) - 1) & 0xffff0000)
    196  1.1  kiyohara #define GTIDMAC_HARXR(x)	(0x0a60 + ((x) << 2))	/* High Addr Remap x */
    197  1.1  kiyohara #define GTIDMAC_BAER		0x0a80			/* Base Addr Enable */
    198  1.1  kiyohara #define GTIDMAC_BAER_EN(w)		(1 << (w))
    199  1.1  kiyohara #define GTIDMAC_CXAPR(x)	(0x0a70 + ((x) << 2))	/* Chan x Acs Protect */
    200  1.1  kiyohara #define GTIDMAC_CXAPR_WINACC(w, ac)	((ac) << ((w) << 1))
    201  1.1  kiyohara #define GTIDMAC_CXAPR_WINACC_NOAA	0x0		/* No access allowed */
    202  1.1  kiyohara #define GTIDMAC_CXAPR_WINACC_RO		0x1		/* Read Only */
    203  1.1  kiyohara #define GTIDMAC_CXAPR_WINACC_RESV	0x2		/* Reserved */
    204  1.1  kiyohara #define GTIDMAC_CXAPR_WINACC_FA		0x3		/* Full access */
    205  1.1  kiyohara 
    206  1.1  kiyohara /* XOR Engine Descriptor Registers */
    207  1.3  kiyohara #define MVXORE_XEXNDPR(sc, x)	/* Next Desc Pointer */ \
    208  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0b00)
    209  1.3  kiyohara #define MVXORE_XEXCDPR(sc, x)	/* Current Desc Ptr */ \
    210  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0b10)
    211  1.3  kiyohara #define MVXORE_XEXBCR(sc, x)	/* Byte Count */ \
    212  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0b20)
    213  1.1  kiyohara /* XOR Engine Address Decording Registers */
    214  1.3  kiyohara #define MVXORE_XEXWCR(sc, x)	/* Window Control */ \
    215  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0b40)
    216  1.1  kiyohara #define MVXORE_XEXWCR_WINEN(w)		(1 << (w))
    217  1.1  kiyohara #define MVXORE_XEXWCR_WINACC(w, ac)	((ac) << (((w) << 1) + 16))
    218  1.1  kiyohara #define MVXORE_XEXWCR_WINACC_NOAA	0x0		/* No access allowed */
    219  1.1  kiyohara #define MVXORE_XEXWCR_WINACC_RO		0x1		/* Read Only */
    220  1.1  kiyohara #define MVXORE_XEXWCR_WINACC_RESV	0x2		/* Reserved */
    221  1.1  kiyohara #define MVXORE_XEXWCR_WINACC_FA		0x3		/* Full access */
    222  1.3  kiyohara #define MVXORE_XEBARX(sc, p, w)	/* Base Address */ \
    223  1.3  kiyohara 			(MVXORE_PORT2BASE((sc), (p)) + 0x0b50 + ((w) << 2))
    224  1.1  kiyohara #define MVXORE_XEBARX_TARGET(t)		((t) & 0xf)
    225  1.1  kiyohara #define MVXORE_XEBARX_ATTR(a)		(((a) & 0xff) << 8)
    226  1.1  kiyohara #define MVXORE_XEBARX_BASE(b)		((b) & 0xffff0000)
    227  1.3  kiyohara #define MVXORE_XESMRX(sc, p, w)	/* Size Mask */ \
    228  1.3  kiyohara 			(MVXORE_PORT2BASE((sc), (p)) + 0x0b70 + ((w) << 2))
    229  1.1  kiyohara #define MVXORE_XESMRX_SIZE(s)		(((s) - 1) & 0xffff0000)
    230  1.3  kiyohara #define MVXORE_XEHARRX(sc, p, w)/* High Address Remap */ \
    231  1.3  kiyohara 			(MVXORE_PORT2BASE((sc), (p)) + 0x0b90 + ((w) << 2))
    232  1.3  kiyohara #define MVXORE_XEXAOCR(sc, x)	/* Addr Override Ctrl */ \
    233  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0ba0)
    234  1.1  kiyohara /* XOR Engine ECC/MemInit Registers */
    235  1.3  kiyohara #define MVXORE_XEXDPR(sc, x)	/* Destination Ptr */ \
    236  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0bb0)
    237  1.3  kiyohara #define MVXORE_XEXBSR(sc, x)	/* Block Size */ \
    238  1.3  kiyohara 				(MVXORE_CHAN2BASE((sc), (x)) + 0x0bc0)
    239  1.3  kiyohara #define MVXORE_XETMCR(sc, p)	/* Timer Mode Control */ \
    240  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0bd0)
    241  1.1  kiyohara #define MVXORE_XETMCR_TIMEREN		(1 << 0)
    242  1.1  kiyohara #define MVXORE_XETMCR_SECTIONSIZECTRL_MASK  0x1f
    243  1.1  kiyohara #define MVXORE_XETMCR_SECTIONSIZECTRL_SHIFT 8
    244  1.3  kiyohara #define MVXORE_XETMIVR(sc, p)	/* Tmr Mode Init Val */ \
    245  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0bd4)
    246  1.3  kiyohara #define MVXORE_XETMCVR(sc, p)	/* Tmr Mode Curr Val */ \
    247  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0bd8)
    248  1.3  kiyohara #define MVXORE_XEIVRL(sc, p)	/* Initial Value Low */ \
    249  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0be0)
    250  1.3  kiyohara #define MVXORE_XEIVRH(sc, p)	/* Initial Value High */ \
    251  1.3  kiyohara 				(MVXORE_PORT2BASE((sc), (p)) + 0x0be4)
    252  1.1  kiyohara 
    253  1.1  kiyohara 
    254  1.1  kiyohara struct gtidmac_desc {
    255  1.2  kiyohara #if BYTE_ORDER == LITTLE_ENDIAN
    256  1.1  kiyohara 	union {
    257  1.1  kiyohara 		struct {
    258  1.1  kiyohara 			uint16_t rbc;	/* Remind BC */
    259  1.1  kiyohara 			uint16_t bcnt;
    260  1.1  kiyohara 		} mode64k;
    261  1.1  kiyohara 		struct {
    262  1.1  kiyohara 			uint32_t bcnt;
    263  1.1  kiyohara 		} mode16m;
    264  1.1  kiyohara 	} bc;			/* Byte Count */
    265  1.1  kiyohara 	uint32_t srcaddr;	/* Source Address */
    266  1.1  kiyohara 	uint32_t dstaddr;	/* Destination Address */
    267  1.1  kiyohara 	uint32_t nextdp;	/* Next Descriptor Pointer */
    268  1.2  kiyohara #else
    269  1.2  kiyohara 	uint32_t srcaddr;	/* Source Address */
    270  1.2  kiyohara 	union {
    271  1.2  kiyohara 		struct {
    272  1.2  kiyohara 			uint16_t rbc;	/* Remind BC */
    273  1.2  kiyohara 			uint16_t bcnt;
    274  1.2  kiyohara 		} mode64k;
    275  1.2  kiyohara 		struct {
    276  1.2  kiyohara 			uint32_t bcnt;
    277  1.2  kiyohara 		} mode16m;
    278  1.2  kiyohara 	} bc;			/* Byte Count */
    279  1.2  kiyohara 	uint32_t nextdp;	/* Next Descriptor Pointer */
    280  1.2  kiyohara 	uint32_t dstaddr;	/* Destination Address */
    281  1.2  kiyohara #endif
    282  1.1  kiyohara } __packed;
    283  1.1  kiyohara 
    284  1.1  kiyohara #define GTIDMAC_DESC_BYTECOUNT_MASK	0x00ffffff
    285  1.1  kiyohara 
    286  1.1  kiyohara struct mvxore_desc {
    287  1.1  kiyohara 	uint32_t stat;				/* Status */
    288  1.1  kiyohara 	uint32_t result;			/* CRC-32 Result */
    289  1.1  kiyohara 	uint32_t cmd;				/* Command */
    290  1.1  kiyohara 	uint32_t nextda;			/* Next Descriptor Address */
    291  1.1  kiyohara 	uint32_t bcnt;				/* Byte Count */
    292  1.1  kiyohara 	uint32_t dstaddr;			/* Destination Address */
    293  1.1  kiyohara 	uint32_t srcaddr[MVXORE_NSRC];	/* Source Address #0-7 */
    294  1.1  kiyohara 	uint32_t reserved[2];
    295  1.1  kiyohara } __packed;
    296  1.1  kiyohara 
    297  1.1  kiyohara #define MVXORE_DESC_STAT_SUCCESS	(1 << 30)
    298  1.1  kiyohara #define MVXORE_DESC_STAT_OWN		(1 << 31)
    299  1.1  kiyohara 
    300  1.1  kiyohara #define MVXORE_DESC_CMD_SRCCMD(s)	(1 << (s))
    301  1.1  kiyohara #define MVXORE_DESC_CMD_CRCLAST		(1 << 30) /* Indicate last desc CRC32 */
    302  1.1  kiyohara #define MVXORE_DESC_CMD_EODINTEN	(1 << 31) /* End of Desc Intr Enable */
    303  1.1  kiyohara 
    304  1.1  kiyohara #define MVXORE_DESC_BCNT_MASK	0x00ffffff
    305  1.1  kiyohara 
    306  1.1  kiyohara #endif	/* _GTIDMACREG_H_ */
    307