gtidmacreg.h revision 1.1
1 /* $NetBSD: gtidmacreg.h,v 1.1 2010/04/28 13:51:56 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008, 2009 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _GTIDMACREG_H_ 29 #define _GTIDMACREG_H_ 30 31 /* 32 * IDMA Controller Interface Registers / XOR Engine Control Registers 33 */ 34 35 #define GTIDMAC_SIZE 0x1000 36 37 38 #define GTIDMAC_NWINDOW 8 39 #define GTIDMAC_NREMAP 4 40 #define GTIDMAC_NACCPROT 4 /* Num Access Protect */ 41 #define GTIDMAC_NINTRRUPT 4 42 #define GTIDMAC_MAXXFER (16 * 1024 * 1024 - 1) /* 16M - 1 Byte */ 43 44 #define MVXORE_NWINDOW 8 45 #define MVXORE_NREMAP 4 46 #define MVXORE_NINTRRUPT 2 47 #define MVXORE_MAXXFER (16 * 1024 * 1024 - 1) /* 16M - 1 Byte */ 48 #define MVXORE_NSRC 8 49 50 51 #define GTIDMAC_CHAN2BASE(c) ((((c) & 0x4) << 6) + (((c) & 0x3) << 2)) 52 53 /* IDMA Descriptor Register Map */ 54 #define GTIDMAC_CIDMABCR(c) /* Chan IDMA Byte Count */ \ 55 (GTIDMAC_CHAN2BASE(c) + 0x0800) 56 #define GTIDMAC_CIDMABCR_BYTECNT_MASK 0x00ffffff 57 #define GTIDMAC_CIDMABCR_BCLEFT (1 << 30) /* Left Byte Count */ 58 #define GTIDMAC_CIDMABCR_OWN (1 << 31) /* Ownership Bit */ 59 #define GTIDMAC_CIDMASAR(c) /* Chan IDMA Source Address */ \ 60 (GTIDMAC_CHAN2BASE(c) + 0x0810) 61 #define GTIDMAC_CIDMADAR(c) /* Chan IDMA Destination Address */ \ 62 (GTIDMAC_CHAN2BASE(c) + 0x0820) 63 #define GTIDMAC_CNDPR(c) /* Chan Next Descriptor Pointer */ \ 64 (GTIDMAC_CHAN2BASE(c) + 0x0830) 65 #define GTIDMAC_CCDPR(c) /* Chan Current Descriptor Pointer */ \ 66 (GTIDMAC_CHAN2BASE(c) + 0x0870) 67 /* IDMA Control Register Map */ 68 #define GTIDMAC_CCLR(c) /* Chan Control Low */ \ 69 (GTIDMAC_CHAN2BASE(c) + 0x0840) 70 #define GTIDMAC_CCLR_DBL_MASK (7 << 0) /* DstBurstLimit */ 71 #define GTIDMAC_CCLR_DBL_8B (0 << 0) 72 #define GTIDMAC_CCLR_DBL_16B (1 << 0) 73 #define GTIDMAC_CCLR_DBL_32B (3 << 0) 74 #define GTIDMAC_CCLR_DBL_64B (7 << 0) 75 #define GTIDMAC_CCLR_DBL_128B (4 << 0) 76 #define GTIDMAC_CCLR_SRCHOLD (1 << 3) /* Source Hold */ 77 #define GTIDMAC_CCLR_DESTHOLD (1 << 5) /* Destination Hold */ 78 #define GTIDMAC_CCLR_SBL_MASK (7 << 6) /* SrcBurstLimit */ 79 #define GTIDMAC_CCLR_SBL_8B (0 << 6) 80 #define GTIDMAC_CCLR_SBL_16B (1 << 6) 81 #define GTIDMAC_CCLR_SBL_32B (3 << 6) 82 #define GTIDMAC_CCLR_SBL_64B (7 << 6) 83 #define GTIDMAC_CCLR_SBL_128B (4 << 6) 84 #define GTIDMAC_CCLR_CHAINMODE_C (0 << 9) /* Chained Mode */ 85 #define GTIDMAC_CCLR_CHAINMODE_NC (1 << 9) /* Non-Chained Mode */ 86 #define GTIDMAC_CCLR_INTMODE (1 << 10) /* Interrupt Mode */ 87 #define GTIDMAC_CCLR_INTMODE_NULL (1 << 10) /* Next Desc NULL */ 88 #define GTIDMAC_CCLR_TRANSFERMODE_D (0 << 11) /* Transfer Mode */ 89 #define GTIDMAC_CCLR_TRANSFERMODE_B (1 << 11) /* Demand/Block */ 90 #define GTIDMAC_CCLR_CHANEN (1 << 12) /* Channel Enable */ 91 #define GTIDMAC_CCLR_FETCHND (1 << 13) /* Fetch Next Desc */ 92 #define GTIDMAC_CCLR_CHANACT (1 << 14) /* IDMA Chan Active */ 93 #define GTIDMAC_CCLR_CDEN (1 << 17) /* Close Desc Enable */ 94 #define GTIDMAC_CCLR_ABR (1 << 20) /* Channel Abort */ 95 #define GTIDMAC_CCLR_SADDROVR_MASK (3 << 21) /* Override Src Addr */ 96 #define GTIDMAC_CCLR_SADDROVR_NO (0 << 21) 97 #define GTIDMAC_CCLR_SADDROVR_BAR1 (1 << 21) 98 #define GTIDMAC_CCLR_SADDROVR_BAR2 (2 << 21) 99 #define GTIDMAC_CCLR_SADDROVR_BAR3 (3 << 21) 100 #define GTIDMAC_CCLR_NADDROVR_MASK (3 << 21) /* Override Next Addr */ 101 #define GTIDMAC_CCLR_NADDROVR_NO (0 << 21) 102 #define GTIDMAC_CCLR_NADDROVR_BAR1 (1 << 21) 103 #define GTIDMAC_CCLR_NADDROVR_BAR2 (2 << 21) 104 #define GTIDMAC_CCLR_NADDROVR_BAR3 (3 << 21) 105 #define GTIDMAC_CCLR_DESCMODE_64K (0 << 31) 106 #define GTIDMAC_CCLR_DESCMODE_16M (1 << 31) 107 #define GTIDMAC_CCHR(c) /* Chan Control High */ \ 108 (GTIDMAC_CHAN2BASE(c) + 0x0880) 109 #define GTIDMAC_CCHR_ENDIAN_BE (0 << 0) /* big endian */ 110 #define GTIDMAC_CCHR_ENDIAN_LE (1 << 0) /* little endian */ 111 #define GTIDMAC_CCHR_DESCBYTESWAP (1 << 1) /* Desc Byte Swap */ 112 #define GTIDMAC_ARBR(c) (0x0860 + (((c) & 0x04) << 6)) /* Arbitrate ??*/ 113 #define GTIDMAC_XTOR(c) (0x08d0 + (((c) & 0x04) << 6)) /* x-bar t/o?? */ 114 /* IDMA Interrupt Register Map */ 115 #define GTIDMAC_ICR(c) (0x08c0 + (((c) & 0x04) << 6)) /* Intr Cause */ 116 #define GTIDMAC_IMR(c) (0x08c4 + (((c) & 0x04) << 6)) /* Intr Mask */ 117 #define GTIDMAC_I_BITS 8 118 #define GTIDMAC_I(c, b) ((b) << (GTIDMAC_I_BITS * ((c) & 0x3))) 119 #define GTIDMAC_I_COMP (1 << 0) /* Completion */ 120 #define GTIDMAC_I_ADDRMISS (1 << 1) /* Address Miss */ 121 #define GTIDMAC_I_ACCPROT (1 << 2) /* Acc Prot Violation */ 122 #define GTIDMAC_I_WRPROT (1 << 3) /* Write Protect */ 123 #define GTIDMAC_I_OWN (1 << 4) /* Ownership Violation*/ 124 #define GTIDMAC_EAR(c) (0x08c8 + (((c) & 0x04) << 6)) /* Err Address */ 125 #define GTIDMAC_ESR(c) (0x08cc + (((c) & 0x04) << 6)) /* Err Select */ 126 #define GTIDMAC_ESR_SEL 0x1f 127 128 /* XOR Engine Control Registers */ 129 #define MVXORE_XECHAR 0x0900 /* Channel Arbiter */ 130 #define MVXORE_XECHAR_SLICEOWN(s, c) ((c) << (s)) 131 #define MVXORE_XEXCR(x) (0x0910 + ((x) << 2)) /* Configuration */ 132 #define MVXORE_XEXCR_OM_MASK (7 << 0) /* Operation Mode */ 133 #define MVXORE_XEXCR_OM_XOR (0 << 0) 134 #define MVXORE_XEXCR_OM_CRC32 (1 << 0) 135 #define MVXORE_XEXCR_OM_DMA (2 << 0) 136 #define MVXORE_XEXCR_OM_ECC (3 << 0) /* ECC cleanup ope */ 137 #define MVXORE_XEXCR_OM_MEMINIT (4 << 0) 138 #define MVXORE_XEXCR_SBL_MASK (7 << 4) /* SrcBurstLimit */ 139 #define MVXORE_XEXCR_SBL_32B (2 << 4) 140 #define MVXORE_XEXCR_SBL_64B (3 << 4) 141 #define MVXORE_XEXCR_SBL_128B (4 << 4) 142 #define MVXORE_XEXCR_DBL_MASK (7 << 8) /* SrcBurstLimit */ 143 #define MVXORE_XEXCR_DBL_32B (2 << 8) 144 #define MVXORE_XEXCR_DBL_64B (3 << 8) 145 #define MVXORE_XEXCR_DBL_128B (4 << 8) 146 #define MVXORE_XEXCR_DRDRESSWP (1 << 12) /* Endianess Swap */ 147 #define MVXORE_XEXCR_DWRREQSWP (1 << 13) /* ReadReq/WriteRes */ 148 #define MVXORE_XEXCR_DESSWP (1 << 14) /* Desc read/write */ 149 #define MVXORE_XEXCR_REGACCPROTECT (1 << 15) /* Reg Access protect */ 150 #define MVXORE_XEXACTR(x) (0x0920 + ((x) << 2)) /* Activation */ 151 #define MVXORE_XEXACTR_XESTART (1 << 0) 152 #define MVXORE_XEXACTR_XESTOP (1 << 1) 153 #define MVXORE_XEXACTR_XEPAUSE (1 << 2) 154 #define MVXORE_XEXACTR_XERESTART (1 << 3) 155 #define MVXORE_XEXACTR_XESTATUS_MASK (3 << 4) 156 #define MVXORE_XEXACTR_XESTATUS_NA (0 << 4) /* not active */ 157 #define MVXORE_XEXACTR_XESTATUS_ACT (1 << 4) /* active */ 158 #define MVXORE_XEXACTR_XESTATUS_P (2 << 4) /* paused */ 159 /* XOR Engine Interrupt Registers */ 160 #define MVXORE_XEICR 0x0930 /* Interrupt Cause */ 161 #define MVXORE_XEIMR 0x0940 /* Interrupt Mask */ 162 #define MVXORE_I_BITS 16 163 #define MVXORE_I(c, b) ((b) << (MVXORE_I_BITS * (c))) 164 #define MVXORE_I_EOD (1 << 0) /* End of Descriptor */ 165 #define MVXORE_I_EOC (1 << 1) /* End of Chain */ 166 #define MVXORE_I_STOPPED (1 << 2) 167 #define MVXORE_I_PAUSED (1 << 3) 168 #define MVXORE_I_ADDRDECODE (1 << 4) 169 #define MVXORE_I_ACCPROT (1 << 5) /* Access Protect */ 170 #define MVXORE_I_WRPROT (1 << 6) /* Write Protect */ 171 #define MVXORE_I_OWN (1 << 7) /* Ownership */ 172 #define MVXORE_I_INTPARITY (1 << 8) /* Parity error */ 173 #define MVXORE_I_XBAR (1 << 9) /* Crossbar Parity E */ 174 #define MVXORE_XEECR 0x0950 /* Error Cause */ 175 #define MVXORE_XEECR_ERRORTYPE_MASK 0x0000001f 176 #define MVXORE_XEEAR 0x0960 /* Error Address */ 177 178 /* IDMA Address Decoding Registers Map */ 179 #define GTIDMAC_BARX(r) (0x0a00 + ((r) << 3)) /* Base Address x */ 180 #define GTIDMAC_BARX_TARGET(t) ((t) & 0xf) 181 #define GTIDMAC_BARX_ATTR(a) (((a) & 0xff) << 8) 182 #define GTIDMAC_BARX_BASE(b) ((b) & 0xffff0000) 183 #define GTIDMAC_SRX(r) (0x0a04 + ((r) << 3)) /* Size x */ 184 #define GTIDMAC_SRX_SIZE(s) (((s) - 1) & 0xffff0000) 185 #define GTIDMAC_HARXR(x) (0x0a60 + ((x) << 2)) /* High Addr Remap x */ 186 #define GTIDMAC_BAER 0x0a80 /* Base Addr Enable */ 187 #define GTIDMAC_BAER_EN(w) (1 << (w)) 188 #define GTIDMAC_CXAPR(x) (0x0a70 + ((x) << 2)) /* Chan x Acs Protect */ 189 #define GTIDMAC_CXAPR_WINACC(w, ac) ((ac) << ((w) << 1)) 190 #define GTIDMAC_CXAPR_WINACC_NOAA 0x0 /* No access allowed */ 191 #define GTIDMAC_CXAPR_WINACC_RO 0x1 /* Read Only */ 192 #define GTIDMAC_CXAPR_WINACC_RESV 0x2 /* Reserved */ 193 #define GTIDMAC_CXAPR_WINACC_FA 0x3 /* Full access */ 194 195 /* XOR Engine Descriptor Registers */ 196 #define MVXORE_XEXNDPR(x) (0x0b00 + ((x) << 2)) /* Next Desc Pointer */ 197 #define MVXORE_XEXCDPR(x) (0x0b10 + ((x) << 2)) /* Current Desc Ptr */ 198 #define MVXORE_XEXBCR(x) (0x0b20 + ((x) << 2)) /* Byte Count */ 199 /* XOR Engine Address Decording Registers */ 200 #define MVXORE_XEXWCR(x) (0x0b40 + ((x) << 2)) /* Window Control */ 201 #define MVXORE_XEXWCR_WINEN(w) (1 << (w)) 202 #define MVXORE_XEXWCR_WINACC(w, ac) ((ac) << (((w) << 1) + 16)) 203 #define MVXORE_XEXWCR_WINACC_NOAA 0x0 /* No access allowed */ 204 #define MVXORE_XEXWCR_WINACC_RO 0x1 /* Read Only */ 205 #define MVXORE_XEXWCR_WINACC_RESV 0x2 /* Reserved */ 206 #define MVXORE_XEXWCR_WINACC_FA 0x3 /* Full access */ 207 #define MVXORE_XEBARX(x) (0x0b50 + ((x) << 2)) /* Base Address */ 208 #define MVXORE_XEBARX_TARGET(t) ((t) & 0xf) 209 #define MVXORE_XEBARX_ATTR(a) (((a) & 0xff) << 8) 210 #define MVXORE_XEBARX_BASE(b) ((b) & 0xffff0000) 211 #define MVXORE_XESMRX(x) (0x0b70 + ((x) << 2)) /* Size Mask */ 212 #define MVXORE_XESMRX_SIZE(s) (((s) - 1) & 0xffff0000) 213 #define MVXORE_XEHARRX(x) (0x0b90 + ((x) << 2)) /* High Address Remap */ 214 #define MVXORE_XEXAOCR(x) (0x0ba0 + ((x) << 2)) /* Addr Override Ctrl */ 215 /* XOR Engine ECC/MemInit Registers */ 216 #define MVXORE_XEXDPR(x) (0x0bb0 + ((x) << 2)) /* Destination Ptr */ 217 #define MVXORE_XEXBSR(x) (0x0bc0 + ((x) << 2)) /* Block Size */ 218 #define MVXORE_XETMCR 0x0bd0 /* Timer Mode Control */ 219 #define MVXORE_XETMCR_TIMEREN (1 << 0) 220 #define MVXORE_XETMCR_SECTIONSIZECTRL_MASK 0x1f 221 #define MVXORE_XETMCR_SECTIONSIZECTRL_SHIFT 8 222 #define MVXORE_XETMIVR 0x0bd4 /* Tmr Mode Init Val */ 223 #define MVXORE_XETMCVR 0x0bd8 /* Tmr Mode Curr Val */ 224 #define MVXORE_XEIVRL 0x0be0 /* Initial Value Low */ 225 #define MVXORE_XEIVRH 0x0be4 /* Initial Value High */ 226 227 228 struct gtidmac_desc { 229 union { 230 struct { 231 uint16_t rbc; /* Remind BC */ 232 uint16_t bcnt; 233 } mode64k; 234 struct { 235 uint32_t bcnt; 236 } mode16m; 237 } bc; /* Byte Count */ 238 uint32_t srcaddr; /* Source Address */ 239 uint32_t dstaddr; /* Destination Address */ 240 uint32_t nextdp; /* Next Descriptor Pointer */ 241 } __packed; 242 243 #define GTIDMAC_DESC_BYTECOUNT_MASK 0x00ffffff 244 245 struct mvxore_desc { 246 uint32_t stat; /* Status */ 247 uint32_t result; /* CRC-32 Result */ 248 uint32_t cmd; /* Command */ 249 uint32_t nextda; /* Next Descriptor Address */ 250 uint32_t bcnt; /* Byte Count */ 251 uint32_t dstaddr; /* Destination Address */ 252 uint32_t srcaddr[MVXORE_NSRC]; /* Source Address #0-7 */ 253 uint32_t reserved[2]; 254 } __packed; 255 256 #define MVXORE_DESC_STAT_SUCCESS (1 << 30) 257 #define MVXORE_DESC_STAT_OWN (1 << 31) 258 259 #define MVXORE_DESC_CMD_SRCCMD(s) (1 << (s)) 260 #define MVXORE_DESC_CMD_CRCLAST (1 << 30) /* Indicate last desc CRC32 */ 261 #define MVXORE_DESC_CMD_EODINTEN (1 << 31) /* End of Desc Intr Enable */ 262 263 #define MVXORE_DESC_BCNT_MASK 0x00ffffff 264 265 #endif /* _GTIDMACREG_H_ */ 266
Indexes created Mon Sep 29 21:09:56 GMT 2025