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gtpci.c revision 1.10
      1  1.10  lukem /*	$NetBSD: gtpci.c,v 1.10 2003/07/14 15:47:17 lukem Exp $	*/
      2   1.1   matt 
      3   1.1   matt /*
      4   1.1   matt  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
      5   1.1   matt  * All rights reserved.
      6   1.1   matt  *
      7   1.1   matt  * Redistribution and use in source and binary forms, with or without
      8   1.1   matt  * modification, are permitted provided that the following conditions
      9   1.1   matt  * are met:
     10   1.1   matt  * 1. Redistributions of source code must retain the above copyright
     11   1.1   matt  *    notice, this list of conditions and the following disclaimer.
     12   1.1   matt  * 2. Redistributions in binary form must reproduce the above copyright
     13   1.1   matt  *    notice, this list of conditions and the following disclaimer in the
     14   1.1   matt  *    documentation and/or other materials provided with the distribution.
     15   1.1   matt  * 3. All advertising materials mentioning features or use of this software
     16   1.1   matt  *    must display the following acknowledgement:
     17   1.1   matt  *      This product includes software developed for the NetBSD Project by
     18   1.1   matt  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
     19   1.1   matt  * 4. The name of Allegro Networks, Inc. may not be used to endorse
     20   1.1   matt  *    or promote products derived from this software without specific prior
     21   1.1   matt  *    written permission.
     22   1.1   matt  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
     23   1.1   matt  *    or promote products derived from this software without specific prior
     24   1.1   matt  *    written permission.
     25   1.1   matt  *
     26   1.1   matt  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
     27   1.1   matt  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     28   1.1   matt  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
     29   1.1   matt  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     30   1.1   matt  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
     31   1.1   matt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32   1.1   matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33   1.1   matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34   1.1   matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35   1.1   matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36   1.1   matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37   1.1   matt  * POSSIBILITY OF SUCH DAMAGE.
     38   1.1   matt  */
     39  1.10  lukem 
     40  1.10  lukem #include <sys/cdefs.h>
     41  1.10  lukem __KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.10 2003/07/14 15:47:17 lukem Exp $");
     42   1.1   matt 
     43   1.1   matt #include "opt_marvell.h"
     44   1.1   matt #include <sys/param.h>
     45   1.1   matt #include <sys/device.h>
     46   1.1   matt #include <sys/extent.h>
     47   1.1   matt #include <sys/malloc.h>
     48   1.1   matt #include <lib/libkern/libkern.h>
     49   1.1   matt 
     50   1.1   matt #define _BUS_SPACE_PRIVATE
     51   1.1   matt #define _BUS_DMA_PRIVATE
     52   1.1   matt #include <machine/bus.h>
     53   1.1   matt #include <machine/intr.h>
     54   1.1   matt 
     55   1.1   matt #include <dev/pci/pcireg.h>
     56   1.1   matt #include <dev/pci/pcivar.h>
     57   1.1   matt #include <dev/pci/pciconf.h>
     58   1.1   matt #include <dev/marvell/gtreg.h>
     59   1.1   matt #include <dev/marvell/gtvar.h>
     60   1.1   matt #include <dev/marvell/gtintrreg.h>
     61   1.1   matt #include <dev/marvell/gtpcireg.h>
     62   1.1   matt #include <dev/marvell/gtpcivar.h>
     63   1.1   matt #include <dev/marvell/gtvar.h>
     64   1.1   matt 
     65   1.1   matt static int	gtpci_error_intr(void *);
     66   1.1   matt 
     67   1.5   matt static void	gtpci_bus_init(struct gtpci_chipset *);
     68   1.5   matt 
     69   1.1   matt static void	gtpci_bus_attach_hook(struct device *, struct device *,
     70   1.1   matt 		    struct pcibus_attach_args *);
     71   1.1   matt static int	gtpci_bus_maxdevs(pci_chipset_tag_t, int);
     72   1.1   matt 
     73   1.1   matt static const char *
     74   1.1   matt 		gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
     75   1.1   matt static const struct evcnt *
     76   1.1   matt 		gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
     77   1.1   matt static void	*gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
     78   1.1   matt 		    int, int (*)(void *), void *);
     79   1.1   matt static void	gtpci_intr_disestablish(pci_chipset_tag_t, void *);
     80   1.1   matt 
     81   1.1   matt #ifdef DEBUG
     82   1.1   matt int gtpci_debug = 0;
     83   1.1   matt #endif
     84   1.1   matt 
     85   1.1   matt struct gtpci_softc {
     86   1.1   matt 	struct device gtpci_dev;
     87   1.2   matt 	struct gtpci_chipset gtpci_gtpc;
     88   1.1   matt };
     89   1.1   matt 
     90   1.1   matt static int gtpci_cfprint(void *, const char *);
     91   1.1   matt static int gtpci_match(struct device *, struct cfdata *, void *);
     92   1.1   matt static void gtpci_attach(struct device *, struct device *, void *);
     93   1.1   matt 
     94   1.1   matt CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc),
     95   1.1   matt     gtpci_match, gtpci_attach, NULL, NULL);
     96   1.1   matt 
     97   1.1   matt extern struct cfdriver gtpci_cd;
     98   1.1   matt 
     99   1.1   matt const struct pci_chipset_functions gtpci_functions = {
    100   1.1   matt 	gtpci_bus_attach_hook,
    101   1.1   matt 	gtpci_bus_maxdevs,
    102   1.1   matt 	gtpci_md_bus_devorder,
    103   1.1   matt 
    104   1.1   matt 	gtpci_make_tag,
    105   1.1   matt 	gtpci_decompose_tag,
    106   1.1   matt 
    107   1.1   matt 	gtpci_conf_read,
    108   1.1   matt 	gtpci_conf_write,
    109   1.1   matt 	gtpci_md_conf_hook,
    110   1.1   matt 	gtpci_md_conf_interrupt,
    111   1.1   matt 
    112   1.1   matt 	gtpci_md_intr_map,
    113   1.1   matt 	gtpci_intr_string,
    114   1.1   matt 	gtpci_intr_evcnt,
    115   1.1   matt 	gtpci_intr_establish,
    116   1.1   matt 	gtpci_intr_disestablish
    117   1.1   matt };
    118   1.1   matt 
    119   1.6   matt static const int pci_irqs[2][3] = {
    120   1.6   matt     { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 },
    121   1.6   matt     { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 },
    122   1.6   matt };
    123   1.6   matt 
    124   1.6   matt static const struct pci_init {
    125   1.6   matt 	int bar_regno;
    126   1.6   matt 	u_int32_t bar_enable;
    127   1.6   matt  	bus_addr_t low_decode;
    128   1.6   matt 	bus_addr_t high_decode;
    129   1.6   matt 	bus_addr_t barsize;
    130   1.6   matt 	bus_addr_t accctl_high;
    131   1.6   matt 	bus_addr_t accctl_low;
    132   1.6   matt 	bus_addr_t accctl_top;
    133   1.6   matt } pci_initinfo[2][4] = {
    134   1.6   matt     	{
    135   1.6   matt 		{
    136   1.6   matt 			0x10,			PCI_BARE_SCS0En,
    137   1.6   matt 			GT_SCS0_Low_Decode,	GT_SCS0_High_Decode,
    138   1.6   matt 			PCI_SCS0_BAR_SIZE(0),
    139   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 0),
    140   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 0),
    141   1.6   matt 			PCI_ACCESS_CONTROL_TOP(0, 0),
    142   1.6   matt 		}, {
    143   1.6   matt 			0x14,			PCI_BARE_SCS1En,
    144   1.6   matt 			GT_SCS1_Low_Decode,	GT_SCS1_High_Decode,
    145   1.6   matt 			PCI_SCS1_BAR_SIZE(0),
    146   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 1),
    147   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 1),
    148   1.6   matt 			PCI_ACCESS_CONTROL_TOP(0, 1),
    149   1.6   matt 		}, {
    150   1.6   matt 			0x18,			PCI_BARE_SCS2En,
    151   1.6   matt 			GT_SCS2_Low_Decode,	GT_SCS2_High_Decode,
    152   1.6   matt 			PCI_SCS2_BAR_SIZE(0),
    153   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 2),
    154   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 2),
    155   1.6   matt 			PCI_ACCESS_CONTROL_TOP(0, 2),
    156   1.6   matt 		}, {
    157   1.6   matt 			0x1c,			PCI_BARE_SCS3En,
    158   1.6   matt 			GT_SCS3_Low_Decode,	GT_SCS3_High_Decode,
    159   1.6   matt 			PCI_SCS3_BAR_SIZE(0),
    160   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 3),
    161   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 3),
    162   1.6   matt 			PCI_ACCESS_CONTROL_TOP(0, 3),
    163   1.6   matt 		},
    164   1.6   matt 	}, {
    165   1.6   matt 		{
    166   1.6   matt 			0x10,			PCI_BARE_SCS0En,
    167   1.6   matt 			GT_SCS0_Low_Decode,	GT_SCS0_High_Decode,
    168   1.6   matt 			PCI_SCS0_BAR_SIZE(1),
    169   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 0),
    170   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 0),
    171   1.6   matt 			PCI_ACCESS_CONTROL_TOP(1, 0),
    172   1.6   matt 		}, {
    173   1.6   matt 			0x14,			PCI_BARE_SCS1En,
    174   1.6   matt 			GT_SCS1_Low_Decode,	GT_SCS1_High_Decode,
    175   1.6   matt 			PCI_SCS1_BAR_SIZE(1),
    176   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 1),
    177   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 1),
    178   1.6   matt 			PCI_ACCESS_CONTROL_TOP(1, 1),
    179   1.6   matt 		}, {
    180   1.6   matt 			0x18,			PCI_BARE_SCS2En,
    181   1.6   matt 			GT_SCS2_Low_Decode,	GT_SCS2_High_Decode,
    182   1.6   matt 			PCI_SCS2_BAR_SIZE(1),
    183   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 2),
    184   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 2),
    185   1.6   matt 			PCI_ACCESS_CONTROL_TOP(1, 2),
    186   1.6   matt 		}, {
    187   1.6   matt 			0x1c,			PCI_BARE_SCS3En,
    188   1.6   matt 			GT_SCS3_Low_Decode,	GT_SCS3_High_Decode,
    189   1.6   matt 			PCI_SCS3_BAR_SIZE(1),
    190   1.6   matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 3),
    191   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 3),
    192   1.6   matt 			PCI_ACCESS_CONTROL_TOP(1, 3),
    193   1.6   matt 		},
    194   1.6   matt 	}
    195   1.6   matt };
    196   1.6   matt 
    197   1.1   matt int
    198   1.1   matt gtpci_match(struct device *parent, struct cfdata *self, void *aux)
    199   1.1   matt {
    200   1.2   matt 	struct gt_softc * const gt = (struct gt_softc *) parent;
    201   1.2   matt 	struct gt_attach_args * const ga = aux;
    202   1.1   matt 
    203   1.2   matt 	return GT_PCIOK(gt, ga, &gtpci_cd);
    204   1.1   matt }
    205   1.1   matt 
    206   1.1   matt int
    207   1.1   matt gtpci_cfprint(void *aux, const char *pnp)
    208   1.1   matt {
    209   1.1   matt 	struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux;
    210   1.1   matt 
    211   1.1   matt 	if (pnp)
    212   1.2   matt 		aprint_normal("pci at %s", pnp);
    213   1.1   matt 
    214   1.2   matt 	aprint_normal(" bus %d", pba->pba_bus);
    215   1.1   matt 
    216   1.1   matt 	return (UNCONF);
    217   1.1   matt }
    218   1.1   matt 
    219   1.1   matt void
    220   1.1   matt gtpci_attach(struct device *parent, struct device *self, void *aux)
    221   1.1   matt {
    222   1.1   matt 	struct pcibus_attach_args pba;
    223   1.2   matt 	struct gt_attach_args * const ga = aux;
    224   1.2   matt 	struct gt_softc * const gt = (struct gt_softc *) parent;
    225   1.2   matt 	struct gtpci_softc * const gtp = (struct gtpci_softc *) self;
    226   1.2   matt 	struct gtpci_chipset * const gtpc = &gtp->gtpci_gtpc;
    227   1.2   matt 	struct pci_chipset * const pc = &gtpc->gtpc_pc;
    228   1.2   matt 	const int busno = ga->ga_unit;
    229   1.1   matt 	uint32_t data;
    230   1.1   matt 
    231   1.2   matt 	GT_PCIFOUND(gt, ga);
    232   1.1   matt 
    233   1.1   matt 	pc->pc_funcs = &gtpci_functions;
    234   1.1   matt 	pc->pc_parent = self;
    235   1.1   matt 
    236   1.2   matt 	gtpc->gtpc_busno = busno;
    237   1.2   matt 	gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno);
    238   1.2   matt 	gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno);
    239   1.2   matt 	gtpc->gtpc_syncreg = PCI_SYNC_REG(busno);
    240   1.2   matt 	gtpc->gtpc_gt_memt = ga->ga_memt;
    241   1.2   matt 	gtpc->gtpc_gt_memh = ga->ga_memh;
    242   1.1   matt 
    243   1.6   matt 	/*
    244   1.6   matt 	 * Let's find out where we are located.
    245   1.6   matt 	 */
    246   1.6   matt 	data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno));
    247   1.6   matt 	gtpc->gtpc_self = gtpci_make_tag(&gtpc->gtpc_pc,
    248   1.6   matt 		PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0);
    249   1.6   matt 
    250   1.6   matt 
    251   1.1   matt 	switch (busno) {
    252   1.1   matt 	case 0:
    253   1.2   matt 		gtpc->gtpc_io_bs = gt->gt_pci0_iot;
    254   1.2   matt 		gtpc->gtpc_mem_bs = gt->gt_pci0_memt;
    255   1.9    scw 		gtpc->gtpc_host = gt->gt_pci0_host;
    256   1.1   matt 		break;
    257   1.1   matt 	case 1:
    258   1.2   matt 		gtpc->gtpc_io_bs = gt->gt_pci1_iot;
    259   1.2   matt 		gtpc->gtpc_mem_bs = gt->gt_pci1_memt;
    260   1.9    scw 		gtpc->gtpc_host = gt->gt_pci1_host;
    261   1.1   matt 		break;
    262   1.1   matt 	default:
    263   1.1   matt 		break;
    264   1.1   matt 	}
    265   1.1   matt 
    266   1.2   matt 	/*
    267   1.2   matt 	 * If no bus_spaces exist, then it's been disabled.
    268   1.2   matt 	 */
    269   1.2   matt 	if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) {
    270   1.2   matt 		aprint_normal(": disabled\n");
    271   1.2   matt 		return;
    272   1.2   matt 	}
    273   1.2   matt 
    274   1.2   matt 	aprint_normal("\n");
    275   1.2   matt 
    276   1.6   matt 	/*
    277   1.6   matt 	 * clear any pre-existing error interrupt(s)
    278   1.6   matt 	 * clear latched pci error registers
    279   1.6   matt 	 * establish ISRs for PCI errors
    280   1.6   matt 	 * enable PCI error interrupts
    281   1.6   matt 	 */
    282   1.9    scw 	gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 0);
    283   1.6   matt 	gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0);
    284   1.6   matt 	(void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
    285   1.6   matt 	(void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
    286   1.6   matt 	(void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
    287   1.6   matt 	(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
    288   1.6   matt 	(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
    289   1.9    scw 	if (gtpc->gtpc_host) {
    290   1.9    scw 		intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL,
    291   1.9    scw 		    IPL_GTERR, gtpci_error_intr, pc);
    292   1.9    scw 		intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL,
    293   1.9    scw 		    IPL_GTERR, gtpci_error_intr, pc);
    294   1.9    scw 		intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL,
    295   1.9    scw 		    IPL_GTERR, gtpci_error_intr, pc);
    296   1.9    scw 		aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n",
    297   1.9    scw 		    pc->pc_parent->dv_xname, "pci", busno,
    298   1.9    scw 		    intr_string(pci_irqs[gtpc->gtpc_busno][0]),
    299   1.9    scw 		    intr_string(pci_irqs[gtpc->gtpc_busno][1]),
    300   1.9    scw 		    intr_string(pci_irqs[gtpc->gtpc_busno][2]));
    301   1.9    scw 		gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno),
    302   1.9    scw 		    PCI_SERRMSK_ALL_ERRS);
    303   1.9    scw 	}
    304   1.6   matt 
    305   1.6   matt 	/*
    306   1.6   matt 	 * Fill in the pci_bus_attach_args
    307   1.6   matt 	 */
    308   1.1   matt 	pba.pba_pc = pc;
    309   1.1   matt 	pba.pba_bus = 0;
    310   1.1   matt 	pba.pba_busname = "pci";
    311   1.2   matt 	pba.pba_iot = gtpc->gtpc_io_bs;
    312   1.2   matt 	pba.pba_memt = gtpc->gtpc_mem_bs;
    313   1.1   matt 	pba.pba_dmat = gt->gt_dmat;
    314   1.2   matt 	pba.pba_flags = 0;
    315   1.2   matt 	if (pba.pba_iot != NULL)
    316   1.2   matt 		pba.pba_flags |= PCI_FLAGS_IO_ENABLED;
    317   1.2   matt 	if (pba.pba_memt != NULL)
    318   1.2   matt 		pba.pba_flags |= PCI_FLAGS_MEM_ENABLED;
    319   1.1   matt 
    320   1.2   matt 	data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
    321   1.1   matt 	if (data & PCI_CMD_MRdMul)
    322   1.1   matt 		pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
    323   1.1   matt 	if (data & PCI_CMD_MRdLine)
    324   1.1   matt 		pba.pba_flags |= PCI_FLAGS_MRL_OKAY;
    325   1.1   matt 	pba.pba_flags |= PCI_FLAGS_MWI_OKAY;
    326   1.1   matt 
    327   1.1   matt 	gt_watchdog_service();
    328   1.6   matt 	/*
    329   1.6   matt 	 * Configure the pci bus.
    330   1.6   matt 	 */
    331   1.1   matt 	config_found(self, &pba, gtpci_cfprint);
    332   1.1   matt 
    333   1.1   matt 	gt_watchdog_service();
    334   1.1   matt 
    335   1.1   matt }
    336   1.1   matt 
    337   1.1   matt void
    338   1.5   matt gtpci_bus_init(struct gtpci_chipset *gtpc)
    339   1.5   matt {
    340   1.6   matt 	const struct pci_init *pi;
    341   1.6   matt 	uint32_t data, datal, datah;
    342   1.5   matt 	pcireg_t pcidata;
    343   1.6   matt 	int i;
    344   1.5   matt 
    345   1.5   matt 	/*
    346   1.5   matt 	 * disable all BARs to start.
    347   1.5   matt 	 */
    348   1.5   matt 	gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
    349   1.5   matt 	    0xffffffff);
    350   1.5   matt 
    351   1.8    scw #ifndef GT_PCI0_EXT_ARBITER
    352   1.8    scw #define	GT_PCI0_EXT_ARBITER 0
    353   1.8    scw #endif
    354   1.8    scw #ifndef GT_PCI1_EXT_ARBITER
    355   1.8    scw #define	GT_PCI1_EXT_ARBITER 0
    356   1.8    scw #endif
    357   1.8    scw 
    358   1.9    scw 	if (gtpc->gtpc_host &&
    359   1.9    scw 	    ((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) ||
    360   1.9    scw 	     (!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) {
    361   1.8    scw 		/*
    362   1.8    scw 		 * Enable internal arbiter
    363   1.8    scw 		 */
    364   1.8    scw 		data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno));
    365   1.8    scw 		data |= PCI_ARBCTL_EN;
    366   1.8    scw 		gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data);
    367   1.8    scw 	} else {
    368   1.8    scw 		/*
    369   1.8    scw 		 * Make sure the internal arbiter is disabled
    370   1.8    scw 		 */
    371   1.8    scw 		gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0);
    372   1.8    scw 	}
    373   1.5   matt 
    374   1.5   matt 	/*
    375   1.5   matt 	 * Make the GT reflects reality.
    376   1.6   matt 	 * We always enable internal memory.
    377   1.5   matt 	 */
    378   1.9    scw 	if (gtpc->gtpc_host) {
    379   1.9    scw 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    380   1.9    scw 		    0x20) & 0xfff;
    381   1.9    scw 		gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20,
    382   1.9    scw 		    GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) |
    383   1.9    scw 		    pcidata);
    384   1.9    scw 	}
    385   1.6   matt 	data = PCI_BARE_IntMemEn;
    386   1.6   matt 
    387   1.7   matt 	for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++)
    388   1.6   matt 		gtpci_write(gtpc, pi->barsize, 0);
    389   1.5   matt 
    390   1.9    scw 	if (gtpc->gtpc_host) {
    391   1.9    scw 		/*
    392   1.9    scw 		 * Enable bus master access (needed for config access).
    393   1.9    scw 		 */
    394   1.9    scw 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    395   1.9    scw 		    PCI_COMMAND_STATUS_REG);
    396   1.9    scw 		pcidata |= PCI_COMMAND_MASTER_ENABLE;
    397   1.9    scw 		gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    398   1.9    scw 		    PCI_COMMAND_STATUS_REG, pcidata);
    399   1.9    scw 	}
    400   1.5   matt 
    401   1.5   matt 	/*
    402   1.5   matt 	 * Map each SCS BAR to correspond to each SDRAM decode register.
    403   1.5   matt 	 */
    404   1.7   matt 	for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) {
    405   1.6   matt 		datal = gtpci_read(gtpc, pi->low_decode);
    406   1.6   matt 		datah = gtpci_read(gtpc, pi->high_decode);
    407   1.6   matt 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    408   1.6   matt 		    pi->bar_regno);
    409   1.6   matt 		gtpci_write(gtpc, pi->accctl_high, 0);
    410   1.6   matt 		if (datal < datah) {
    411   1.6   matt 			datal &= 0xfff;
    412   1.6   matt 			pcidata &= 0xfff;
    413   1.6   matt 			pcidata |= datal << 20;
    414   1.6   matt 			data |= pi->bar_enable;
    415   1.6   matt 			datah -= datal;
    416   1.6   matt 			datal |= PCI_ACCCTLBASEL_PrefetchEn|
    417   1.6   matt 			    PCI_ACCCTLBASEL_RdPrefetch|
    418   1.6   matt 			    PCI_ACCCTLBASEL_RdLinePrefetch|
    419   1.6   matt 			    PCI_ACCCTLBASEL_RdMulPrefetch|
    420   1.6   matt 			    PCI_ACCCTLBASEL_WBurst_8_QW|
    421   1.6   matt 			    PCI_ACCCTLBASEL_PCISwap_NoSwap;
    422   1.6   matt 			gtpci_write(gtpc, pi->accctl_low, datal);
    423   1.6   matt 		} else {
    424   1.6   matt 			pcidata &= 0xfff;
    425   1.6   matt 			datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap;
    426   1.6   matt 			datah = 0;
    427   1.6   matt 		}
    428   1.6   matt 		gtpci_write(gtpc, pi->barsize,
    429   1.6   matt 		    datah ? ((datah << 20) | 0xff000) : 0);
    430   1.9    scw 		if (gtpc->gtpc_host) {
    431   1.9    scw 			gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    432   1.9    scw 			    pi->bar_regno, pcidata);
    433   1.9    scw 		}
    434   1.6   matt 		gtpci_write(gtpc, pi->accctl_low, datal);
    435   1.6   matt 		gtpci_write(gtpc, pi->accctl_top, datah);
    436   1.5   matt 	}
    437   1.5   matt 
    438   1.5   matt 	/*
    439   1.5   matt 	 * Now re-enable those BARs that are real.
    440   1.5   matt 	 */
    441   1.5   matt 	gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
    442   1.6   matt 	    ~data);
    443   1.5   matt 
    444   1.9    scw 	if (gtpc->gtpc_host) {
    445   1.9    scw 		/*
    446   1.9    scw 		 * Enable I/O and memory (bus master is already enabled) access.
    447   1.9    scw 		 */
    448   1.9    scw 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    449   1.9    scw 		    PCI_COMMAND_STATUS_REG);
    450   1.9    scw 		pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
    451   1.9    scw 		gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    452   1.9    scw 		    PCI_COMMAND_STATUS_REG, pcidata);
    453   1.9    scw 	}
    454   1.5   matt }
    455   1.5   matt 
    456   1.5   matt void
    457   1.1   matt gtpci_bus_attach_hook(struct device *parent, struct device *self,
    458   1.1   matt 	struct pcibus_attach_args *pba)
    459   1.1   matt {
    460   1.5   matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc;
    461   1.5   matt 	uint32_t data;
    462   1.6   matt #if defined(DEBUG)
    463   1.1   matt 	pcitag_t tag;
    464   1.6   matt 	int bus, dev;
    465   1.6   matt 	int i;
    466   1.5   matt #endif
    467   1.1   matt 
    468   1.5   matt 	if (gtpc->gtpc_pc.pc_parent != parent)
    469   1.1   matt 		return;
    470   1.1   matt 
    471   1.2   matt 	data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
    472   1.2   matt 	aprint_normal(": id %d%s%s%s%s%s%s%s%s",
    473   1.1   matt 		PCI_MODE_PciID_GET(data),
    474   1.1   matt 		(data & PCI_MODE_Pci64) ? ", 64bit" : "",
    475   1.1   matt 		(data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "",
    476   1.1   matt 		(data & PCI_MODE_VPD) ? ", VPD" : "",
    477   1.1   matt 		(data & PCI_MODE_MSI) ? ", MSI" : "",
    478   1.1   matt 		(data & PCI_MODE_PMG) ? ", PMG" : "",
    479   1.1   matt 		(data & PCI_MODE_HotSwap) ? ", HotSwap" : "",
    480   1.1   matt 		(data & PCI_MODE_BIST) ? ", BIST" : "",
    481   1.1   matt 		(data & PCI_MODE_PRst) ? "" : ", PRst");
    482   1.1   matt 
    483   1.3   matt #if 0
    484   1.1   matt 	while ((data & PCI_MODE_PRst) == 0) {
    485   1.3   matt 		DELAY(10);
    486   1.2   matt 		data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
    487   1.3   matt 		aprint_normal(".");
    488   1.1   matt 	}
    489   1.3   matt #endif
    490   1.1   matt 
    491   1.5   matt 	gtpci_bus_init(gtpc);
    492   1.5   matt 	gtpci_bus_configure(gtpc);
    493   1.6   matt 
    494   1.6   matt 	data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
    495   1.6   matt 	if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) {
    496   1.6   matt 		aprint_normal("\n%s: ", self->dv_xname);
    497   1.6   matt 		if (data & PCI_CMD_MSwapEn) {
    498   1.6   matt 			switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) {
    499   1.6   matt 			case PCI_CMD_MWordSwap:
    500   1.6   matt 				aprint_normal(" mswap=w"); break;
    501   1.6   matt 			case PCI_CMD_MByteSwap:
    502   1.6   matt 				aprint_normal(" mswap=b"); break;
    503   1.6   matt 			case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap:
    504   1.6   matt 				aprint_normal(" mswap=b+w"); break;
    505   1.6   matt 			case 0:
    506   1.6   matt 				aprint_normal(" mswap=none"); break;
    507   1.6   matt 			}
    508   1.6   matt 		}
    509   1.6   matt 
    510   1.6   matt 		if (data & PCI_CMD_SSwapEn) {
    511   1.6   matt 			switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) {
    512   1.6   matt 			case PCI_CMD_SWordSwap:
    513   1.6   matt 				aprint_normal(" sswap=w"); break;
    514   1.6   matt 			case PCI_CMD_SByteSwap:
    515   1.6   matt 				aprint_normal(" sswap=b"); break;
    516   1.6   matt 			case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap:
    517   1.6   matt 				aprint_normal(" sswap=b+w"); break;
    518   1.6   matt 			case 0:
    519   1.6   matt 				aprint_normal(" sswap=none"); break;
    520   1.6   matt 			}
    521   1.6   matt 		}
    522   1.6   matt 	}
    523   1.6   matt 
    524   1.6   matt #if defined(DEBUG)
    525   1.6   matt 	if (gtpci_debug == 0)
    526   1.6   matt 		return;
    527   1.1   matt 
    528   1.2   matt 	data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno));
    529   1.2   matt 	aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data);
    530   1.1   matt 
    531   1.2   matt 	aprint_normal("\n%s: 0:0:0\n", self->dv_xname);
    532   1.2   matt 	aprint_normal("   %sSCS0=%#010x",
    533   1.1   matt 		(data & 1) ? "-" : "+",
    534   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x10));
    535   1.2   matt 	aprint_normal("/%#010x", gtpci_read(gtpc,
    536   1.6   matt 		PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno)));
    537   1.2   matt 	aprint_normal("  remap %#010x\n",
    538   1.2   matt 		gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    539   1.1   matt 
    540   1.2   matt 	aprint_normal("   %sSCS1=%#010x",
    541   1.1   matt 		(data & 2) ? "-" : "+",
    542   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x14));
    543   1.2   matt 	aprint_normal("/%#010x",
    544   1.6   matt 		gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno)));
    545   1.2   matt 	aprint_normal("  remap %#010x\n",
    546   1.2   matt 		gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    547   1.1   matt 
    548   1.2   matt 	aprint_normal("   %sSCS2=%#010x",
    549   1.1   matt 		(data & 4) ? "-" : "+",
    550   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x18));
    551   1.2   matt 	aprint_normal("/%#010x",
    552   1.6   matt 		gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno)));
    553   1.2   matt 	aprint_normal("  remap %#010x\n",
    554   1.2   matt 		gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    555   1.1   matt 
    556   1.2   matt 	aprint_normal("   %sSCS3=%#010x",
    557   1.1   matt 		(data & 8) ? "-" : "+",
    558   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x1c));
    559   1.2   matt 	aprint_normal("/%#010x",
    560   1.6   matt 		gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno)));
    561   1.2   matt 	aprint_normal("  remap %#010x\n",
    562   1.2   matt 		gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    563   1.1   matt 
    564   1.2   matt 	aprint_normal("   %sIMem=%#010x",
    565   1.1   matt 		(data & PCI_BARE_IntMemEn) ? "-" : "+",
    566   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20));
    567   1.2   matt 	aprint_normal("\n");
    568   1.2   matt 	aprint_normal("    %sIIO=%#010x",
    569   1.1   matt 		(data & PCI_BARE_IntIOEn) ? "-" : "+",
    570   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x24));
    571   1.2   matt 	aprint_normal("\n");
    572   1.6   matt 
    573   1.6   matt 	gtpci_decompose_tag(&gtpc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL);
    574   1.6   matt 	tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, dev, 1);
    575   1.2   matt 	aprint_normal("    %sCS0=%#010x",
    576   1.1   matt 		(data & PCI_BARE_CS0En) ? "-" : "+",
    577   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
    578   1.2   matt 	aprint_normal("/%#010x",
    579   1.6   matt 		gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno)));
    580   1.2   matt 	aprint_normal("  remap %#010x\n",
    581   1.2   matt 		gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    582   1.1   matt 
    583   1.2   matt 	aprint_normal("    %sCS1=%#010x",
    584   1.1   matt 		(data & PCI_BARE_CS1En) ? "-" : "+",
    585   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
    586   1.2   matt 	aprint_normal("/%#010x",
    587   1.6   matt 		gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno)));
    588   1.2   matt 	aprint_normal("  remap %#010x\n",
    589   1.2   matt 		gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    590   1.1   matt 
    591   1.2   matt 	aprint_normal("    %sCS2=%#010x",
    592   1.1   matt 		(data & PCI_BARE_CS2En) ? "-" : "+",
    593   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
    594   1.2   matt 	aprint_normal("/%#010x",
    595   1.6   matt 		gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno)));
    596   1.2   matt 	aprint_normal("  remap %#010x\n",
    597   1.2   matt 		gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    598   1.1   matt 
    599   1.2   matt 	aprint_normal("    %sCS3=%#010x",
    600   1.1   matt 		(data & PCI_BARE_CS3En) ? "-" : "+",
    601   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
    602   1.2   matt 	aprint_normal("/%#010x",
    603   1.6   matt 		gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno)));
    604   1.2   matt 	aprint_normal("  remap %#010x\n",
    605   1.2   matt 		gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    606   1.1   matt 
    607   1.2   matt 	aprint_normal(" %sBootCS=%#010x",
    608   1.1   matt 		(data & PCI_BARE_BootCSEn) ? "-" : "+",
    609   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x20));
    610   1.2   matt 	aprint_normal("/%#010x",
    611   1.6   matt 		gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno)));
    612   1.2   matt 	aprint_normal("  remap %#010x\n",
    613   1.2   matt 		gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno)));
    614   1.1   matt 
    615   1.6   matt 	tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, tag, 2);
    616   1.2   matt 	aprint_normal("  %sP2PM0=%#010x",
    617   1.1   matt 		(data & PCI_BARE_P2PMem0En) ? "-" : "+",
    618   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
    619   1.2   matt 	aprint_normal("/%#010x",
    620   1.6   matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno)));
    621   1.2   matt 	aprint_normal("  remap %#010x.%#010x\n",
    622   1.2   matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
    623   1.2   matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
    624   1.1   matt 
    625   1.2   matt 	aprint_normal("  %sP2PM1=%#010x",
    626   1.1   matt 		(data & PCI_BARE_P2PMem1En) ? "-" : "+",
    627   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
    628   1.2   matt 	aprint_normal("/%#010x",
    629   1.6   matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno)));
    630   1.2   matt 	aprint_normal("  remap %#010x.%#010x\n",
    631   1.2   matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
    632   1.2   matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
    633   1.1   matt 
    634   1.2   matt 	aprint_normal("  %sP2PIO=%#010x",
    635   1.1   matt 		(data & PCI_BARE_P2PIOEn) ? "-" : "+",
    636   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
    637   1.2   matt 	aprint_normal("/%#010x",
    638   1.6   matt 		gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno)));
    639   1.2   matt 	aprint_normal("  remap %#010x\n",
    640   1.2   matt 		gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    641   1.1   matt 
    642   1.2   matt 	aprint_normal("    %sCPU=%#010x",
    643   1.1   matt 		(data & PCI_BARE_CPUEn) ? "-" : "+",
    644   1.6   matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
    645   1.2   matt 	aprint_normal("/%#010x",
    646   1.6   matt 		gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno)));
    647   1.2   matt 	aprint_normal("  remap %#010x\n",
    648   1.2   matt 		gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    649   1.1   matt 
    650   1.1   matt 	for (i = 0; i < 8; i++) {
    651   1.2   matt 		aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i);
    652   1.6   matt 		data = gtpci_read(gtpc,
    653   1.6   matt 		    PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i));
    654   1.6   matt 		if (data)
    655   1.6   matt 			aprint_normal("base=0x%08x.", data);
    656   1.6   matt 		else
    657   1.6   matt 			aprint_normal("base=0x");
    658   1.6   matt 		data = gtpci_read(gtpc,
    659   1.6   matt 			PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i));
    660   1.6   matt 		printf("%08x cfg=0x%08x", data << 20, data & ~0xfff);
    661   1.6   matt 		aprint_normal(" top=0x%03x00000",
    662   1.6   matt 		    gtpci_read(gtpc,
    663   1.6   matt 			PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i)));
    664   1.1   matt 	}
    665   1.1   matt #endif
    666   1.1   matt }
    667   1.1   matt 
    668   1.1   matt static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings;
    669   1.1   matt 
    670   1.1   matt int
    671   1.1   matt gtpci_error_intr(void *arg)
    672   1.1   matt {
    673   1.1   matt 	pci_chipset_tag_t pc = arg;
    674   1.2   matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    675   1.1   matt 	uint32_t cause, mask, errmask;
    676   1.1   matt 	u_int32_t alo, ahi, dlo, dhi, cmd;
    677   1.1   matt 	int i;
    678   1.1   matt 
    679   1.2   matt 	cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno));
    680   1.2   matt 	errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno));
    681   1.6   matt 	cause &= errmask | 0xf8000000;
    682   1.2   matt 	gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause);
    683   1.1   matt 	printf("%s: pci%d error: cause=%#x mask=%#x",
    684   1.2   matt 		pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask);
    685   1.6   matt 	if ((cause & 0xf8000000) == 0) {
    686   1.1   matt 		printf(" ?\n");
    687   1.1   matt 		return 0;
    688   1.1   matt 	}
    689   1.1   matt 
    690   1.1   matt 	for (i = 0, mask = 1; i <= 26; i++, mask += mask)
    691   1.1   matt 		if (mask & cause)
    692   1.1   matt 			printf(" %s", gtpci_error_strings[i]);
    693   1.1   matt 
    694   1.1   matt 	/*
    695   1.1   matt 	 * "no new data is latched until the PCI Error Low Address
    696   1.1   matt 	 * register is read.  This means that PCI Error Low Address
    697   1.1   matt 	 * register must be the last register read by the interrupt
    698   1.1   matt 	 * handler."
    699   1.1   matt 	 */
    700   1.2   matt 	dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
    701   1.2   matt 	dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
    702   1.2   matt 	cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
    703   1.2   matt 	ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
    704   1.2   matt 	alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
    705   1.6   matt 	printf("\n%s: pci%d error: %s cmd=%#x",
    706   1.2   matt 		pc->pc_parent->dv_xname, gtpc->gtpc_busno,
    707   1.6   matt 		gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd);
    708   1.6   matt 	if (dhi == 0)
    709   1.6   matt 		printf(" data=%08x", dlo);
    710   1.6   matt 	else
    711   1.6   matt 		printf(" data=%08x.%08x", dhi, dlo);
    712   1.6   matt 	if (ahi == 0)
    713   1.6   matt 		printf(" address=%08x\n", alo);
    714   1.6   matt 	else
    715   1.6   matt 		printf(" address=%08x.%08x\n", ahi, alo);
    716   1.1   matt 
    717   1.1   matt #if defined(DEBUG) && defined(DDB)
    718   1.6   matt 	if (gtpci_debug > 1)
    719   1.1   matt 		Debugger();
    720   1.1   matt #endif
    721   1.1   matt 	return 1;
    722   1.1   matt }
    723   1.1   matt 
    724   1.1   matt 
    725   1.1   matt #if 0
    726   1.1   matt void
    727   1.1   matt gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs,
    728   1.1   matt 	struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi)
    729   1.1   matt {
    730   1.1   matt 	/* See how I/O space is configured.  Read the base and top
    731   1.1   matt 	 * registers.
    732   1.1   matt 	 */
    733   1.1   matt 	paddr_t pbasel, pbaseh;
    734   1.1   matt 	uint32_t datal, datah;
    735   1.1   matt 
    736   1.2   matt 	datal = gtpci_read(gtpc, lo);
    737   1.2   matt 	datah = gtpci_read(gtpc, hi);
    738   1.1   matt 	pbasel = GT_LowAddr_GET(datal);
    739   1.1   matt 	pbaseh = GT_HighAddr_GET(datah);
    740   1.1   matt 	/*
    741   1.1   matt 	 * If the start is greater than the end, ignore the region.
    742   1.1   matt  	 */
    743   1.1   matt 	if (pbaseh < pbasel)
    744   1.1   matt 		return;
    745   1.1   matt 	if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase
    746   1.1   matt 	    && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) {
    747   1.1   matt 		bs->bs_regions[bs->bs_nregion].br_vbase =
    748   1.1   matt 			gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask);
    749   1.1   matt 	}
    750   1.1   matt 	bs->bs_regions[bs->bs_nregion].br_pbase = pbasel;
    751   1.1   matt 	if (bs->bs_flags & _BUS_SPACE_RELATIVE) {
    752   1.1   matt 		bs->bs_regions[bs->bs_nregion].br_start = 0;
    753   1.1   matt 		bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel;
    754   1.1   matt 	} else {
    755   1.1   matt 		bs->bs_regions[bs->bs_nregion].br_start = pbasel;
    756   1.1   matt 		bs->bs_regions[bs->bs_nregion].br_end = pbaseh;
    757   1.1   matt 	}
    758   1.1   matt 	bs->bs_nregion++;
    759   1.1   matt }
    760   1.1   matt #endif
    761   1.1   matt 
    762   1.1   matt /*
    763   1.1   matt  * Internal functions.
    764   1.1   matt  */
    765   1.1   matt int
    766   1.1   matt gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
    767   1.1   matt {
    768   1.1   matt 	return 32;
    769   1.1   matt }
    770   1.1   matt 
    771   1.1   matt pcitag_t
    772   1.1   matt gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno)
    773   1.1   matt {
    774   1.1   matt 	return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0);
    775   1.1   matt }
    776   1.1   matt 
    777   1.1   matt void
    778   1.1   matt gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
    779   1.1   matt 		    int *bp, int *dp, int *fp)
    780   1.1   matt {
    781   1.1   matt 	if (bp != NULL)
    782   1.1   matt 		*bp = PCI_CFG_GET_BUSNO(tag);
    783   1.1   matt 	if (dp != NULL)
    784   1.1   matt 		*dp = PCI_CFG_GET_DEVNO(tag);
    785   1.1   matt 	if (fp != NULL)
    786   1.1   matt 		*fp = PCI_CFG_GET_FUNCNO(tag);
    787   1.1   matt }
    788   1.1   matt 
    789   1.1   matt pcireg_t
    790   1.1   matt gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno)
    791   1.1   matt {
    792   1.2   matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    793   1.1   matt #ifdef DIAGNOSTIC
    794   1.6   matt 	if ((regno & 3) || (regno & ~0xff))
    795   1.1   matt 		panic("gtpci_conf_read: bad regno %#x\n", regno);
    796   1.1   matt #endif
    797   1.2   matt 	gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
    798   1.2   matt 	return gtpci_read(gtpc, gtpc->gtpc_cfgdata);
    799   1.1   matt }
    800   1.1   matt 
    801   1.1   matt void
    802   1.1   matt gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data)
    803   1.1   matt {
    804   1.2   matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    805   1.1   matt #ifdef DIAGNOSTIC
    806   1.6   matt 	if ((regno & 3) || (regno & ~0xff))
    807   1.1   matt 		panic("gtpci_conf_write: bad regno %#x\n", regno);
    808   1.1   matt #endif
    809   1.2   matt 	gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
    810   1.2   matt 	gtpci_write(gtpc, gtpc->gtpc_cfgdata, data);
    811   1.1   matt }
    812   1.1   matt 
    813   1.1   matt const char *
    814   1.1   matt gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih)
    815   1.1   matt {
    816   1.1   matt 	return intr_string(pih);
    817   1.1   matt }
    818   1.1   matt 
    819   1.1   matt const struct evcnt *
    820   1.1   matt gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih)
    821   1.1   matt {
    822   1.1   matt 	return intr_evcnt(pih);
    823   1.1   matt }
    824   1.1   matt 
    825   1.1   matt void *
    826   1.1   matt gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih,
    827   1.1   matt     int ipl, int (*handler)(void *), void *arg)
    828   1.1   matt {
    829   1.1   matt 	return intr_establish(pih, IST_LEVEL, ipl, handler, arg);
    830   1.1   matt }
    831   1.1   matt 
    832   1.1   matt void
    833   1.1   matt gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
    834   1.1   matt {
    835   1.1   matt 	intr_disestablish(cookie);
    836   1.1   matt }
    837