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gtpci.c revision 1.6
      1  1.6  matt /*	$NetBSD: gtpci.c,v 1.6 2003/04/01 19:11:44 matt Exp $	*/
      2  1.1  matt 
      3  1.1  matt /*
      4  1.1  matt  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
      5  1.1  matt  * All rights reserved.
      6  1.1  matt  *
      7  1.1  matt  * Redistribution and use in source and binary forms, with or without
      8  1.1  matt  * modification, are permitted provided that the following conditions
      9  1.1  matt  * are met:
     10  1.1  matt  * 1. Redistributions of source code must retain the above copyright
     11  1.1  matt  *    notice, this list of conditions and the following disclaimer.
     12  1.1  matt  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  matt  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  matt  *    documentation and/or other materials provided with the distribution.
     15  1.1  matt  * 3. All advertising materials mentioning features or use of this software
     16  1.1  matt  *    must display the following acknowledgement:
     17  1.1  matt  *      This product includes software developed for the NetBSD Project by
     18  1.1  matt  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
     19  1.1  matt  * 4. The name of Allegro Networks, Inc. may not be used to endorse
     20  1.1  matt  *    or promote products derived from this software without specific prior
     21  1.1  matt  *    written permission.
     22  1.1  matt  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
     23  1.1  matt  *    or promote products derived from this software without specific prior
     24  1.1  matt  *    written permission.
     25  1.1  matt  *
     26  1.1  matt  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
     27  1.1  matt  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     28  1.1  matt  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
     29  1.1  matt  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     30  1.1  matt  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
     31  1.1  matt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32  1.1  matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33  1.1  matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34  1.1  matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35  1.1  matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36  1.1  matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37  1.1  matt  * POSSIBILITY OF SUCH DAMAGE.
     38  1.1  matt  */
     39  1.1  matt 
     40  1.1  matt #include "opt_marvell.h"
     41  1.1  matt #include <sys/param.h>
     42  1.1  matt #include <sys/device.h>
     43  1.1  matt #include <sys/extent.h>
     44  1.1  matt #include <sys/malloc.h>
     45  1.1  matt #include <lib/libkern/libkern.h>
     46  1.1  matt 
     47  1.1  matt #define _BUS_SPACE_PRIVATE
     48  1.1  matt #define _BUS_DMA_PRIVATE
     49  1.1  matt #include <machine/bus.h>
     50  1.1  matt #include <machine/intr.h>
     51  1.1  matt 
     52  1.1  matt #include <dev/pci/pcireg.h>
     53  1.1  matt #include <dev/pci/pcivar.h>
     54  1.1  matt #include <dev/pci/pciconf.h>
     55  1.1  matt #include <dev/marvell/gtreg.h>
     56  1.1  matt #include <dev/marvell/gtvar.h>
     57  1.1  matt #include <dev/marvell/gtintrreg.h>
     58  1.1  matt #include <dev/marvell/gtpcireg.h>
     59  1.1  matt #include <dev/marvell/gtpcivar.h>
     60  1.1  matt #include <dev/marvell/gtvar.h>
     61  1.1  matt 
     62  1.6  matt #define DEBUG
     63  1.6  matt 
     64  1.1  matt static int	gtpci_error_intr(void *);
     65  1.1  matt 
     66  1.5  matt static void	gtpci_bus_init(struct gtpci_chipset *);
     67  1.5  matt 
     68  1.1  matt static void	gtpci_bus_attach_hook(struct device *, struct device *,
     69  1.1  matt 		    struct pcibus_attach_args *);
     70  1.1  matt static int	gtpci_bus_maxdevs(pci_chipset_tag_t, int);
     71  1.1  matt 
     72  1.1  matt static const char *
     73  1.1  matt 		gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
     74  1.1  matt static const struct evcnt *
     75  1.1  matt 		gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
     76  1.1  matt static void	*gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
     77  1.1  matt 		    int, int (*)(void *), void *);
     78  1.1  matt static void	gtpci_intr_disestablish(pci_chipset_tag_t, void *);
     79  1.1  matt 
     80  1.1  matt #ifdef DEBUG
     81  1.1  matt int gtpci_debug = 0;
     82  1.1  matt #endif
     83  1.1  matt 
     84  1.1  matt struct gtpci_softc {
     85  1.1  matt 	struct device gtpci_dev;
     86  1.2  matt 	struct gtpci_chipset gtpci_gtpc;
     87  1.1  matt };
     88  1.1  matt 
     89  1.1  matt static int gtpci_cfprint(void *, const char *);
     90  1.1  matt static int gtpci_match(struct device *, struct cfdata *, void *);
     91  1.1  matt static void gtpci_attach(struct device *, struct device *, void *);
     92  1.1  matt 
     93  1.1  matt CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc),
     94  1.1  matt     gtpci_match, gtpci_attach, NULL, NULL);
     95  1.1  matt 
     96  1.1  matt extern struct cfdriver gtpci_cd;
     97  1.1  matt 
     98  1.1  matt const struct pci_chipset_functions gtpci_functions = {
     99  1.1  matt 	gtpci_bus_attach_hook,
    100  1.1  matt 	gtpci_bus_maxdevs,
    101  1.1  matt 	gtpci_md_bus_devorder,
    102  1.1  matt 
    103  1.1  matt 	gtpci_make_tag,
    104  1.1  matt 	gtpci_decompose_tag,
    105  1.1  matt 
    106  1.1  matt 	gtpci_conf_read,
    107  1.1  matt 	gtpci_conf_write,
    108  1.1  matt 	gtpci_md_conf_hook,
    109  1.1  matt 	gtpci_md_conf_interrupt,
    110  1.1  matt 
    111  1.1  matt 	gtpci_md_intr_map,
    112  1.1  matt 	gtpci_intr_string,
    113  1.1  matt 	gtpci_intr_evcnt,
    114  1.1  matt 	gtpci_intr_establish,
    115  1.1  matt 	gtpci_intr_disestablish
    116  1.1  matt };
    117  1.1  matt 
    118  1.6  matt static const int pci_irqs[2][3] = {
    119  1.6  matt     { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 },
    120  1.6  matt     { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 },
    121  1.6  matt };
    122  1.6  matt 
    123  1.6  matt static const struct pci_init {
    124  1.6  matt 	int bar_regno;
    125  1.6  matt 	u_int32_t bar_enable;
    126  1.6  matt  	bus_addr_t low_decode;
    127  1.6  matt 	bus_addr_t high_decode;
    128  1.6  matt 	bus_addr_t barsize;
    129  1.6  matt 	bus_addr_t accctl_high;
    130  1.6  matt 	bus_addr_t accctl_low;
    131  1.6  matt 	bus_addr_t accctl_top;
    132  1.6  matt } pci_initinfo[2][4] = {
    133  1.6  matt     	{
    134  1.6  matt 		{
    135  1.6  matt 			0x10,			PCI_BARE_SCS0En,
    136  1.6  matt 			GT_SCS0_Low_Decode,	GT_SCS0_High_Decode,
    137  1.6  matt 			PCI_SCS0_BAR_SIZE(0),
    138  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 0),
    139  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 0),
    140  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 0),
    141  1.6  matt 		}, {
    142  1.6  matt 			0x14,			PCI_BARE_SCS1En,
    143  1.6  matt 			GT_SCS1_Low_Decode,	GT_SCS1_High_Decode,
    144  1.6  matt 			PCI_SCS1_BAR_SIZE(0),
    145  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 1),
    146  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 1),
    147  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 1),
    148  1.6  matt 		}, {
    149  1.6  matt 			0x18,			PCI_BARE_SCS2En,
    150  1.6  matt 			GT_SCS2_Low_Decode,	GT_SCS2_High_Decode,
    151  1.6  matt 			PCI_SCS2_BAR_SIZE(0),
    152  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 2),
    153  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 2),
    154  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 2),
    155  1.6  matt 		}, {
    156  1.6  matt 			0x1c,			PCI_BARE_SCS3En,
    157  1.6  matt 			GT_SCS3_Low_Decode,	GT_SCS3_High_Decode,
    158  1.6  matt 			PCI_SCS3_BAR_SIZE(0),
    159  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 3),
    160  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 3),
    161  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 3),
    162  1.6  matt 		},
    163  1.6  matt 	}, {
    164  1.6  matt 		{
    165  1.6  matt 			0x10,			PCI_BARE_SCS0En,
    166  1.6  matt 			GT_SCS0_Low_Decode,	GT_SCS0_High_Decode,
    167  1.6  matt 			PCI_SCS0_BAR_SIZE(1),
    168  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 0),
    169  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 0),
    170  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 0),
    171  1.6  matt 		}, {
    172  1.6  matt 			0x14,			PCI_BARE_SCS1En,
    173  1.6  matt 			GT_SCS1_Low_Decode,	GT_SCS1_High_Decode,
    174  1.6  matt 			PCI_SCS1_BAR_SIZE(1),
    175  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 1),
    176  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 1),
    177  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 1),
    178  1.6  matt 		}, {
    179  1.6  matt 			0x18,			PCI_BARE_SCS2En,
    180  1.6  matt 			GT_SCS2_Low_Decode,	GT_SCS2_High_Decode,
    181  1.6  matt 			PCI_SCS2_BAR_SIZE(1),
    182  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 2),
    183  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 2),
    184  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 2),
    185  1.6  matt 		}, {
    186  1.6  matt 			0x1c,			PCI_BARE_SCS3En,
    187  1.6  matt 			GT_SCS3_Low_Decode,	GT_SCS3_High_Decode,
    188  1.6  matt 			PCI_SCS3_BAR_SIZE(1),
    189  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 3),
    190  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 3),
    191  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 3),
    192  1.6  matt 		},
    193  1.6  matt 	}
    194  1.6  matt };
    195  1.6  matt 
    196  1.1  matt int
    197  1.1  matt gtpci_match(struct device *parent, struct cfdata *self, void *aux)
    198  1.1  matt {
    199  1.2  matt 	struct gt_softc * const gt = (struct gt_softc *) parent;
    200  1.2  matt 	struct gt_attach_args * const ga = aux;
    201  1.1  matt 
    202  1.2  matt 	return GT_PCIOK(gt, ga, &gtpci_cd);
    203  1.1  matt }
    204  1.1  matt 
    205  1.1  matt int
    206  1.1  matt gtpci_cfprint(void *aux, const char *pnp)
    207  1.1  matt {
    208  1.1  matt 	struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux;
    209  1.1  matt 
    210  1.1  matt 	if (pnp)
    211  1.2  matt 		aprint_normal("pci at %s", pnp);
    212  1.1  matt 
    213  1.2  matt 	aprint_normal(" bus %d", pba->pba_bus);
    214  1.1  matt 
    215  1.1  matt 	return (UNCONF);
    216  1.1  matt }
    217  1.1  matt 
    218  1.1  matt void
    219  1.1  matt gtpci_attach(struct device *parent, struct device *self, void *aux)
    220  1.1  matt {
    221  1.1  matt 	struct pcibus_attach_args pba;
    222  1.2  matt 	struct gt_attach_args * const ga = aux;
    223  1.2  matt 	struct gt_softc * const gt = (struct gt_softc *) parent;
    224  1.2  matt 	struct gtpci_softc * const gtp = (struct gtpci_softc *) self;
    225  1.2  matt 	struct gtpci_chipset * const gtpc = &gtp->gtpci_gtpc;
    226  1.2  matt 	struct pci_chipset * const pc = &gtpc->gtpc_pc;
    227  1.2  matt 	const int busno = ga->ga_unit;
    228  1.1  matt 	uint32_t data;
    229  1.1  matt 
    230  1.2  matt 	GT_PCIFOUND(gt, ga);
    231  1.1  matt 
    232  1.1  matt 	pc->pc_funcs = &gtpci_functions;
    233  1.1  matt 	pc->pc_parent = self;
    234  1.1  matt 
    235  1.2  matt 	gtpc->gtpc_busno = busno;
    236  1.2  matt 	gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno);
    237  1.2  matt 	gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno);
    238  1.2  matt 	gtpc->gtpc_syncreg = PCI_SYNC_REG(busno);
    239  1.2  matt 	gtpc->gtpc_gt_memt = ga->ga_memt;
    240  1.2  matt 	gtpc->gtpc_gt_memh = ga->ga_memh;
    241  1.1  matt 
    242  1.6  matt 	/*
    243  1.6  matt 	 * Let's find out where we are located.
    244  1.6  matt 	 */
    245  1.6  matt 	data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno));
    246  1.6  matt 	gtpc->gtpc_self = gtpci_make_tag(&gtpc->gtpc_pc,
    247  1.6  matt 		PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0);
    248  1.6  matt 
    249  1.6  matt 
    250  1.1  matt 	switch (busno) {
    251  1.1  matt 	case 0:
    252  1.2  matt 		gtpc->gtpc_io_bs = gt->gt_pci0_iot;
    253  1.2  matt 		gtpc->gtpc_mem_bs = gt->gt_pci0_memt;
    254  1.1  matt 		break;
    255  1.1  matt 	case 1:
    256  1.2  matt 		gtpc->gtpc_io_bs = gt->gt_pci1_iot;
    257  1.2  matt 		gtpc->gtpc_mem_bs = gt->gt_pci1_memt;
    258  1.1  matt 		break;
    259  1.1  matt 	default:
    260  1.1  matt 		break;
    261  1.1  matt 	}
    262  1.1  matt 
    263  1.2  matt 	/*
    264  1.2  matt 	 * If no bus_spaces exist, then it's been disabled.
    265  1.2  matt 	 */
    266  1.2  matt 	if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) {
    267  1.2  matt 		aprint_normal(": disabled\n");
    268  1.2  matt 		return;
    269  1.2  matt 	}
    270  1.2  matt 
    271  1.2  matt 	aprint_normal("\n");
    272  1.2  matt 
    273  1.6  matt 	/*
    274  1.6  matt 	 * clear any pre-existing error interrupt(s)
    275  1.6  matt 	 * clear latched pci error registers
    276  1.6  matt 	 * establish ISRs for PCI errors
    277  1.6  matt 	 * enable PCI error interrupts
    278  1.6  matt 	 */
    279  1.6  matt 	gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0);
    280  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
    281  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
    282  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
    283  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
    284  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
    285  1.6  matt 	intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL, IPL_GTERR,
    286  1.6  matt 	    gtpci_error_intr, pc);
    287  1.6  matt 	intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL, IPL_GTERR,
    288  1.6  matt 	    gtpci_error_intr, pc);
    289  1.6  matt 	intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL, IPL_GTERR,
    290  1.6  matt 	    gtpci_error_intr, pc);
    291  1.6  matt 	aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n",
    292  1.6  matt 	    pc->pc_parent->dv_xname, "pci", busno,
    293  1.6  matt 	    intr_string(pci_irqs[gtpc->gtpc_busno][0]),
    294  1.6  matt 	    intr_string(pci_irqs[gtpc->gtpc_busno][1]),
    295  1.6  matt 	    intr_string(pci_irqs[gtpc->gtpc_busno][2]));
    296  1.6  matt 	gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), PCI_SERRMSK_ALL_ERRS);
    297  1.6  matt 
    298  1.6  matt 	/*
    299  1.6  matt 	 * Fill in the pci_bus_attach_args
    300  1.6  matt 	 */
    301  1.1  matt 	pba.pba_pc = pc;
    302  1.1  matt 	pba.pba_bus = 0;
    303  1.1  matt 	pba.pba_busname = "pci";
    304  1.2  matt 	pba.pba_iot = gtpc->gtpc_io_bs;
    305  1.2  matt 	pba.pba_memt = gtpc->gtpc_mem_bs;
    306  1.1  matt 	pba.pba_dmat = gt->gt_dmat;
    307  1.2  matt 	pba.pba_flags = 0;
    308  1.2  matt 	if (pba.pba_iot != NULL)
    309  1.2  matt 		pba.pba_flags |= PCI_FLAGS_IO_ENABLED;
    310  1.2  matt 	if (pba.pba_memt != NULL)
    311  1.2  matt 		pba.pba_flags |= PCI_FLAGS_MEM_ENABLED;
    312  1.1  matt 
    313  1.2  matt 	data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
    314  1.1  matt 	if (data & PCI_CMD_MRdMul)
    315  1.1  matt 		pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
    316  1.1  matt 	if (data & PCI_CMD_MRdLine)
    317  1.1  matt 		pba.pba_flags |= PCI_FLAGS_MRL_OKAY;
    318  1.1  matt 	pba.pba_flags |= PCI_FLAGS_MWI_OKAY;
    319  1.1  matt 
    320  1.1  matt 	gt_watchdog_service();
    321  1.6  matt 	/*
    322  1.6  matt 	 * Configure the pci bus.
    323  1.6  matt 	 */
    324  1.1  matt 	config_found(self, &pba, gtpci_cfprint);
    325  1.1  matt 
    326  1.1  matt 	gt_watchdog_service();
    327  1.1  matt 
    328  1.1  matt }
    329  1.1  matt 
    330  1.1  matt void
    331  1.5  matt gtpci_bus_init(struct gtpci_chipset *gtpc)
    332  1.5  matt {
    333  1.6  matt 	const struct pci_init *pi;
    334  1.6  matt 	uint32_t data, datal, datah;
    335  1.5  matt 	pcireg_t pcidata;
    336  1.6  matt 	int i;
    337  1.5  matt 
    338  1.5  matt 	/*
    339  1.5  matt 	 * disable all BARs to start.
    340  1.5  matt 	 */
    341  1.5  matt 	gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
    342  1.5  matt 	    0xffffffff);
    343  1.5  matt 
    344  1.5  matt 	/*
    345  1.5  matt 	 * Enable internal arbiter
    346  1.5  matt 	 */
    347  1.5  matt         data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno));
    348  1.6  matt         data |= PCI_ARBCTL_EN;
    349  1.5  matt         gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data);
    350  1.5  matt 
    351  1.5  matt 	/*
    352  1.5  matt 	 * Make the GT reflects reality.
    353  1.6  matt 	 * We always enable internal memory.
    354  1.5  matt 	 */
    355  1.6  matt 	pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20) & 0xfff;
    356  1.6  matt 	gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20,
    357  1.5  matt 	    GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) | pcidata);
    358  1.6  matt 	data = PCI_BARE_IntMemEn;
    359  1.6  matt 
    360  1.6  matt 	for (pi = pci_initinfo[gtpc->gtpc_busno], i = 0; i < 4; i++, pi++)
    361  1.6  matt 		gtpci_write(gtpc, pi->barsize, 0);
    362  1.5  matt 
    363  1.5  matt 	/*
    364  1.6  matt 	 * Enable bus master access (needed for config access).
    365  1.5  matt 	 */
    366  1.6  matt 	pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    367  1.6  matt 	    PCI_COMMAND_STATUS_REG);
    368  1.6  matt 	pcidata |= PCI_COMMAND_MASTER_ENABLE;
    369  1.6  matt 	gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    370  1.6  matt 	    PCI_COMMAND_STATUS_REG, pcidata);
    371  1.5  matt 
    372  1.5  matt 	/*
    373  1.5  matt 	 * Map each SCS BAR to correspond to each SDRAM decode register.
    374  1.5  matt 	 */
    375  1.6  matt 	for (pi = pci_initinfo[gtpc->gtpc_busno], i = 0; i < 4; i++, pi++) {
    376  1.6  matt 		datal = gtpci_read(gtpc, pi->low_decode);
    377  1.6  matt 		datah = gtpci_read(gtpc, pi->high_decode);
    378  1.6  matt 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    379  1.6  matt 		    pi->bar_regno);
    380  1.6  matt 		gtpci_write(gtpc, pi->accctl_high, 0);
    381  1.6  matt 		if (datal < datah) {
    382  1.6  matt 			datal &= 0xfff;
    383  1.6  matt 			pcidata &= 0xfff;
    384  1.6  matt 			pcidata |= datal << 20;
    385  1.6  matt 			data |= pi->bar_enable;
    386  1.6  matt 			datah -= datal;
    387  1.6  matt 			datal |= PCI_ACCCTLBASEL_PrefetchEn|
    388  1.6  matt 			    PCI_ACCCTLBASEL_RdPrefetch|
    389  1.6  matt 			    PCI_ACCCTLBASEL_RdLinePrefetch|
    390  1.6  matt 			    PCI_ACCCTLBASEL_RdMulPrefetch|
    391  1.6  matt 			    PCI_ACCCTLBASEL_WBurst_8_QW|
    392  1.6  matt 			    PCI_ACCCTLBASEL_PCISwap_NoSwap;
    393  1.6  matt 			gtpci_write(gtpc, pi->accctl_low, datal);
    394  1.6  matt 		} else {
    395  1.6  matt 			pcidata &= 0xfff;
    396  1.6  matt 			datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap;
    397  1.6  matt 			datah = 0;
    398  1.6  matt 		}
    399  1.6  matt 		gtpci_write(gtpc, pi->barsize,
    400  1.6  matt 		    datah ? ((datah << 20) | 0xff000) : 0);
    401  1.6  matt 		gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    402  1.6  matt 		    pi->bar_regno, pcidata);
    403  1.6  matt 		gtpci_write(gtpc, pi->accctl_low, datal);
    404  1.6  matt 		gtpci_write(gtpc, pi->accctl_top, datah);
    405  1.5  matt 	}
    406  1.5  matt 
    407  1.5  matt 	/*
    408  1.5  matt 	 * Now re-enable those BARs that are real.
    409  1.5  matt 	 */
    410  1.5  matt 	gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
    411  1.6  matt 	    ~data);
    412  1.5  matt 
    413  1.5  matt 	/*
    414  1.6  matt 	 * Enable I/O and memory (bus master is already enabled) access.
    415  1.5  matt 	 */
    416  1.6  matt 	pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    417  1.6  matt 	    PCI_COMMAND_STATUS_REG);
    418  1.6  matt 	pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
    419  1.6  matt 	gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    420  1.6  matt 	    PCI_COMMAND_STATUS_REG, pcidata);
    421  1.5  matt }
    422  1.5  matt 
    423  1.5  matt void
    424  1.1  matt gtpci_bus_attach_hook(struct device *parent, struct device *self,
    425  1.1  matt 	struct pcibus_attach_args *pba)
    426  1.1  matt {
    427  1.5  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc;
    428  1.5  matt 	uint32_t data;
    429  1.6  matt #if defined(DEBUG)
    430  1.1  matt 	pcitag_t tag;
    431  1.6  matt 	int bus, dev;
    432  1.6  matt 	int i;
    433  1.5  matt #endif
    434  1.1  matt 
    435  1.5  matt 	if (gtpc->gtpc_pc.pc_parent != parent)
    436  1.1  matt 		return;
    437  1.1  matt 
    438  1.2  matt 	data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
    439  1.2  matt 	aprint_normal(": id %d%s%s%s%s%s%s%s%s",
    440  1.1  matt 		PCI_MODE_PciID_GET(data),
    441  1.1  matt 		(data & PCI_MODE_Pci64) ? ", 64bit" : "",
    442  1.1  matt 		(data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "",
    443  1.1  matt 		(data & PCI_MODE_VPD) ? ", VPD" : "",
    444  1.1  matt 		(data & PCI_MODE_MSI) ? ", MSI" : "",
    445  1.1  matt 		(data & PCI_MODE_PMG) ? ", PMG" : "",
    446  1.1  matt 		(data & PCI_MODE_HotSwap) ? ", HotSwap" : "",
    447  1.1  matt 		(data & PCI_MODE_BIST) ? ", BIST" : "",
    448  1.1  matt 		(data & PCI_MODE_PRst) ? "" : ", PRst");
    449  1.1  matt 
    450  1.3  matt #if 0
    451  1.1  matt 	while ((data & PCI_MODE_PRst) == 0) {
    452  1.3  matt 		DELAY(10);
    453  1.2  matt 		data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
    454  1.3  matt 		aprint_normal(".");
    455  1.1  matt 	}
    456  1.3  matt #endif
    457  1.1  matt 
    458  1.5  matt 	gtpci_bus_init(gtpc);
    459  1.5  matt 	gtpci_bus_configure(gtpc);
    460  1.6  matt 
    461  1.6  matt 	data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
    462  1.6  matt 	if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) {
    463  1.6  matt 		aprint_normal("\n%s: ", self->dv_xname);
    464  1.6  matt 		if (data & PCI_CMD_MSwapEn) {
    465  1.6  matt 			switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) {
    466  1.6  matt 			case PCI_CMD_MWordSwap:
    467  1.6  matt 				aprint_normal(" mswap=w"); break;
    468  1.6  matt 			case PCI_CMD_MByteSwap:
    469  1.6  matt 				aprint_normal(" mswap=b"); break;
    470  1.6  matt 			case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap:
    471  1.6  matt 				aprint_normal(" mswap=b+w"); break;
    472  1.6  matt 			case 0:
    473  1.6  matt 				aprint_normal(" mswap=none"); break;
    474  1.6  matt 			}
    475  1.6  matt 		}
    476  1.6  matt 
    477  1.6  matt 		if (data & PCI_CMD_SSwapEn) {
    478  1.6  matt 			switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) {
    479  1.6  matt 			case PCI_CMD_SWordSwap:
    480  1.6  matt 				aprint_normal(" sswap=w"); break;
    481  1.6  matt 			case PCI_CMD_SByteSwap:
    482  1.6  matt 				aprint_normal(" sswap=b"); break;
    483  1.6  matt 			case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap:
    484  1.6  matt 				aprint_normal(" sswap=b+w"); break;
    485  1.6  matt 			case 0:
    486  1.6  matt 				aprint_normal(" sswap=none"); break;
    487  1.6  matt 			}
    488  1.6  matt 		}
    489  1.6  matt 	}
    490  1.6  matt 
    491  1.6  matt #if defined(DEBUG)
    492  1.6  matt 	if (gtpci_debug == 0)
    493  1.6  matt 		return;
    494  1.1  matt 
    495  1.2  matt 	data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno));
    496  1.2  matt 	aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data);
    497  1.1  matt 
    498  1.2  matt 	aprint_normal("\n%s: 0:0:0\n", self->dv_xname);
    499  1.2  matt 	aprint_normal("   %sSCS0=%#010x",
    500  1.1  matt 		(data & 1) ? "-" : "+",
    501  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x10));
    502  1.2  matt 	aprint_normal("/%#010x", gtpci_read(gtpc,
    503  1.6  matt 		PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno)));
    504  1.2  matt 	aprint_normal("  remap %#010x\n",
    505  1.2  matt 		gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    506  1.1  matt 
    507  1.2  matt 	aprint_normal("   %sSCS1=%#010x",
    508  1.1  matt 		(data & 2) ? "-" : "+",
    509  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x14));
    510  1.2  matt 	aprint_normal("/%#010x",
    511  1.6  matt 		gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno)));
    512  1.2  matt 	aprint_normal("  remap %#010x\n",
    513  1.2  matt 		gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    514  1.1  matt 
    515  1.2  matt 	aprint_normal("   %sSCS2=%#010x",
    516  1.1  matt 		(data & 4) ? "-" : "+",
    517  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x18));
    518  1.2  matt 	aprint_normal("/%#010x",
    519  1.6  matt 		gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno)));
    520  1.2  matt 	aprint_normal("  remap %#010x\n",
    521  1.2  matt 		gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    522  1.1  matt 
    523  1.2  matt 	aprint_normal("   %sSCS3=%#010x",
    524  1.1  matt 		(data & 8) ? "-" : "+",
    525  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x1c));
    526  1.2  matt 	aprint_normal("/%#010x",
    527  1.6  matt 		gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno)));
    528  1.2  matt 	aprint_normal("  remap %#010x\n",
    529  1.2  matt 		gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    530  1.1  matt 
    531  1.2  matt 	aprint_normal("   %sIMem=%#010x",
    532  1.1  matt 		(data & PCI_BARE_IntMemEn) ? "-" : "+",
    533  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20));
    534  1.2  matt 	aprint_normal("\n");
    535  1.2  matt 	aprint_normal("    %sIIO=%#010x",
    536  1.1  matt 		(data & PCI_BARE_IntIOEn) ? "-" : "+",
    537  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x24));
    538  1.2  matt 	aprint_normal("\n");
    539  1.6  matt 
    540  1.6  matt 	gtpci_decompose_tag(&gtpc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL);
    541  1.6  matt 	tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, dev, 1);
    542  1.2  matt 	aprint_normal("    %sCS0=%#010x",
    543  1.1  matt 		(data & PCI_BARE_CS0En) ? "-" : "+",
    544  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
    545  1.2  matt 	aprint_normal("/%#010x",
    546  1.6  matt 		gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno)));
    547  1.2  matt 	aprint_normal("  remap %#010x\n",
    548  1.2  matt 		gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    549  1.1  matt 
    550  1.2  matt 	aprint_normal("    %sCS1=%#010x",
    551  1.1  matt 		(data & PCI_BARE_CS1En) ? "-" : "+",
    552  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
    553  1.2  matt 	aprint_normal("/%#010x",
    554  1.6  matt 		gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno)));
    555  1.2  matt 	aprint_normal("  remap %#010x\n",
    556  1.2  matt 		gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    557  1.1  matt 
    558  1.2  matt 	aprint_normal("    %sCS2=%#010x",
    559  1.1  matt 		(data & PCI_BARE_CS2En) ? "-" : "+",
    560  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
    561  1.2  matt 	aprint_normal("/%#010x",
    562  1.6  matt 		gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno)));
    563  1.2  matt 	aprint_normal("  remap %#010x\n",
    564  1.2  matt 		gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    565  1.1  matt 
    566  1.2  matt 	aprint_normal("    %sCS3=%#010x",
    567  1.1  matt 		(data & PCI_BARE_CS3En) ? "-" : "+",
    568  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
    569  1.2  matt 	aprint_normal("/%#010x",
    570  1.6  matt 		gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno)));
    571  1.2  matt 	aprint_normal("  remap %#010x\n",
    572  1.2  matt 		gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    573  1.1  matt 
    574  1.2  matt 	aprint_normal(" %sBootCS=%#010x",
    575  1.1  matt 		(data & PCI_BARE_BootCSEn) ? "-" : "+",
    576  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x20));
    577  1.2  matt 	aprint_normal("/%#010x",
    578  1.6  matt 		gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno)));
    579  1.2  matt 	aprint_normal("  remap %#010x\n",
    580  1.2  matt 		gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno)));
    581  1.1  matt 
    582  1.6  matt 	tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, tag, 2);
    583  1.2  matt 	aprint_normal("  %sP2PM0=%#010x",
    584  1.1  matt 		(data & PCI_BARE_P2PMem0En) ? "-" : "+",
    585  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
    586  1.2  matt 	aprint_normal("/%#010x",
    587  1.6  matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno)));
    588  1.2  matt 	aprint_normal("  remap %#010x.%#010x\n",
    589  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
    590  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
    591  1.1  matt 
    592  1.2  matt 	aprint_normal("  %sP2PM1=%#010x",
    593  1.1  matt 		(data & PCI_BARE_P2PMem1En) ? "-" : "+",
    594  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
    595  1.2  matt 	aprint_normal("/%#010x",
    596  1.6  matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno)));
    597  1.2  matt 	aprint_normal("  remap %#010x.%#010x\n",
    598  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
    599  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
    600  1.1  matt 
    601  1.2  matt 	aprint_normal("  %sP2PIO=%#010x",
    602  1.1  matt 		(data & PCI_BARE_P2PIOEn) ? "-" : "+",
    603  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
    604  1.2  matt 	aprint_normal("/%#010x",
    605  1.6  matt 		gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno)));
    606  1.2  matt 	aprint_normal("  remap %#010x\n",
    607  1.2  matt 		gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    608  1.1  matt 
    609  1.2  matt 	aprint_normal("    %sCPU=%#010x",
    610  1.1  matt 		(data & PCI_BARE_CPUEn) ? "-" : "+",
    611  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
    612  1.2  matt 	aprint_normal("/%#010x",
    613  1.6  matt 		gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno)));
    614  1.2  matt 	aprint_normal("  remap %#010x\n",
    615  1.2  matt 		gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    616  1.1  matt 
    617  1.1  matt 	for (i = 0; i < 8; i++) {
    618  1.2  matt 		aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i);
    619  1.6  matt 		data = gtpci_read(gtpc,
    620  1.6  matt 		    PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i));
    621  1.6  matt 		if (data)
    622  1.6  matt 			aprint_normal("base=0x%08x.", data);
    623  1.6  matt 		else
    624  1.6  matt 			aprint_normal("base=0x");
    625  1.6  matt 		data = gtpci_read(gtpc,
    626  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i));
    627  1.6  matt 		printf("%08x cfg=0x%08x", data << 20, data & ~0xfff);
    628  1.6  matt 		aprint_normal(" top=0x%03x00000",
    629  1.6  matt 		    gtpci_read(gtpc,
    630  1.6  matt 			PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i)));
    631  1.1  matt 	}
    632  1.1  matt #endif
    633  1.1  matt }
    634  1.1  matt 
    635  1.1  matt static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings;
    636  1.1  matt 
    637  1.1  matt int
    638  1.1  matt gtpci_error_intr(void *arg)
    639  1.1  matt {
    640  1.1  matt 	pci_chipset_tag_t pc = arg;
    641  1.2  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    642  1.1  matt 	uint32_t cause, mask, errmask;
    643  1.1  matt 	u_int32_t alo, ahi, dlo, dhi, cmd;
    644  1.1  matt 	int i;
    645  1.1  matt 
    646  1.2  matt 	cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno));
    647  1.2  matt 	errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno));
    648  1.6  matt 	cause &= errmask | 0xf8000000;
    649  1.2  matt 	gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause);
    650  1.1  matt 	printf("%s: pci%d error: cause=%#x mask=%#x",
    651  1.2  matt 		pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask);
    652  1.6  matt 	if ((cause & 0xf8000000) == 0) {
    653  1.1  matt 		printf(" ?\n");
    654  1.1  matt 		return 0;
    655  1.1  matt 	}
    656  1.1  matt 
    657  1.1  matt 	for (i = 0, mask = 1; i <= 26; i++, mask += mask)
    658  1.1  matt 		if (mask & cause)
    659  1.1  matt 			printf(" %s", gtpci_error_strings[i]);
    660  1.1  matt 
    661  1.1  matt 	/*
    662  1.1  matt 	 * "no new data is latched until the PCI Error Low Address
    663  1.1  matt 	 * register is read.  This means that PCI Error Low Address
    664  1.1  matt 	 * register must be the last register read by the interrupt
    665  1.1  matt 	 * handler."
    666  1.1  matt 	 */
    667  1.2  matt 	dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
    668  1.2  matt 	dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
    669  1.2  matt 	cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
    670  1.2  matt 	ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
    671  1.2  matt 	alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
    672  1.6  matt 	printf("\n%s: pci%d error: %s cmd=%#x",
    673  1.2  matt 		pc->pc_parent->dv_xname, gtpc->gtpc_busno,
    674  1.6  matt 		gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd);
    675  1.6  matt 	if (dhi == 0)
    676  1.6  matt 		printf(" data=%08x", dlo);
    677  1.6  matt 	else
    678  1.6  matt 		printf(" data=%08x.%08x", dhi, dlo);
    679  1.6  matt 	if (ahi == 0)
    680  1.6  matt 		printf(" address=%08x\n", alo);
    681  1.6  matt 	else
    682  1.6  matt 		printf(" address=%08x.%08x\n", ahi, alo);
    683  1.1  matt 
    684  1.1  matt #if defined(DEBUG) && defined(DDB)
    685  1.6  matt 	if (gtpci_debug > 1)
    686  1.1  matt 		Debugger();
    687  1.1  matt #endif
    688  1.1  matt 	return 1;
    689  1.1  matt }
    690  1.1  matt 
    691  1.1  matt 
    692  1.1  matt #if 0
    693  1.1  matt void
    694  1.1  matt gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs,
    695  1.1  matt 	struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi)
    696  1.1  matt {
    697  1.1  matt 	/* See how I/O space is configured.  Read the base and top
    698  1.1  matt 	 * registers.
    699  1.1  matt 	 */
    700  1.1  matt 	paddr_t pbasel, pbaseh;
    701  1.1  matt 	uint32_t datal, datah;
    702  1.1  matt 
    703  1.2  matt 	datal = gtpci_read(gtpc, lo);
    704  1.2  matt 	datah = gtpci_read(gtpc, hi);
    705  1.1  matt 	pbasel = GT_LowAddr_GET(datal);
    706  1.1  matt 	pbaseh = GT_HighAddr_GET(datah);
    707  1.1  matt 	/*
    708  1.1  matt 	 * If the start is greater than the end, ignore the region.
    709  1.1  matt  	 */
    710  1.1  matt 	if (pbaseh < pbasel)
    711  1.1  matt 		return;
    712  1.1  matt 	if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase
    713  1.1  matt 	    && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) {
    714  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_vbase =
    715  1.1  matt 			gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask);
    716  1.1  matt 	}
    717  1.1  matt 	bs->bs_regions[bs->bs_nregion].br_pbase = pbasel;
    718  1.1  matt 	if (bs->bs_flags & _BUS_SPACE_RELATIVE) {
    719  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_start = 0;
    720  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel;
    721  1.1  matt 	} else {
    722  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_start = pbasel;
    723  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_end = pbaseh;
    724  1.1  matt 	}
    725  1.1  matt 	bs->bs_nregion++;
    726  1.1  matt }
    727  1.1  matt #endif
    728  1.1  matt 
    729  1.1  matt /*
    730  1.1  matt  * Internal functions.
    731  1.1  matt  */
    732  1.1  matt int
    733  1.1  matt gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
    734  1.1  matt {
    735  1.1  matt 	return 32;
    736  1.1  matt }
    737  1.1  matt 
    738  1.1  matt pcitag_t
    739  1.1  matt gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno)
    740  1.1  matt {
    741  1.1  matt 	return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0);
    742  1.1  matt }
    743  1.1  matt 
    744  1.1  matt void
    745  1.1  matt gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
    746  1.1  matt 		    int *bp, int *dp, int *fp)
    747  1.1  matt {
    748  1.1  matt 	if (bp != NULL)
    749  1.1  matt 		*bp = PCI_CFG_GET_BUSNO(tag);
    750  1.1  matt 	if (dp != NULL)
    751  1.1  matt 		*dp = PCI_CFG_GET_DEVNO(tag);
    752  1.1  matt 	if (fp != NULL)
    753  1.1  matt 		*fp = PCI_CFG_GET_FUNCNO(tag);
    754  1.1  matt }
    755  1.1  matt 
    756  1.1  matt pcireg_t
    757  1.1  matt gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno)
    758  1.1  matt {
    759  1.2  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    760  1.1  matt #ifdef DIAGNOSTIC
    761  1.6  matt 	if ((regno & 3) || (regno & ~0xff))
    762  1.1  matt 		panic("gtpci_conf_read: bad regno %#x\n", regno);
    763  1.1  matt #endif
    764  1.2  matt 	gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
    765  1.2  matt 	return gtpci_read(gtpc, gtpc->gtpc_cfgdata);
    766  1.1  matt }
    767  1.1  matt 
    768  1.1  matt void
    769  1.1  matt gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data)
    770  1.1  matt {
    771  1.2  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    772  1.1  matt #ifdef DIAGNOSTIC
    773  1.6  matt 	if ((regno & 3) || (regno & ~0xff))
    774  1.1  matt 		panic("gtpci_conf_write: bad regno %#x\n", regno);
    775  1.1  matt #endif
    776  1.2  matt 	gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
    777  1.2  matt 	gtpci_write(gtpc, gtpc->gtpc_cfgdata, data);
    778  1.1  matt }
    779  1.1  matt 
    780  1.1  matt const char *
    781  1.1  matt gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih)
    782  1.1  matt {
    783  1.1  matt 	return intr_string(pih);
    784  1.1  matt }
    785  1.1  matt 
    786  1.1  matt const struct evcnt *
    787  1.1  matt gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih)
    788  1.1  matt {
    789  1.1  matt 	return intr_evcnt(pih);
    790  1.1  matt }
    791  1.1  matt 
    792  1.1  matt void *
    793  1.1  matt gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih,
    794  1.1  matt     int ipl, int (*handler)(void *), void *arg)
    795  1.1  matt {
    796  1.1  matt 	return intr_establish(pih, IST_LEVEL, ipl, handler, arg);
    797  1.1  matt }
    798  1.1  matt 
    799  1.1  matt void
    800  1.1  matt gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
    801  1.1  matt {
    802  1.1  matt 	intr_disestablish(cookie);
    803  1.1  matt }
    804