gtpci.c revision 1.8 1 1.8 scw /* $NetBSD: gtpci.c,v 1.8 2003/05/27 11:39:50 scw Exp $ */
2 1.1 matt
3 1.1 matt /*
4 1.1 matt * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5 1.1 matt * All rights reserved.
6 1.1 matt *
7 1.1 matt * Redistribution and use in source and binary forms, with or without
8 1.1 matt * modification, are permitted provided that the following conditions
9 1.1 matt * are met:
10 1.1 matt * 1. Redistributions of source code must retain the above copyright
11 1.1 matt * notice, this list of conditions and the following disclaimer.
12 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 matt * notice, this list of conditions and the following disclaimer in the
14 1.1 matt * documentation and/or other materials provided with the distribution.
15 1.1 matt * 3. All advertising materials mentioning features or use of this software
16 1.1 matt * must display the following acknowledgement:
17 1.1 matt * This product includes software developed for the NetBSD Project by
18 1.1 matt * Allegro Networks, Inc., and Wasabi Systems, Inc.
19 1.1 matt * 4. The name of Allegro Networks, Inc. may not be used to endorse
20 1.1 matt * or promote products derived from this software without specific prior
21 1.1 matt * written permission.
22 1.1 matt * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23 1.1 matt * or promote products derived from this software without specific prior
24 1.1 matt * written permission.
25 1.1 matt *
26 1.1 matt * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27 1.1 matt * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 1.1 matt * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29 1.1 matt * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 1.1 matt * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 1.1 matt * POSSIBILITY OF SUCH DAMAGE.
38 1.1 matt */
39 1.1 matt
40 1.1 matt #include "opt_marvell.h"
41 1.1 matt #include <sys/param.h>
42 1.1 matt #include <sys/device.h>
43 1.1 matt #include <sys/extent.h>
44 1.1 matt #include <sys/malloc.h>
45 1.1 matt #include <lib/libkern/libkern.h>
46 1.1 matt
47 1.1 matt #define _BUS_SPACE_PRIVATE
48 1.1 matt #define _BUS_DMA_PRIVATE
49 1.1 matt #include <machine/bus.h>
50 1.1 matt #include <machine/intr.h>
51 1.1 matt
52 1.1 matt #include <dev/pci/pcireg.h>
53 1.1 matt #include <dev/pci/pcivar.h>
54 1.1 matt #include <dev/pci/pciconf.h>
55 1.1 matt #include <dev/marvell/gtreg.h>
56 1.1 matt #include <dev/marvell/gtvar.h>
57 1.1 matt #include <dev/marvell/gtintrreg.h>
58 1.1 matt #include <dev/marvell/gtpcireg.h>
59 1.1 matt #include <dev/marvell/gtpcivar.h>
60 1.1 matt #include <dev/marvell/gtvar.h>
61 1.1 matt
62 1.1 matt static int gtpci_error_intr(void *);
63 1.1 matt
64 1.5 matt static void gtpci_bus_init(struct gtpci_chipset *);
65 1.5 matt
66 1.1 matt static void gtpci_bus_attach_hook(struct device *, struct device *,
67 1.1 matt struct pcibus_attach_args *);
68 1.1 matt static int gtpci_bus_maxdevs(pci_chipset_tag_t, int);
69 1.1 matt
70 1.1 matt static const char *
71 1.1 matt gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
72 1.1 matt static const struct evcnt *
73 1.1 matt gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
74 1.1 matt static void *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
75 1.1 matt int, int (*)(void *), void *);
76 1.1 matt static void gtpci_intr_disestablish(pci_chipset_tag_t, void *);
77 1.1 matt
78 1.1 matt #ifdef DEBUG
79 1.1 matt int gtpci_debug = 0;
80 1.1 matt #endif
81 1.1 matt
82 1.1 matt struct gtpci_softc {
83 1.1 matt struct device gtpci_dev;
84 1.2 matt struct gtpci_chipset gtpci_gtpc;
85 1.1 matt };
86 1.1 matt
87 1.1 matt static int gtpci_cfprint(void *, const char *);
88 1.1 matt static int gtpci_match(struct device *, struct cfdata *, void *);
89 1.1 matt static void gtpci_attach(struct device *, struct device *, void *);
90 1.1 matt
91 1.1 matt CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc),
92 1.1 matt gtpci_match, gtpci_attach, NULL, NULL);
93 1.1 matt
94 1.1 matt extern struct cfdriver gtpci_cd;
95 1.1 matt
96 1.1 matt const struct pci_chipset_functions gtpci_functions = {
97 1.1 matt gtpci_bus_attach_hook,
98 1.1 matt gtpci_bus_maxdevs,
99 1.1 matt gtpci_md_bus_devorder,
100 1.1 matt
101 1.1 matt gtpci_make_tag,
102 1.1 matt gtpci_decompose_tag,
103 1.1 matt
104 1.1 matt gtpci_conf_read,
105 1.1 matt gtpci_conf_write,
106 1.1 matt gtpci_md_conf_hook,
107 1.1 matt gtpci_md_conf_interrupt,
108 1.1 matt
109 1.1 matt gtpci_md_intr_map,
110 1.1 matt gtpci_intr_string,
111 1.1 matt gtpci_intr_evcnt,
112 1.1 matt gtpci_intr_establish,
113 1.1 matt gtpci_intr_disestablish
114 1.1 matt };
115 1.1 matt
116 1.6 matt static const int pci_irqs[2][3] = {
117 1.6 matt { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 },
118 1.6 matt { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 },
119 1.6 matt };
120 1.6 matt
121 1.6 matt static const struct pci_init {
122 1.6 matt int bar_regno;
123 1.6 matt u_int32_t bar_enable;
124 1.6 matt bus_addr_t low_decode;
125 1.6 matt bus_addr_t high_decode;
126 1.6 matt bus_addr_t barsize;
127 1.6 matt bus_addr_t accctl_high;
128 1.6 matt bus_addr_t accctl_low;
129 1.6 matt bus_addr_t accctl_top;
130 1.6 matt } pci_initinfo[2][4] = {
131 1.6 matt {
132 1.6 matt {
133 1.6 matt 0x10, PCI_BARE_SCS0En,
134 1.6 matt GT_SCS0_Low_Decode, GT_SCS0_High_Decode,
135 1.6 matt PCI_SCS0_BAR_SIZE(0),
136 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(0, 0),
137 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(0, 0),
138 1.6 matt PCI_ACCESS_CONTROL_TOP(0, 0),
139 1.6 matt }, {
140 1.6 matt 0x14, PCI_BARE_SCS1En,
141 1.6 matt GT_SCS1_Low_Decode, GT_SCS1_High_Decode,
142 1.6 matt PCI_SCS1_BAR_SIZE(0),
143 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(0, 1),
144 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(0, 1),
145 1.6 matt PCI_ACCESS_CONTROL_TOP(0, 1),
146 1.6 matt }, {
147 1.6 matt 0x18, PCI_BARE_SCS2En,
148 1.6 matt GT_SCS2_Low_Decode, GT_SCS2_High_Decode,
149 1.6 matt PCI_SCS2_BAR_SIZE(0),
150 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(0, 2),
151 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(0, 2),
152 1.6 matt PCI_ACCESS_CONTROL_TOP(0, 2),
153 1.6 matt }, {
154 1.6 matt 0x1c, PCI_BARE_SCS3En,
155 1.6 matt GT_SCS3_Low_Decode, GT_SCS3_High_Decode,
156 1.6 matt PCI_SCS3_BAR_SIZE(0),
157 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(0, 3),
158 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(0, 3),
159 1.6 matt PCI_ACCESS_CONTROL_TOP(0, 3),
160 1.6 matt },
161 1.6 matt }, {
162 1.6 matt {
163 1.6 matt 0x10, PCI_BARE_SCS0En,
164 1.6 matt GT_SCS0_Low_Decode, GT_SCS0_High_Decode,
165 1.6 matt PCI_SCS0_BAR_SIZE(1),
166 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(1, 0),
167 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(1, 0),
168 1.6 matt PCI_ACCESS_CONTROL_TOP(1, 0),
169 1.6 matt }, {
170 1.6 matt 0x14, PCI_BARE_SCS1En,
171 1.6 matt GT_SCS1_Low_Decode, GT_SCS1_High_Decode,
172 1.6 matt PCI_SCS1_BAR_SIZE(1),
173 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(1, 1),
174 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(1, 1),
175 1.6 matt PCI_ACCESS_CONTROL_TOP(1, 1),
176 1.6 matt }, {
177 1.6 matt 0x18, PCI_BARE_SCS2En,
178 1.6 matt GT_SCS2_Low_Decode, GT_SCS2_High_Decode,
179 1.6 matt PCI_SCS2_BAR_SIZE(1),
180 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(1, 2),
181 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(1, 2),
182 1.6 matt PCI_ACCESS_CONTROL_TOP(1, 2),
183 1.6 matt }, {
184 1.6 matt 0x1c, PCI_BARE_SCS3En,
185 1.6 matt GT_SCS3_Low_Decode, GT_SCS3_High_Decode,
186 1.6 matt PCI_SCS3_BAR_SIZE(1),
187 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(1, 3),
188 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(1, 3),
189 1.6 matt PCI_ACCESS_CONTROL_TOP(1, 3),
190 1.6 matt },
191 1.6 matt }
192 1.6 matt };
193 1.6 matt
194 1.1 matt int
195 1.1 matt gtpci_match(struct device *parent, struct cfdata *self, void *aux)
196 1.1 matt {
197 1.2 matt struct gt_softc * const gt = (struct gt_softc *) parent;
198 1.2 matt struct gt_attach_args * const ga = aux;
199 1.1 matt
200 1.2 matt return GT_PCIOK(gt, ga, >pci_cd);
201 1.1 matt }
202 1.1 matt
203 1.1 matt int
204 1.1 matt gtpci_cfprint(void *aux, const char *pnp)
205 1.1 matt {
206 1.1 matt struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux;
207 1.1 matt
208 1.1 matt if (pnp)
209 1.2 matt aprint_normal("pci at %s", pnp);
210 1.1 matt
211 1.2 matt aprint_normal(" bus %d", pba->pba_bus);
212 1.1 matt
213 1.1 matt return (UNCONF);
214 1.1 matt }
215 1.1 matt
216 1.1 matt void
217 1.1 matt gtpci_attach(struct device *parent, struct device *self, void *aux)
218 1.1 matt {
219 1.1 matt struct pcibus_attach_args pba;
220 1.2 matt struct gt_attach_args * const ga = aux;
221 1.2 matt struct gt_softc * const gt = (struct gt_softc *) parent;
222 1.2 matt struct gtpci_softc * const gtp = (struct gtpci_softc *) self;
223 1.2 matt struct gtpci_chipset * const gtpc = >p->gtpci_gtpc;
224 1.2 matt struct pci_chipset * const pc = >pc->gtpc_pc;
225 1.2 matt const int busno = ga->ga_unit;
226 1.1 matt uint32_t data;
227 1.1 matt
228 1.2 matt GT_PCIFOUND(gt, ga);
229 1.1 matt
230 1.1 matt pc->pc_funcs = >pci_functions;
231 1.1 matt pc->pc_parent = self;
232 1.1 matt
233 1.2 matt gtpc->gtpc_busno = busno;
234 1.2 matt gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno);
235 1.2 matt gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno);
236 1.2 matt gtpc->gtpc_syncreg = PCI_SYNC_REG(busno);
237 1.2 matt gtpc->gtpc_gt_memt = ga->ga_memt;
238 1.2 matt gtpc->gtpc_gt_memh = ga->ga_memh;
239 1.1 matt
240 1.6 matt /*
241 1.6 matt * Let's find out where we are located.
242 1.6 matt */
243 1.6 matt data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno));
244 1.6 matt gtpc->gtpc_self = gtpci_make_tag(>pc->gtpc_pc,
245 1.6 matt PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0);
246 1.6 matt
247 1.6 matt
248 1.1 matt switch (busno) {
249 1.1 matt case 0:
250 1.2 matt gtpc->gtpc_io_bs = gt->gt_pci0_iot;
251 1.2 matt gtpc->gtpc_mem_bs = gt->gt_pci0_memt;
252 1.1 matt break;
253 1.1 matt case 1:
254 1.2 matt gtpc->gtpc_io_bs = gt->gt_pci1_iot;
255 1.2 matt gtpc->gtpc_mem_bs = gt->gt_pci1_memt;
256 1.1 matt break;
257 1.1 matt default:
258 1.1 matt break;
259 1.1 matt }
260 1.1 matt
261 1.2 matt /*
262 1.2 matt * If no bus_spaces exist, then it's been disabled.
263 1.2 matt */
264 1.2 matt if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) {
265 1.2 matt aprint_normal(": disabled\n");
266 1.2 matt return;
267 1.2 matt }
268 1.2 matt
269 1.2 matt aprint_normal("\n");
270 1.2 matt
271 1.6 matt /*
272 1.6 matt * clear any pre-existing error interrupt(s)
273 1.6 matt * clear latched pci error registers
274 1.6 matt * establish ISRs for PCI errors
275 1.6 matt * enable PCI error interrupts
276 1.6 matt */
277 1.6 matt gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0);
278 1.6 matt (void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
279 1.6 matt (void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
280 1.6 matt (void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
281 1.6 matt (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
282 1.6 matt (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
283 1.6 matt intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL, IPL_GTERR,
284 1.6 matt gtpci_error_intr, pc);
285 1.6 matt intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL, IPL_GTERR,
286 1.6 matt gtpci_error_intr, pc);
287 1.6 matt intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL, IPL_GTERR,
288 1.6 matt gtpci_error_intr, pc);
289 1.6 matt aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n",
290 1.6 matt pc->pc_parent->dv_xname, "pci", busno,
291 1.6 matt intr_string(pci_irqs[gtpc->gtpc_busno][0]),
292 1.6 matt intr_string(pci_irqs[gtpc->gtpc_busno][1]),
293 1.6 matt intr_string(pci_irqs[gtpc->gtpc_busno][2]));
294 1.6 matt gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), PCI_SERRMSK_ALL_ERRS);
295 1.6 matt
296 1.6 matt /*
297 1.6 matt * Fill in the pci_bus_attach_args
298 1.6 matt */
299 1.1 matt pba.pba_pc = pc;
300 1.1 matt pba.pba_bus = 0;
301 1.1 matt pba.pba_busname = "pci";
302 1.2 matt pba.pba_iot = gtpc->gtpc_io_bs;
303 1.2 matt pba.pba_memt = gtpc->gtpc_mem_bs;
304 1.1 matt pba.pba_dmat = gt->gt_dmat;
305 1.2 matt pba.pba_flags = 0;
306 1.2 matt if (pba.pba_iot != NULL)
307 1.2 matt pba.pba_flags |= PCI_FLAGS_IO_ENABLED;
308 1.2 matt if (pba.pba_memt != NULL)
309 1.2 matt pba.pba_flags |= PCI_FLAGS_MEM_ENABLED;
310 1.1 matt
311 1.2 matt data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
312 1.1 matt if (data & PCI_CMD_MRdMul)
313 1.1 matt pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
314 1.1 matt if (data & PCI_CMD_MRdLine)
315 1.1 matt pba.pba_flags |= PCI_FLAGS_MRL_OKAY;
316 1.1 matt pba.pba_flags |= PCI_FLAGS_MWI_OKAY;
317 1.1 matt
318 1.1 matt gt_watchdog_service();
319 1.6 matt /*
320 1.6 matt * Configure the pci bus.
321 1.6 matt */
322 1.1 matt config_found(self, &pba, gtpci_cfprint);
323 1.1 matt
324 1.1 matt gt_watchdog_service();
325 1.1 matt
326 1.1 matt }
327 1.1 matt
328 1.1 matt void
329 1.5 matt gtpci_bus_init(struct gtpci_chipset *gtpc)
330 1.5 matt {
331 1.6 matt const struct pci_init *pi;
332 1.6 matt uint32_t data, datal, datah;
333 1.5 matt pcireg_t pcidata;
334 1.6 matt int i;
335 1.5 matt
336 1.5 matt /*
337 1.5 matt * disable all BARs to start.
338 1.5 matt */
339 1.5 matt gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
340 1.5 matt 0xffffffff);
341 1.5 matt
342 1.8 scw #ifndef GT_PCI0_EXT_ARBITER
343 1.8 scw #define GT_PCI0_EXT_ARBITER 0
344 1.8 scw #endif
345 1.8 scw #ifndef GT_PCI1_EXT_ARBITER
346 1.8 scw #define GT_PCI1_EXT_ARBITER 0
347 1.8 scw #endif
348 1.8 scw
349 1.8 scw if ((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) ||
350 1.8 scw (!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1)) {
351 1.8 scw /*
352 1.8 scw * Enable internal arbiter
353 1.8 scw */
354 1.8 scw data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno));
355 1.8 scw data |= PCI_ARBCTL_EN;
356 1.8 scw gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data);
357 1.8 scw } else {
358 1.8 scw /*
359 1.8 scw * Make sure the internal arbiter is disabled
360 1.8 scw */
361 1.8 scw gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0);
362 1.8 scw }
363 1.5 matt
364 1.5 matt /*
365 1.5 matt * Make the GT reflects reality.
366 1.6 matt * We always enable internal memory.
367 1.5 matt */
368 1.6 matt pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20) & 0xfff;
369 1.6 matt gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 0x20,
370 1.5 matt GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) | pcidata);
371 1.6 matt data = PCI_BARE_IntMemEn;
372 1.6 matt
373 1.7 matt for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++)
374 1.6 matt gtpci_write(gtpc, pi->barsize, 0);
375 1.5 matt
376 1.5 matt /*
377 1.6 matt * Enable bus master access (needed for config access).
378 1.5 matt */
379 1.6 matt pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
380 1.6 matt PCI_COMMAND_STATUS_REG);
381 1.6 matt pcidata |= PCI_COMMAND_MASTER_ENABLE;
382 1.6 matt gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
383 1.6 matt PCI_COMMAND_STATUS_REG, pcidata);
384 1.5 matt
385 1.5 matt /*
386 1.5 matt * Map each SCS BAR to correspond to each SDRAM decode register.
387 1.5 matt */
388 1.7 matt for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) {
389 1.6 matt datal = gtpci_read(gtpc, pi->low_decode);
390 1.6 matt datah = gtpci_read(gtpc, pi->high_decode);
391 1.6 matt pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
392 1.6 matt pi->bar_regno);
393 1.6 matt gtpci_write(gtpc, pi->accctl_high, 0);
394 1.6 matt if (datal < datah) {
395 1.6 matt datal &= 0xfff;
396 1.6 matt pcidata &= 0xfff;
397 1.6 matt pcidata |= datal << 20;
398 1.6 matt data |= pi->bar_enable;
399 1.6 matt datah -= datal;
400 1.6 matt datal |= PCI_ACCCTLBASEL_PrefetchEn|
401 1.6 matt PCI_ACCCTLBASEL_RdPrefetch|
402 1.6 matt PCI_ACCCTLBASEL_RdLinePrefetch|
403 1.6 matt PCI_ACCCTLBASEL_RdMulPrefetch|
404 1.6 matt PCI_ACCCTLBASEL_WBurst_8_QW|
405 1.6 matt PCI_ACCCTLBASEL_PCISwap_NoSwap;
406 1.6 matt gtpci_write(gtpc, pi->accctl_low, datal);
407 1.6 matt } else {
408 1.6 matt pcidata &= 0xfff;
409 1.6 matt datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap;
410 1.6 matt datah = 0;
411 1.6 matt }
412 1.6 matt gtpci_write(gtpc, pi->barsize,
413 1.6 matt datah ? ((datah << 20) | 0xff000) : 0);
414 1.6 matt gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
415 1.6 matt pi->bar_regno, pcidata);
416 1.6 matt gtpci_write(gtpc, pi->accctl_low, datal);
417 1.6 matt gtpci_write(gtpc, pi->accctl_top, datah);
418 1.5 matt }
419 1.5 matt
420 1.5 matt /*
421 1.5 matt * Now re-enable those BARs that are real.
422 1.5 matt */
423 1.5 matt gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
424 1.6 matt ~data);
425 1.5 matt
426 1.5 matt /*
427 1.6 matt * Enable I/O and memory (bus master is already enabled) access.
428 1.5 matt */
429 1.6 matt pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
430 1.6 matt PCI_COMMAND_STATUS_REG);
431 1.6 matt pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
432 1.6 matt gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
433 1.6 matt PCI_COMMAND_STATUS_REG, pcidata);
434 1.5 matt }
435 1.5 matt
436 1.5 matt void
437 1.1 matt gtpci_bus_attach_hook(struct device *parent, struct device *self,
438 1.1 matt struct pcibus_attach_args *pba)
439 1.1 matt {
440 1.5 matt struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc;
441 1.5 matt uint32_t data;
442 1.6 matt #if defined(DEBUG)
443 1.1 matt pcitag_t tag;
444 1.6 matt int bus, dev;
445 1.6 matt int i;
446 1.5 matt #endif
447 1.1 matt
448 1.5 matt if (gtpc->gtpc_pc.pc_parent != parent)
449 1.1 matt return;
450 1.1 matt
451 1.2 matt data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
452 1.2 matt aprint_normal(": id %d%s%s%s%s%s%s%s%s",
453 1.1 matt PCI_MODE_PciID_GET(data),
454 1.1 matt (data & PCI_MODE_Pci64) ? ", 64bit" : "",
455 1.1 matt (data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "",
456 1.1 matt (data & PCI_MODE_VPD) ? ", VPD" : "",
457 1.1 matt (data & PCI_MODE_MSI) ? ", MSI" : "",
458 1.1 matt (data & PCI_MODE_PMG) ? ", PMG" : "",
459 1.1 matt (data & PCI_MODE_HotSwap) ? ", HotSwap" : "",
460 1.1 matt (data & PCI_MODE_BIST) ? ", BIST" : "",
461 1.1 matt (data & PCI_MODE_PRst) ? "" : ", PRst");
462 1.1 matt
463 1.3 matt #if 0
464 1.1 matt while ((data & PCI_MODE_PRst) == 0) {
465 1.3 matt DELAY(10);
466 1.2 matt data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
467 1.3 matt aprint_normal(".");
468 1.1 matt }
469 1.3 matt #endif
470 1.1 matt
471 1.5 matt gtpci_bus_init(gtpc);
472 1.5 matt gtpci_bus_configure(gtpc);
473 1.6 matt
474 1.6 matt data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
475 1.6 matt if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) {
476 1.6 matt aprint_normal("\n%s: ", self->dv_xname);
477 1.6 matt if (data & PCI_CMD_MSwapEn) {
478 1.6 matt switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) {
479 1.6 matt case PCI_CMD_MWordSwap:
480 1.6 matt aprint_normal(" mswap=w"); break;
481 1.6 matt case PCI_CMD_MByteSwap:
482 1.6 matt aprint_normal(" mswap=b"); break;
483 1.6 matt case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap:
484 1.6 matt aprint_normal(" mswap=b+w"); break;
485 1.6 matt case 0:
486 1.6 matt aprint_normal(" mswap=none"); break;
487 1.6 matt }
488 1.6 matt }
489 1.6 matt
490 1.6 matt if (data & PCI_CMD_SSwapEn) {
491 1.6 matt switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) {
492 1.6 matt case PCI_CMD_SWordSwap:
493 1.6 matt aprint_normal(" sswap=w"); break;
494 1.6 matt case PCI_CMD_SByteSwap:
495 1.6 matt aprint_normal(" sswap=b"); break;
496 1.6 matt case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap:
497 1.6 matt aprint_normal(" sswap=b+w"); break;
498 1.6 matt case 0:
499 1.6 matt aprint_normal(" sswap=none"); break;
500 1.6 matt }
501 1.6 matt }
502 1.6 matt }
503 1.6 matt
504 1.6 matt #if defined(DEBUG)
505 1.6 matt if (gtpci_debug == 0)
506 1.6 matt return;
507 1.1 matt
508 1.2 matt data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno));
509 1.2 matt aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data);
510 1.1 matt
511 1.2 matt aprint_normal("\n%s: 0:0:0\n", self->dv_xname);
512 1.2 matt aprint_normal(" %sSCS0=%#010x",
513 1.1 matt (data & 1) ? "-" : "+",
514 1.6 matt gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x10));
515 1.2 matt aprint_normal("/%#010x", gtpci_read(gtpc,
516 1.6 matt PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno)));
517 1.2 matt aprint_normal(" remap %#010x\n",
518 1.2 matt gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
519 1.1 matt
520 1.2 matt aprint_normal(" %sSCS1=%#010x",
521 1.1 matt (data & 2) ? "-" : "+",
522 1.6 matt gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x14));
523 1.2 matt aprint_normal("/%#010x",
524 1.6 matt gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno)));
525 1.2 matt aprint_normal(" remap %#010x\n",
526 1.2 matt gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
527 1.1 matt
528 1.2 matt aprint_normal(" %sSCS2=%#010x",
529 1.1 matt (data & 4) ? "-" : "+",
530 1.6 matt gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x18));
531 1.2 matt aprint_normal("/%#010x",
532 1.6 matt gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno)));
533 1.2 matt aprint_normal(" remap %#010x\n",
534 1.2 matt gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
535 1.1 matt
536 1.2 matt aprint_normal(" %sSCS3=%#010x",
537 1.1 matt (data & 8) ? "-" : "+",
538 1.6 matt gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x1c));
539 1.2 matt aprint_normal("/%#010x",
540 1.6 matt gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno)));
541 1.2 matt aprint_normal(" remap %#010x\n",
542 1.2 matt gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
543 1.1 matt
544 1.2 matt aprint_normal(" %sIMem=%#010x",
545 1.1 matt (data & PCI_BARE_IntMemEn) ? "-" : "+",
546 1.6 matt gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20));
547 1.2 matt aprint_normal("\n");
548 1.2 matt aprint_normal(" %sIIO=%#010x",
549 1.1 matt (data & PCI_BARE_IntIOEn) ? "-" : "+",
550 1.6 matt gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x24));
551 1.2 matt aprint_normal("\n");
552 1.6 matt
553 1.6 matt gtpci_decompose_tag(>pc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL);
554 1.6 matt tag = gtpci_make_tag(>pc->gtpc_pc, bus, dev, 1);
555 1.2 matt aprint_normal(" %sCS0=%#010x",
556 1.1 matt (data & PCI_BARE_CS0En) ? "-" : "+",
557 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x10));
558 1.2 matt aprint_normal("/%#010x",
559 1.6 matt gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno)));
560 1.2 matt aprint_normal(" remap %#010x\n",
561 1.2 matt gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
562 1.1 matt
563 1.2 matt aprint_normal(" %sCS1=%#010x",
564 1.1 matt (data & PCI_BARE_CS1En) ? "-" : "+",
565 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x14));
566 1.2 matt aprint_normal("/%#010x",
567 1.6 matt gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno)));
568 1.2 matt aprint_normal(" remap %#010x\n",
569 1.2 matt gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
570 1.1 matt
571 1.2 matt aprint_normal(" %sCS2=%#010x",
572 1.1 matt (data & PCI_BARE_CS2En) ? "-" : "+",
573 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x18));
574 1.2 matt aprint_normal("/%#010x",
575 1.6 matt gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno)));
576 1.2 matt aprint_normal(" remap %#010x\n",
577 1.2 matt gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
578 1.1 matt
579 1.2 matt aprint_normal(" %sCS3=%#010x",
580 1.1 matt (data & PCI_BARE_CS3En) ? "-" : "+",
581 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c));
582 1.2 matt aprint_normal("/%#010x",
583 1.6 matt gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno)));
584 1.2 matt aprint_normal(" remap %#010x\n",
585 1.2 matt gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
586 1.1 matt
587 1.2 matt aprint_normal(" %sBootCS=%#010x",
588 1.1 matt (data & PCI_BARE_BootCSEn) ? "-" : "+",
589 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x20));
590 1.2 matt aprint_normal("/%#010x",
591 1.6 matt gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno)));
592 1.2 matt aprint_normal(" remap %#010x\n",
593 1.2 matt gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno)));
594 1.1 matt
595 1.6 matt tag = gtpci_make_tag(>pc->gtpc_pc, bus, tag, 2);
596 1.2 matt aprint_normal(" %sP2PM0=%#010x",
597 1.1 matt (data & PCI_BARE_P2PMem0En) ? "-" : "+",
598 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x10));
599 1.2 matt aprint_normal("/%#010x",
600 1.6 matt gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno)));
601 1.2 matt aprint_normal(" remap %#010x.%#010x\n",
602 1.2 matt gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
603 1.2 matt gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
604 1.1 matt
605 1.2 matt aprint_normal(" %sP2PM1=%#010x",
606 1.1 matt (data & PCI_BARE_P2PMem1En) ? "-" : "+",
607 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x14));
608 1.2 matt aprint_normal("/%#010x",
609 1.6 matt gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno)));
610 1.2 matt aprint_normal(" remap %#010x.%#010x\n",
611 1.2 matt gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
612 1.2 matt gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
613 1.1 matt
614 1.2 matt aprint_normal(" %sP2PIO=%#010x",
615 1.1 matt (data & PCI_BARE_P2PIOEn) ? "-" : "+",
616 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x18));
617 1.2 matt aprint_normal("/%#010x",
618 1.6 matt gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno)));
619 1.2 matt aprint_normal(" remap %#010x\n",
620 1.2 matt gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
621 1.1 matt
622 1.2 matt aprint_normal(" %sCPU=%#010x",
623 1.1 matt (data & PCI_BARE_CPUEn) ? "-" : "+",
624 1.6 matt gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c));
625 1.2 matt aprint_normal("/%#010x",
626 1.6 matt gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno)));
627 1.2 matt aprint_normal(" remap %#010x\n",
628 1.2 matt gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
629 1.1 matt
630 1.1 matt for (i = 0; i < 8; i++) {
631 1.2 matt aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i);
632 1.6 matt data = gtpci_read(gtpc,
633 1.6 matt PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i));
634 1.6 matt if (data)
635 1.6 matt aprint_normal("base=0x%08x.", data);
636 1.6 matt else
637 1.6 matt aprint_normal("base=0x");
638 1.6 matt data = gtpci_read(gtpc,
639 1.6 matt PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i));
640 1.6 matt printf("%08x cfg=0x%08x", data << 20, data & ~0xfff);
641 1.6 matt aprint_normal(" top=0x%03x00000",
642 1.6 matt gtpci_read(gtpc,
643 1.6 matt PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i)));
644 1.1 matt }
645 1.1 matt #endif
646 1.1 matt }
647 1.1 matt
648 1.1 matt static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings;
649 1.1 matt
650 1.1 matt int
651 1.1 matt gtpci_error_intr(void *arg)
652 1.1 matt {
653 1.1 matt pci_chipset_tag_t pc = arg;
654 1.2 matt struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
655 1.1 matt uint32_t cause, mask, errmask;
656 1.1 matt u_int32_t alo, ahi, dlo, dhi, cmd;
657 1.1 matt int i;
658 1.1 matt
659 1.2 matt cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno));
660 1.2 matt errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno));
661 1.6 matt cause &= errmask | 0xf8000000;
662 1.2 matt gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause);
663 1.1 matt printf("%s: pci%d error: cause=%#x mask=%#x",
664 1.2 matt pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask);
665 1.6 matt if ((cause & 0xf8000000) == 0) {
666 1.1 matt printf(" ?\n");
667 1.1 matt return 0;
668 1.1 matt }
669 1.1 matt
670 1.1 matt for (i = 0, mask = 1; i <= 26; i++, mask += mask)
671 1.1 matt if (mask & cause)
672 1.1 matt printf(" %s", gtpci_error_strings[i]);
673 1.1 matt
674 1.1 matt /*
675 1.1 matt * "no new data is latched until the PCI Error Low Address
676 1.1 matt * register is read. This means that PCI Error Low Address
677 1.1 matt * register must be the last register read by the interrupt
678 1.1 matt * handler."
679 1.1 matt */
680 1.2 matt dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
681 1.2 matt dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
682 1.2 matt cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
683 1.2 matt ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
684 1.2 matt alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
685 1.6 matt printf("\n%s: pci%d error: %s cmd=%#x",
686 1.2 matt pc->pc_parent->dv_xname, gtpc->gtpc_busno,
687 1.6 matt gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd);
688 1.6 matt if (dhi == 0)
689 1.6 matt printf(" data=%08x", dlo);
690 1.6 matt else
691 1.6 matt printf(" data=%08x.%08x", dhi, dlo);
692 1.6 matt if (ahi == 0)
693 1.6 matt printf(" address=%08x\n", alo);
694 1.6 matt else
695 1.6 matt printf(" address=%08x.%08x\n", ahi, alo);
696 1.1 matt
697 1.1 matt #if defined(DEBUG) && defined(DDB)
698 1.6 matt if (gtpci_debug > 1)
699 1.1 matt Debugger();
700 1.1 matt #endif
701 1.1 matt return 1;
702 1.1 matt }
703 1.1 matt
704 1.1 matt
705 1.1 matt #if 0
706 1.1 matt void
707 1.1 matt gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs,
708 1.1 matt struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi)
709 1.1 matt {
710 1.1 matt /* See how I/O space is configured. Read the base and top
711 1.1 matt * registers.
712 1.1 matt */
713 1.1 matt paddr_t pbasel, pbaseh;
714 1.1 matt uint32_t datal, datah;
715 1.1 matt
716 1.2 matt datal = gtpci_read(gtpc, lo);
717 1.2 matt datah = gtpci_read(gtpc, hi);
718 1.1 matt pbasel = GT_LowAddr_GET(datal);
719 1.1 matt pbaseh = GT_HighAddr_GET(datah);
720 1.1 matt /*
721 1.1 matt * If the start is greater than the end, ignore the region.
722 1.1 matt */
723 1.1 matt if (pbaseh < pbasel)
724 1.1 matt return;
725 1.1 matt if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase
726 1.1 matt && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) {
727 1.1 matt bs->bs_regions[bs->bs_nregion].br_vbase =
728 1.1 matt gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask);
729 1.1 matt }
730 1.1 matt bs->bs_regions[bs->bs_nregion].br_pbase = pbasel;
731 1.1 matt if (bs->bs_flags & _BUS_SPACE_RELATIVE) {
732 1.1 matt bs->bs_regions[bs->bs_nregion].br_start = 0;
733 1.1 matt bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel;
734 1.1 matt } else {
735 1.1 matt bs->bs_regions[bs->bs_nregion].br_start = pbasel;
736 1.1 matt bs->bs_regions[bs->bs_nregion].br_end = pbaseh;
737 1.1 matt }
738 1.1 matt bs->bs_nregion++;
739 1.1 matt }
740 1.1 matt #endif
741 1.1 matt
742 1.1 matt /*
743 1.1 matt * Internal functions.
744 1.1 matt */
745 1.1 matt int
746 1.1 matt gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
747 1.1 matt {
748 1.1 matt return 32;
749 1.1 matt }
750 1.1 matt
751 1.1 matt pcitag_t
752 1.1 matt gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno)
753 1.1 matt {
754 1.1 matt return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0);
755 1.1 matt }
756 1.1 matt
757 1.1 matt void
758 1.1 matt gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
759 1.1 matt int *bp, int *dp, int *fp)
760 1.1 matt {
761 1.1 matt if (bp != NULL)
762 1.1 matt *bp = PCI_CFG_GET_BUSNO(tag);
763 1.1 matt if (dp != NULL)
764 1.1 matt *dp = PCI_CFG_GET_DEVNO(tag);
765 1.1 matt if (fp != NULL)
766 1.1 matt *fp = PCI_CFG_GET_FUNCNO(tag);
767 1.1 matt }
768 1.1 matt
769 1.1 matt pcireg_t
770 1.1 matt gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno)
771 1.1 matt {
772 1.2 matt struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
773 1.1 matt #ifdef DIAGNOSTIC
774 1.6 matt if ((regno & 3) || (regno & ~0xff))
775 1.1 matt panic("gtpci_conf_read: bad regno %#x\n", regno);
776 1.1 matt #endif
777 1.2 matt gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
778 1.2 matt return gtpci_read(gtpc, gtpc->gtpc_cfgdata);
779 1.1 matt }
780 1.1 matt
781 1.1 matt void
782 1.1 matt gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data)
783 1.1 matt {
784 1.2 matt struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
785 1.1 matt #ifdef DIAGNOSTIC
786 1.6 matt if ((regno & 3) || (regno & ~0xff))
787 1.1 matt panic("gtpci_conf_write: bad regno %#x\n", regno);
788 1.1 matt #endif
789 1.2 matt gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
790 1.2 matt gtpci_write(gtpc, gtpc->gtpc_cfgdata, data);
791 1.1 matt }
792 1.1 matt
793 1.1 matt const char *
794 1.1 matt gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih)
795 1.1 matt {
796 1.1 matt return intr_string(pih);
797 1.1 matt }
798 1.1 matt
799 1.1 matt const struct evcnt *
800 1.1 matt gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih)
801 1.1 matt {
802 1.1 matt return intr_evcnt(pih);
803 1.1 matt }
804 1.1 matt
805 1.1 matt void *
806 1.1 matt gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih,
807 1.1 matt int ipl, int (*handler)(void *), void *arg)
808 1.1 matt {
809 1.1 matt return intr_establish(pih, IST_LEVEL, ipl, handler, arg);
810 1.1 matt }
811 1.1 matt
812 1.1 matt void
813 1.1 matt gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
814 1.1 matt {
815 1.1 matt intr_disestablish(cookie);
816 1.1 matt }
817