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gtpci.c revision 1.9
      1  1.9   scw /*	$NetBSD: gtpci.c,v 1.9 2003/06/12 19:18:49 scw Exp $	*/
      2  1.1  matt 
      3  1.1  matt /*
      4  1.1  matt  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
      5  1.1  matt  * All rights reserved.
      6  1.1  matt  *
      7  1.1  matt  * Redistribution and use in source and binary forms, with or without
      8  1.1  matt  * modification, are permitted provided that the following conditions
      9  1.1  matt  * are met:
     10  1.1  matt  * 1. Redistributions of source code must retain the above copyright
     11  1.1  matt  *    notice, this list of conditions and the following disclaimer.
     12  1.1  matt  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  matt  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  matt  *    documentation and/or other materials provided with the distribution.
     15  1.1  matt  * 3. All advertising materials mentioning features or use of this software
     16  1.1  matt  *    must display the following acknowledgement:
     17  1.1  matt  *      This product includes software developed for the NetBSD Project by
     18  1.1  matt  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
     19  1.1  matt  * 4. The name of Allegro Networks, Inc. may not be used to endorse
     20  1.1  matt  *    or promote products derived from this software without specific prior
     21  1.1  matt  *    written permission.
     22  1.1  matt  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
     23  1.1  matt  *    or promote products derived from this software without specific prior
     24  1.1  matt  *    written permission.
     25  1.1  matt  *
     26  1.1  matt  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
     27  1.1  matt  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     28  1.1  matt  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
     29  1.1  matt  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     30  1.1  matt  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
     31  1.1  matt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     32  1.1  matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     33  1.1  matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     34  1.1  matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     35  1.1  matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     36  1.1  matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     37  1.1  matt  * POSSIBILITY OF SUCH DAMAGE.
     38  1.1  matt  */
     39  1.1  matt 
     40  1.1  matt #include "opt_marvell.h"
     41  1.1  matt #include <sys/param.h>
     42  1.1  matt #include <sys/device.h>
     43  1.1  matt #include <sys/extent.h>
     44  1.1  matt #include <sys/malloc.h>
     45  1.1  matt #include <lib/libkern/libkern.h>
     46  1.1  matt 
     47  1.1  matt #define _BUS_SPACE_PRIVATE
     48  1.1  matt #define _BUS_DMA_PRIVATE
     49  1.1  matt #include <machine/bus.h>
     50  1.1  matt #include <machine/intr.h>
     51  1.1  matt 
     52  1.1  matt #include <dev/pci/pcireg.h>
     53  1.1  matt #include <dev/pci/pcivar.h>
     54  1.1  matt #include <dev/pci/pciconf.h>
     55  1.1  matt #include <dev/marvell/gtreg.h>
     56  1.1  matt #include <dev/marvell/gtvar.h>
     57  1.1  matt #include <dev/marvell/gtintrreg.h>
     58  1.1  matt #include <dev/marvell/gtpcireg.h>
     59  1.1  matt #include <dev/marvell/gtpcivar.h>
     60  1.1  matt #include <dev/marvell/gtvar.h>
     61  1.1  matt 
     62  1.1  matt static int	gtpci_error_intr(void *);
     63  1.1  matt 
     64  1.5  matt static void	gtpci_bus_init(struct gtpci_chipset *);
     65  1.5  matt 
     66  1.1  matt static void	gtpci_bus_attach_hook(struct device *, struct device *,
     67  1.1  matt 		    struct pcibus_attach_args *);
     68  1.1  matt static int	gtpci_bus_maxdevs(pci_chipset_tag_t, int);
     69  1.1  matt 
     70  1.1  matt static const char *
     71  1.1  matt 		gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
     72  1.1  matt static const struct evcnt *
     73  1.1  matt 		gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
     74  1.1  matt static void	*gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
     75  1.1  matt 		    int, int (*)(void *), void *);
     76  1.1  matt static void	gtpci_intr_disestablish(pci_chipset_tag_t, void *);
     77  1.1  matt 
     78  1.1  matt #ifdef DEBUG
     79  1.1  matt int gtpci_debug = 0;
     80  1.1  matt #endif
     81  1.1  matt 
     82  1.1  matt struct gtpci_softc {
     83  1.1  matt 	struct device gtpci_dev;
     84  1.2  matt 	struct gtpci_chipset gtpci_gtpc;
     85  1.1  matt };
     86  1.1  matt 
     87  1.1  matt static int gtpci_cfprint(void *, const char *);
     88  1.1  matt static int gtpci_match(struct device *, struct cfdata *, void *);
     89  1.1  matt static void gtpci_attach(struct device *, struct device *, void *);
     90  1.1  matt 
     91  1.1  matt CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc),
     92  1.1  matt     gtpci_match, gtpci_attach, NULL, NULL);
     93  1.1  matt 
     94  1.1  matt extern struct cfdriver gtpci_cd;
     95  1.1  matt 
     96  1.1  matt const struct pci_chipset_functions gtpci_functions = {
     97  1.1  matt 	gtpci_bus_attach_hook,
     98  1.1  matt 	gtpci_bus_maxdevs,
     99  1.1  matt 	gtpci_md_bus_devorder,
    100  1.1  matt 
    101  1.1  matt 	gtpci_make_tag,
    102  1.1  matt 	gtpci_decompose_tag,
    103  1.1  matt 
    104  1.1  matt 	gtpci_conf_read,
    105  1.1  matt 	gtpci_conf_write,
    106  1.1  matt 	gtpci_md_conf_hook,
    107  1.1  matt 	gtpci_md_conf_interrupt,
    108  1.1  matt 
    109  1.1  matt 	gtpci_md_intr_map,
    110  1.1  matt 	gtpci_intr_string,
    111  1.1  matt 	gtpci_intr_evcnt,
    112  1.1  matt 	gtpci_intr_establish,
    113  1.1  matt 	gtpci_intr_disestablish
    114  1.1  matt };
    115  1.1  matt 
    116  1.6  matt static const int pci_irqs[2][3] = {
    117  1.6  matt     { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 },
    118  1.6  matt     { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 },
    119  1.6  matt };
    120  1.6  matt 
    121  1.6  matt static const struct pci_init {
    122  1.6  matt 	int bar_regno;
    123  1.6  matt 	u_int32_t bar_enable;
    124  1.6  matt  	bus_addr_t low_decode;
    125  1.6  matt 	bus_addr_t high_decode;
    126  1.6  matt 	bus_addr_t barsize;
    127  1.6  matt 	bus_addr_t accctl_high;
    128  1.6  matt 	bus_addr_t accctl_low;
    129  1.6  matt 	bus_addr_t accctl_top;
    130  1.6  matt } pci_initinfo[2][4] = {
    131  1.6  matt     	{
    132  1.6  matt 		{
    133  1.6  matt 			0x10,			PCI_BARE_SCS0En,
    134  1.6  matt 			GT_SCS0_Low_Decode,	GT_SCS0_High_Decode,
    135  1.6  matt 			PCI_SCS0_BAR_SIZE(0),
    136  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 0),
    137  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 0),
    138  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 0),
    139  1.6  matt 		}, {
    140  1.6  matt 			0x14,			PCI_BARE_SCS1En,
    141  1.6  matt 			GT_SCS1_Low_Decode,	GT_SCS1_High_Decode,
    142  1.6  matt 			PCI_SCS1_BAR_SIZE(0),
    143  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 1),
    144  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 1),
    145  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 1),
    146  1.6  matt 		}, {
    147  1.6  matt 			0x18,			PCI_BARE_SCS2En,
    148  1.6  matt 			GT_SCS2_Low_Decode,	GT_SCS2_High_Decode,
    149  1.6  matt 			PCI_SCS2_BAR_SIZE(0),
    150  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 2),
    151  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 2),
    152  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 2),
    153  1.6  matt 		}, {
    154  1.6  matt 			0x1c,			PCI_BARE_SCS3En,
    155  1.6  matt 			GT_SCS3_Low_Decode,	GT_SCS3_High_Decode,
    156  1.6  matt 			PCI_SCS3_BAR_SIZE(0),
    157  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(0, 3),
    158  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(0, 3),
    159  1.6  matt 			PCI_ACCESS_CONTROL_TOP(0, 3),
    160  1.6  matt 		},
    161  1.6  matt 	}, {
    162  1.6  matt 		{
    163  1.6  matt 			0x10,			PCI_BARE_SCS0En,
    164  1.6  matt 			GT_SCS0_Low_Decode,	GT_SCS0_High_Decode,
    165  1.6  matt 			PCI_SCS0_BAR_SIZE(1),
    166  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 0),
    167  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 0),
    168  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 0),
    169  1.6  matt 		}, {
    170  1.6  matt 			0x14,			PCI_BARE_SCS1En,
    171  1.6  matt 			GT_SCS1_Low_Decode,	GT_SCS1_High_Decode,
    172  1.6  matt 			PCI_SCS1_BAR_SIZE(1),
    173  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 1),
    174  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 1),
    175  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 1),
    176  1.6  matt 		}, {
    177  1.6  matt 			0x18,			PCI_BARE_SCS2En,
    178  1.6  matt 			GT_SCS2_Low_Decode,	GT_SCS2_High_Decode,
    179  1.6  matt 			PCI_SCS2_BAR_SIZE(1),
    180  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 2),
    181  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 2),
    182  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 2),
    183  1.6  matt 		}, {
    184  1.6  matt 			0x1c,			PCI_BARE_SCS3En,
    185  1.6  matt 			GT_SCS3_Low_Decode,	GT_SCS3_High_Decode,
    186  1.6  matt 			PCI_SCS3_BAR_SIZE(1),
    187  1.6  matt 			PCI_ACCESS_CONTROL_BASE_HIGH(1, 3),
    188  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(1, 3),
    189  1.6  matt 			PCI_ACCESS_CONTROL_TOP(1, 3),
    190  1.6  matt 		},
    191  1.6  matt 	}
    192  1.6  matt };
    193  1.6  matt 
    194  1.1  matt int
    195  1.1  matt gtpci_match(struct device *parent, struct cfdata *self, void *aux)
    196  1.1  matt {
    197  1.2  matt 	struct gt_softc * const gt = (struct gt_softc *) parent;
    198  1.2  matt 	struct gt_attach_args * const ga = aux;
    199  1.1  matt 
    200  1.2  matt 	return GT_PCIOK(gt, ga, &gtpci_cd);
    201  1.1  matt }
    202  1.1  matt 
    203  1.1  matt int
    204  1.1  matt gtpci_cfprint(void *aux, const char *pnp)
    205  1.1  matt {
    206  1.1  matt 	struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux;
    207  1.1  matt 
    208  1.1  matt 	if (pnp)
    209  1.2  matt 		aprint_normal("pci at %s", pnp);
    210  1.1  matt 
    211  1.2  matt 	aprint_normal(" bus %d", pba->pba_bus);
    212  1.1  matt 
    213  1.1  matt 	return (UNCONF);
    214  1.1  matt }
    215  1.1  matt 
    216  1.1  matt void
    217  1.1  matt gtpci_attach(struct device *parent, struct device *self, void *aux)
    218  1.1  matt {
    219  1.1  matt 	struct pcibus_attach_args pba;
    220  1.2  matt 	struct gt_attach_args * const ga = aux;
    221  1.2  matt 	struct gt_softc * const gt = (struct gt_softc *) parent;
    222  1.2  matt 	struct gtpci_softc * const gtp = (struct gtpci_softc *) self;
    223  1.2  matt 	struct gtpci_chipset * const gtpc = &gtp->gtpci_gtpc;
    224  1.2  matt 	struct pci_chipset * const pc = &gtpc->gtpc_pc;
    225  1.2  matt 	const int busno = ga->ga_unit;
    226  1.1  matt 	uint32_t data;
    227  1.1  matt 
    228  1.2  matt 	GT_PCIFOUND(gt, ga);
    229  1.1  matt 
    230  1.1  matt 	pc->pc_funcs = &gtpci_functions;
    231  1.1  matt 	pc->pc_parent = self;
    232  1.1  matt 
    233  1.2  matt 	gtpc->gtpc_busno = busno;
    234  1.2  matt 	gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno);
    235  1.2  matt 	gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno);
    236  1.2  matt 	gtpc->gtpc_syncreg = PCI_SYNC_REG(busno);
    237  1.2  matt 	gtpc->gtpc_gt_memt = ga->ga_memt;
    238  1.2  matt 	gtpc->gtpc_gt_memh = ga->ga_memh;
    239  1.1  matt 
    240  1.6  matt 	/*
    241  1.6  matt 	 * Let's find out where we are located.
    242  1.6  matt 	 */
    243  1.6  matt 	data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno));
    244  1.6  matt 	gtpc->gtpc_self = gtpci_make_tag(&gtpc->gtpc_pc,
    245  1.6  matt 		PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0);
    246  1.6  matt 
    247  1.6  matt 
    248  1.1  matt 	switch (busno) {
    249  1.1  matt 	case 0:
    250  1.2  matt 		gtpc->gtpc_io_bs = gt->gt_pci0_iot;
    251  1.2  matt 		gtpc->gtpc_mem_bs = gt->gt_pci0_memt;
    252  1.9   scw 		gtpc->gtpc_host = gt->gt_pci0_host;
    253  1.1  matt 		break;
    254  1.1  matt 	case 1:
    255  1.2  matt 		gtpc->gtpc_io_bs = gt->gt_pci1_iot;
    256  1.2  matt 		gtpc->gtpc_mem_bs = gt->gt_pci1_memt;
    257  1.9   scw 		gtpc->gtpc_host = gt->gt_pci1_host;
    258  1.1  matt 		break;
    259  1.1  matt 	default:
    260  1.1  matt 		break;
    261  1.1  matt 	}
    262  1.1  matt 
    263  1.2  matt 	/*
    264  1.2  matt 	 * If no bus_spaces exist, then it's been disabled.
    265  1.2  matt 	 */
    266  1.2  matt 	if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) {
    267  1.2  matt 		aprint_normal(": disabled\n");
    268  1.2  matt 		return;
    269  1.2  matt 	}
    270  1.2  matt 
    271  1.2  matt 	aprint_normal("\n");
    272  1.2  matt 
    273  1.6  matt 	/*
    274  1.6  matt 	 * clear any pre-existing error interrupt(s)
    275  1.6  matt 	 * clear latched pci error registers
    276  1.6  matt 	 * establish ISRs for PCI errors
    277  1.6  matt 	 * enable PCI error interrupts
    278  1.6  matt 	 */
    279  1.9   scw 	gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 0);
    280  1.6  matt 	gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0);
    281  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
    282  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
    283  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
    284  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
    285  1.6  matt 	(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
    286  1.9   scw 	if (gtpc->gtpc_host) {
    287  1.9   scw 		intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL,
    288  1.9   scw 		    IPL_GTERR, gtpci_error_intr, pc);
    289  1.9   scw 		intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL,
    290  1.9   scw 		    IPL_GTERR, gtpci_error_intr, pc);
    291  1.9   scw 		intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL,
    292  1.9   scw 		    IPL_GTERR, gtpci_error_intr, pc);
    293  1.9   scw 		aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n",
    294  1.9   scw 		    pc->pc_parent->dv_xname, "pci", busno,
    295  1.9   scw 		    intr_string(pci_irqs[gtpc->gtpc_busno][0]),
    296  1.9   scw 		    intr_string(pci_irqs[gtpc->gtpc_busno][1]),
    297  1.9   scw 		    intr_string(pci_irqs[gtpc->gtpc_busno][2]));
    298  1.9   scw 		gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno),
    299  1.9   scw 		    PCI_SERRMSK_ALL_ERRS);
    300  1.9   scw 	}
    301  1.6  matt 
    302  1.6  matt 	/*
    303  1.6  matt 	 * Fill in the pci_bus_attach_args
    304  1.6  matt 	 */
    305  1.1  matt 	pba.pba_pc = pc;
    306  1.1  matt 	pba.pba_bus = 0;
    307  1.1  matt 	pba.pba_busname = "pci";
    308  1.2  matt 	pba.pba_iot = gtpc->gtpc_io_bs;
    309  1.2  matt 	pba.pba_memt = gtpc->gtpc_mem_bs;
    310  1.1  matt 	pba.pba_dmat = gt->gt_dmat;
    311  1.2  matt 	pba.pba_flags = 0;
    312  1.2  matt 	if (pba.pba_iot != NULL)
    313  1.2  matt 		pba.pba_flags |= PCI_FLAGS_IO_ENABLED;
    314  1.2  matt 	if (pba.pba_memt != NULL)
    315  1.2  matt 		pba.pba_flags |= PCI_FLAGS_MEM_ENABLED;
    316  1.1  matt 
    317  1.2  matt 	data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
    318  1.1  matt 	if (data & PCI_CMD_MRdMul)
    319  1.1  matt 		pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
    320  1.1  matt 	if (data & PCI_CMD_MRdLine)
    321  1.1  matt 		pba.pba_flags |= PCI_FLAGS_MRL_OKAY;
    322  1.1  matt 	pba.pba_flags |= PCI_FLAGS_MWI_OKAY;
    323  1.1  matt 
    324  1.1  matt 	gt_watchdog_service();
    325  1.6  matt 	/*
    326  1.6  matt 	 * Configure the pci bus.
    327  1.6  matt 	 */
    328  1.1  matt 	config_found(self, &pba, gtpci_cfprint);
    329  1.1  matt 
    330  1.1  matt 	gt_watchdog_service();
    331  1.1  matt 
    332  1.1  matt }
    333  1.1  matt 
    334  1.1  matt void
    335  1.5  matt gtpci_bus_init(struct gtpci_chipset *gtpc)
    336  1.5  matt {
    337  1.6  matt 	const struct pci_init *pi;
    338  1.6  matt 	uint32_t data, datal, datah;
    339  1.5  matt 	pcireg_t pcidata;
    340  1.6  matt 	int i;
    341  1.5  matt 
    342  1.5  matt 	/*
    343  1.5  matt 	 * disable all BARs to start.
    344  1.5  matt 	 */
    345  1.5  matt 	gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
    346  1.5  matt 	    0xffffffff);
    347  1.5  matt 
    348  1.8   scw #ifndef GT_PCI0_EXT_ARBITER
    349  1.8   scw #define	GT_PCI0_EXT_ARBITER 0
    350  1.8   scw #endif
    351  1.8   scw #ifndef GT_PCI1_EXT_ARBITER
    352  1.8   scw #define	GT_PCI1_EXT_ARBITER 0
    353  1.8   scw #endif
    354  1.8   scw 
    355  1.9   scw 	if (gtpc->gtpc_host &&
    356  1.9   scw 	    ((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) ||
    357  1.9   scw 	     (!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) {
    358  1.8   scw 		/*
    359  1.8   scw 		 * Enable internal arbiter
    360  1.8   scw 		 */
    361  1.8   scw 		data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno));
    362  1.8   scw 		data |= PCI_ARBCTL_EN;
    363  1.8   scw 		gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data);
    364  1.8   scw 	} else {
    365  1.8   scw 		/*
    366  1.8   scw 		 * Make sure the internal arbiter is disabled
    367  1.8   scw 		 */
    368  1.8   scw 		gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0);
    369  1.8   scw 	}
    370  1.5  matt 
    371  1.5  matt 	/*
    372  1.5  matt 	 * Make the GT reflects reality.
    373  1.6  matt 	 * We always enable internal memory.
    374  1.5  matt 	 */
    375  1.9   scw 	if (gtpc->gtpc_host) {
    376  1.9   scw 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    377  1.9   scw 		    0x20) & 0xfff;
    378  1.9   scw 		gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20,
    379  1.9   scw 		    GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) |
    380  1.9   scw 		    pcidata);
    381  1.9   scw 	}
    382  1.6  matt 	data = PCI_BARE_IntMemEn;
    383  1.6  matt 
    384  1.7  matt 	for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++)
    385  1.6  matt 		gtpci_write(gtpc, pi->barsize, 0);
    386  1.5  matt 
    387  1.9   scw 	if (gtpc->gtpc_host) {
    388  1.9   scw 		/*
    389  1.9   scw 		 * Enable bus master access (needed for config access).
    390  1.9   scw 		 */
    391  1.9   scw 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    392  1.9   scw 		    PCI_COMMAND_STATUS_REG);
    393  1.9   scw 		pcidata |= PCI_COMMAND_MASTER_ENABLE;
    394  1.9   scw 		gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    395  1.9   scw 		    PCI_COMMAND_STATUS_REG, pcidata);
    396  1.9   scw 	}
    397  1.5  matt 
    398  1.5  matt 	/*
    399  1.5  matt 	 * Map each SCS BAR to correspond to each SDRAM decode register.
    400  1.5  matt 	 */
    401  1.7  matt 	for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) {
    402  1.6  matt 		datal = gtpci_read(gtpc, pi->low_decode);
    403  1.6  matt 		datah = gtpci_read(gtpc, pi->high_decode);
    404  1.6  matt 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    405  1.6  matt 		    pi->bar_regno);
    406  1.6  matt 		gtpci_write(gtpc, pi->accctl_high, 0);
    407  1.6  matt 		if (datal < datah) {
    408  1.6  matt 			datal &= 0xfff;
    409  1.6  matt 			pcidata &= 0xfff;
    410  1.6  matt 			pcidata |= datal << 20;
    411  1.6  matt 			data |= pi->bar_enable;
    412  1.6  matt 			datah -= datal;
    413  1.6  matt 			datal |= PCI_ACCCTLBASEL_PrefetchEn|
    414  1.6  matt 			    PCI_ACCCTLBASEL_RdPrefetch|
    415  1.6  matt 			    PCI_ACCCTLBASEL_RdLinePrefetch|
    416  1.6  matt 			    PCI_ACCCTLBASEL_RdMulPrefetch|
    417  1.6  matt 			    PCI_ACCCTLBASEL_WBurst_8_QW|
    418  1.6  matt 			    PCI_ACCCTLBASEL_PCISwap_NoSwap;
    419  1.6  matt 			gtpci_write(gtpc, pi->accctl_low, datal);
    420  1.6  matt 		} else {
    421  1.6  matt 			pcidata &= 0xfff;
    422  1.6  matt 			datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap;
    423  1.6  matt 			datah = 0;
    424  1.6  matt 		}
    425  1.6  matt 		gtpci_write(gtpc, pi->barsize,
    426  1.6  matt 		    datah ? ((datah << 20) | 0xff000) : 0);
    427  1.9   scw 		if (gtpc->gtpc_host) {
    428  1.9   scw 			gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    429  1.9   scw 			    pi->bar_regno, pcidata);
    430  1.9   scw 		}
    431  1.6  matt 		gtpci_write(gtpc, pi->accctl_low, datal);
    432  1.6  matt 		gtpci_write(gtpc, pi->accctl_top, datah);
    433  1.5  matt 	}
    434  1.5  matt 
    435  1.5  matt 	/*
    436  1.5  matt 	 * Now re-enable those BARs that are real.
    437  1.5  matt 	 */
    438  1.5  matt 	gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
    439  1.6  matt 	    ~data);
    440  1.5  matt 
    441  1.9   scw 	if (gtpc->gtpc_host) {
    442  1.9   scw 		/*
    443  1.9   scw 		 * Enable I/O and memory (bus master is already enabled) access.
    444  1.9   scw 		 */
    445  1.9   scw 		pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
    446  1.9   scw 		    PCI_COMMAND_STATUS_REG);
    447  1.9   scw 		pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
    448  1.9   scw 		gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
    449  1.9   scw 		    PCI_COMMAND_STATUS_REG, pcidata);
    450  1.9   scw 	}
    451  1.5  matt }
    452  1.5  matt 
    453  1.5  matt void
    454  1.1  matt gtpci_bus_attach_hook(struct device *parent, struct device *self,
    455  1.1  matt 	struct pcibus_attach_args *pba)
    456  1.1  matt {
    457  1.5  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc;
    458  1.5  matt 	uint32_t data;
    459  1.6  matt #if defined(DEBUG)
    460  1.1  matt 	pcitag_t tag;
    461  1.6  matt 	int bus, dev;
    462  1.6  matt 	int i;
    463  1.5  matt #endif
    464  1.1  matt 
    465  1.5  matt 	if (gtpc->gtpc_pc.pc_parent != parent)
    466  1.1  matt 		return;
    467  1.1  matt 
    468  1.2  matt 	data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
    469  1.2  matt 	aprint_normal(": id %d%s%s%s%s%s%s%s%s",
    470  1.1  matt 		PCI_MODE_PciID_GET(data),
    471  1.1  matt 		(data & PCI_MODE_Pci64) ? ", 64bit" : "",
    472  1.1  matt 		(data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "",
    473  1.1  matt 		(data & PCI_MODE_VPD) ? ", VPD" : "",
    474  1.1  matt 		(data & PCI_MODE_MSI) ? ", MSI" : "",
    475  1.1  matt 		(data & PCI_MODE_PMG) ? ", PMG" : "",
    476  1.1  matt 		(data & PCI_MODE_HotSwap) ? ", HotSwap" : "",
    477  1.1  matt 		(data & PCI_MODE_BIST) ? ", BIST" : "",
    478  1.1  matt 		(data & PCI_MODE_PRst) ? "" : ", PRst");
    479  1.1  matt 
    480  1.3  matt #if 0
    481  1.1  matt 	while ((data & PCI_MODE_PRst) == 0) {
    482  1.3  matt 		DELAY(10);
    483  1.2  matt 		data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
    484  1.3  matt 		aprint_normal(".");
    485  1.1  matt 	}
    486  1.3  matt #endif
    487  1.1  matt 
    488  1.5  matt 	gtpci_bus_init(gtpc);
    489  1.5  matt 	gtpci_bus_configure(gtpc);
    490  1.6  matt 
    491  1.6  matt 	data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
    492  1.6  matt 	if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) {
    493  1.6  matt 		aprint_normal("\n%s: ", self->dv_xname);
    494  1.6  matt 		if (data & PCI_CMD_MSwapEn) {
    495  1.6  matt 			switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) {
    496  1.6  matt 			case PCI_CMD_MWordSwap:
    497  1.6  matt 				aprint_normal(" mswap=w"); break;
    498  1.6  matt 			case PCI_CMD_MByteSwap:
    499  1.6  matt 				aprint_normal(" mswap=b"); break;
    500  1.6  matt 			case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap:
    501  1.6  matt 				aprint_normal(" mswap=b+w"); break;
    502  1.6  matt 			case 0:
    503  1.6  matt 				aprint_normal(" mswap=none"); break;
    504  1.6  matt 			}
    505  1.6  matt 		}
    506  1.6  matt 
    507  1.6  matt 		if (data & PCI_CMD_SSwapEn) {
    508  1.6  matt 			switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) {
    509  1.6  matt 			case PCI_CMD_SWordSwap:
    510  1.6  matt 				aprint_normal(" sswap=w"); break;
    511  1.6  matt 			case PCI_CMD_SByteSwap:
    512  1.6  matt 				aprint_normal(" sswap=b"); break;
    513  1.6  matt 			case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap:
    514  1.6  matt 				aprint_normal(" sswap=b+w"); break;
    515  1.6  matt 			case 0:
    516  1.6  matt 				aprint_normal(" sswap=none"); break;
    517  1.6  matt 			}
    518  1.6  matt 		}
    519  1.6  matt 	}
    520  1.6  matt 
    521  1.6  matt #if defined(DEBUG)
    522  1.6  matt 	if (gtpci_debug == 0)
    523  1.6  matt 		return;
    524  1.1  matt 
    525  1.2  matt 	data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno));
    526  1.2  matt 	aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data);
    527  1.1  matt 
    528  1.2  matt 	aprint_normal("\n%s: 0:0:0\n", self->dv_xname);
    529  1.2  matt 	aprint_normal("   %sSCS0=%#010x",
    530  1.1  matt 		(data & 1) ? "-" : "+",
    531  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x10));
    532  1.2  matt 	aprint_normal("/%#010x", gtpci_read(gtpc,
    533  1.6  matt 		PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno)));
    534  1.2  matt 	aprint_normal("  remap %#010x\n",
    535  1.2  matt 		gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    536  1.1  matt 
    537  1.2  matt 	aprint_normal("   %sSCS1=%#010x",
    538  1.1  matt 		(data & 2) ? "-" : "+",
    539  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x14));
    540  1.2  matt 	aprint_normal("/%#010x",
    541  1.6  matt 		gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno)));
    542  1.2  matt 	aprint_normal("  remap %#010x\n",
    543  1.2  matt 		gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    544  1.1  matt 
    545  1.2  matt 	aprint_normal("   %sSCS2=%#010x",
    546  1.1  matt 		(data & 4) ? "-" : "+",
    547  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x18));
    548  1.2  matt 	aprint_normal("/%#010x",
    549  1.6  matt 		gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno)));
    550  1.2  matt 	aprint_normal("  remap %#010x\n",
    551  1.2  matt 		gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    552  1.1  matt 
    553  1.2  matt 	aprint_normal("   %sSCS3=%#010x",
    554  1.1  matt 		(data & 8) ? "-" : "+",
    555  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x1c));
    556  1.2  matt 	aprint_normal("/%#010x",
    557  1.6  matt 		gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno)));
    558  1.2  matt 	aprint_normal("  remap %#010x\n",
    559  1.2  matt 		gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    560  1.1  matt 
    561  1.2  matt 	aprint_normal("   %sIMem=%#010x",
    562  1.1  matt 		(data & PCI_BARE_IntMemEn) ? "-" : "+",
    563  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20));
    564  1.2  matt 	aprint_normal("\n");
    565  1.2  matt 	aprint_normal("    %sIIO=%#010x",
    566  1.1  matt 		(data & PCI_BARE_IntIOEn) ? "-" : "+",
    567  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x24));
    568  1.2  matt 	aprint_normal("\n");
    569  1.6  matt 
    570  1.6  matt 	gtpci_decompose_tag(&gtpc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL);
    571  1.6  matt 	tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, dev, 1);
    572  1.2  matt 	aprint_normal("    %sCS0=%#010x",
    573  1.1  matt 		(data & PCI_BARE_CS0En) ? "-" : "+",
    574  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
    575  1.2  matt 	aprint_normal("/%#010x",
    576  1.6  matt 		gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno)));
    577  1.2  matt 	aprint_normal("  remap %#010x\n",
    578  1.2  matt 		gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    579  1.1  matt 
    580  1.2  matt 	aprint_normal("    %sCS1=%#010x",
    581  1.1  matt 		(data & PCI_BARE_CS1En) ? "-" : "+",
    582  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
    583  1.2  matt 	aprint_normal("/%#010x",
    584  1.6  matt 		gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno)));
    585  1.2  matt 	aprint_normal("  remap %#010x\n",
    586  1.2  matt 		gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    587  1.1  matt 
    588  1.2  matt 	aprint_normal("    %sCS2=%#010x",
    589  1.1  matt 		(data & PCI_BARE_CS2En) ? "-" : "+",
    590  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
    591  1.2  matt 	aprint_normal("/%#010x",
    592  1.6  matt 		gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno)));
    593  1.2  matt 	aprint_normal("  remap %#010x\n",
    594  1.2  matt 		gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    595  1.1  matt 
    596  1.2  matt 	aprint_normal("    %sCS3=%#010x",
    597  1.1  matt 		(data & PCI_BARE_CS3En) ? "-" : "+",
    598  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
    599  1.2  matt 	aprint_normal("/%#010x",
    600  1.6  matt 		gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno)));
    601  1.2  matt 	aprint_normal("  remap %#010x\n",
    602  1.2  matt 		gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    603  1.1  matt 
    604  1.2  matt 	aprint_normal(" %sBootCS=%#010x",
    605  1.1  matt 		(data & PCI_BARE_BootCSEn) ? "-" : "+",
    606  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x20));
    607  1.2  matt 	aprint_normal("/%#010x",
    608  1.6  matt 		gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno)));
    609  1.2  matt 	aprint_normal("  remap %#010x\n",
    610  1.2  matt 		gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno)));
    611  1.1  matt 
    612  1.6  matt 	tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, tag, 2);
    613  1.2  matt 	aprint_normal("  %sP2PM0=%#010x",
    614  1.1  matt 		(data & PCI_BARE_P2PMem0En) ? "-" : "+",
    615  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
    616  1.2  matt 	aprint_normal("/%#010x",
    617  1.6  matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno)));
    618  1.2  matt 	aprint_normal("  remap %#010x.%#010x\n",
    619  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
    620  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
    621  1.1  matt 
    622  1.2  matt 	aprint_normal("  %sP2PM1=%#010x",
    623  1.1  matt 		(data & PCI_BARE_P2PMem1En) ? "-" : "+",
    624  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
    625  1.2  matt 	aprint_normal("/%#010x",
    626  1.6  matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno)));
    627  1.2  matt 	aprint_normal("  remap %#010x.%#010x\n",
    628  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
    629  1.2  matt 		gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
    630  1.1  matt 
    631  1.2  matt 	aprint_normal("  %sP2PIO=%#010x",
    632  1.1  matt 		(data & PCI_BARE_P2PIOEn) ? "-" : "+",
    633  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
    634  1.2  matt 	aprint_normal("/%#010x",
    635  1.6  matt 		gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno)));
    636  1.2  matt 	aprint_normal("  remap %#010x\n",
    637  1.2  matt 		gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    638  1.1  matt 
    639  1.2  matt 	aprint_normal("    %sCPU=%#010x",
    640  1.1  matt 		(data & PCI_BARE_CPUEn) ? "-" : "+",
    641  1.6  matt 		gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
    642  1.2  matt 	aprint_normal("/%#010x",
    643  1.6  matt 		gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno)));
    644  1.2  matt 	aprint_normal("  remap %#010x\n",
    645  1.2  matt 		gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
    646  1.1  matt 
    647  1.1  matt 	for (i = 0; i < 8; i++) {
    648  1.2  matt 		aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i);
    649  1.6  matt 		data = gtpci_read(gtpc,
    650  1.6  matt 		    PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i));
    651  1.6  matt 		if (data)
    652  1.6  matt 			aprint_normal("base=0x%08x.", data);
    653  1.6  matt 		else
    654  1.6  matt 			aprint_normal("base=0x");
    655  1.6  matt 		data = gtpci_read(gtpc,
    656  1.6  matt 			PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i));
    657  1.6  matt 		printf("%08x cfg=0x%08x", data << 20, data & ~0xfff);
    658  1.6  matt 		aprint_normal(" top=0x%03x00000",
    659  1.6  matt 		    gtpci_read(gtpc,
    660  1.6  matt 			PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i)));
    661  1.1  matt 	}
    662  1.1  matt #endif
    663  1.1  matt }
    664  1.1  matt 
    665  1.1  matt static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings;
    666  1.1  matt 
    667  1.1  matt int
    668  1.1  matt gtpci_error_intr(void *arg)
    669  1.1  matt {
    670  1.1  matt 	pci_chipset_tag_t pc = arg;
    671  1.2  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    672  1.1  matt 	uint32_t cause, mask, errmask;
    673  1.1  matt 	u_int32_t alo, ahi, dlo, dhi, cmd;
    674  1.1  matt 	int i;
    675  1.1  matt 
    676  1.2  matt 	cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno));
    677  1.2  matt 	errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno));
    678  1.6  matt 	cause &= errmask | 0xf8000000;
    679  1.2  matt 	gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause);
    680  1.1  matt 	printf("%s: pci%d error: cause=%#x mask=%#x",
    681  1.2  matt 		pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask);
    682  1.6  matt 	if ((cause & 0xf8000000) == 0) {
    683  1.1  matt 		printf(" ?\n");
    684  1.1  matt 		return 0;
    685  1.1  matt 	}
    686  1.1  matt 
    687  1.1  matt 	for (i = 0, mask = 1; i <= 26; i++, mask += mask)
    688  1.1  matt 		if (mask & cause)
    689  1.1  matt 			printf(" %s", gtpci_error_strings[i]);
    690  1.1  matt 
    691  1.1  matt 	/*
    692  1.1  matt 	 * "no new data is latched until the PCI Error Low Address
    693  1.1  matt 	 * register is read.  This means that PCI Error Low Address
    694  1.1  matt 	 * register must be the last register read by the interrupt
    695  1.1  matt 	 * handler."
    696  1.1  matt 	 */
    697  1.2  matt 	dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
    698  1.2  matt 	dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
    699  1.2  matt 	cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
    700  1.2  matt 	ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
    701  1.2  matt 	alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
    702  1.6  matt 	printf("\n%s: pci%d error: %s cmd=%#x",
    703  1.2  matt 		pc->pc_parent->dv_xname, gtpc->gtpc_busno,
    704  1.6  matt 		gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd);
    705  1.6  matt 	if (dhi == 0)
    706  1.6  matt 		printf(" data=%08x", dlo);
    707  1.6  matt 	else
    708  1.6  matt 		printf(" data=%08x.%08x", dhi, dlo);
    709  1.6  matt 	if (ahi == 0)
    710  1.6  matt 		printf(" address=%08x\n", alo);
    711  1.6  matt 	else
    712  1.6  matt 		printf(" address=%08x.%08x\n", ahi, alo);
    713  1.1  matt 
    714  1.1  matt #if defined(DEBUG) && defined(DDB)
    715  1.6  matt 	if (gtpci_debug > 1)
    716  1.1  matt 		Debugger();
    717  1.1  matt #endif
    718  1.1  matt 	return 1;
    719  1.1  matt }
    720  1.1  matt 
    721  1.1  matt 
    722  1.1  matt #if 0
    723  1.1  matt void
    724  1.1  matt gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs,
    725  1.1  matt 	struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi)
    726  1.1  matt {
    727  1.1  matt 	/* See how I/O space is configured.  Read the base and top
    728  1.1  matt 	 * registers.
    729  1.1  matt 	 */
    730  1.1  matt 	paddr_t pbasel, pbaseh;
    731  1.1  matt 	uint32_t datal, datah;
    732  1.1  matt 
    733  1.2  matt 	datal = gtpci_read(gtpc, lo);
    734  1.2  matt 	datah = gtpci_read(gtpc, hi);
    735  1.1  matt 	pbasel = GT_LowAddr_GET(datal);
    736  1.1  matt 	pbaseh = GT_HighAddr_GET(datah);
    737  1.1  matt 	/*
    738  1.1  matt 	 * If the start is greater than the end, ignore the region.
    739  1.1  matt  	 */
    740  1.1  matt 	if (pbaseh < pbasel)
    741  1.1  matt 		return;
    742  1.1  matt 	if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase
    743  1.1  matt 	    && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) {
    744  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_vbase =
    745  1.1  matt 			gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask);
    746  1.1  matt 	}
    747  1.1  matt 	bs->bs_regions[bs->bs_nregion].br_pbase = pbasel;
    748  1.1  matt 	if (bs->bs_flags & _BUS_SPACE_RELATIVE) {
    749  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_start = 0;
    750  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel;
    751  1.1  matt 	} else {
    752  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_start = pbasel;
    753  1.1  matt 		bs->bs_regions[bs->bs_nregion].br_end = pbaseh;
    754  1.1  matt 	}
    755  1.1  matt 	bs->bs_nregion++;
    756  1.1  matt }
    757  1.1  matt #endif
    758  1.1  matt 
    759  1.1  matt /*
    760  1.1  matt  * Internal functions.
    761  1.1  matt  */
    762  1.1  matt int
    763  1.1  matt gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
    764  1.1  matt {
    765  1.1  matt 	return 32;
    766  1.1  matt }
    767  1.1  matt 
    768  1.1  matt pcitag_t
    769  1.1  matt gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno)
    770  1.1  matt {
    771  1.1  matt 	return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0);
    772  1.1  matt }
    773  1.1  matt 
    774  1.1  matt void
    775  1.1  matt gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
    776  1.1  matt 		    int *bp, int *dp, int *fp)
    777  1.1  matt {
    778  1.1  matt 	if (bp != NULL)
    779  1.1  matt 		*bp = PCI_CFG_GET_BUSNO(tag);
    780  1.1  matt 	if (dp != NULL)
    781  1.1  matt 		*dp = PCI_CFG_GET_DEVNO(tag);
    782  1.1  matt 	if (fp != NULL)
    783  1.1  matt 		*fp = PCI_CFG_GET_FUNCNO(tag);
    784  1.1  matt }
    785  1.1  matt 
    786  1.1  matt pcireg_t
    787  1.1  matt gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno)
    788  1.1  matt {
    789  1.2  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    790  1.1  matt #ifdef DIAGNOSTIC
    791  1.6  matt 	if ((regno & 3) || (regno & ~0xff))
    792  1.1  matt 		panic("gtpci_conf_read: bad regno %#x\n", regno);
    793  1.1  matt #endif
    794  1.2  matt 	gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
    795  1.2  matt 	return gtpci_read(gtpc, gtpc->gtpc_cfgdata);
    796  1.1  matt }
    797  1.1  matt 
    798  1.1  matt void
    799  1.1  matt gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data)
    800  1.1  matt {
    801  1.2  matt 	struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
    802  1.1  matt #ifdef DIAGNOSTIC
    803  1.6  matt 	if ((regno & 3) || (regno & ~0xff))
    804  1.1  matt 		panic("gtpci_conf_write: bad regno %#x\n", regno);
    805  1.1  matt #endif
    806  1.2  matt 	gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
    807  1.2  matt 	gtpci_write(gtpc, gtpc->gtpc_cfgdata, data);
    808  1.1  matt }
    809  1.1  matt 
    810  1.1  matt const char *
    811  1.1  matt gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih)
    812  1.1  matt {
    813  1.1  matt 	return intr_string(pih);
    814  1.1  matt }
    815  1.1  matt 
    816  1.1  matt const struct evcnt *
    817  1.1  matt gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih)
    818  1.1  matt {
    819  1.1  matt 	return intr_evcnt(pih);
    820  1.1  matt }
    821  1.1  matt 
    822  1.1  matt void *
    823  1.1  matt gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih,
    824  1.1  matt     int ipl, int (*handler)(void *), void *arg)
    825  1.1  matt {
    826  1.1  matt 	return intr_establish(pih, IST_LEVEL, ipl, handler, arg);
    827  1.1  matt }
    828  1.1  matt 
    829  1.1  matt void
    830  1.1  matt gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
    831  1.1  matt {
    832  1.1  matt 	intr_disestablish(cookie);
    833  1.1  matt }
    834