gtpci.c revision 1.13.12.1
1 /* $NetBSD: gtpci.c,v 1.13.12.1 2006/03/31 09:45:21 tron Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.13.12.1 2006/03/31 09:45:21 tron Exp $"); 42 43 #include "opt_marvell.h" 44 #include <sys/param.h> 45 #include <sys/device.h> 46 #include <sys/extent.h> 47 #include <sys/malloc.h> 48 #include <lib/libkern/libkern.h> 49 50 #define _BUS_SPACE_PRIVATE 51 #define _BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pciconf.h> 58 #include <dev/marvell/gtreg.h> 59 #include <dev/marvell/gtvar.h> 60 #include <dev/marvell/gtintrreg.h> 61 #include <dev/marvell/gtpcireg.h> 62 #include <dev/marvell/gtpcivar.h> 63 #include <dev/marvell/gtvar.h> 64 65 static int gtpci_error_intr(void *); 66 67 static void gtpci_bus_init(struct gtpci_chipset *); 68 69 static void gtpci_bus_attach_hook(struct device *, struct device *, 70 struct pcibus_attach_args *); 71 static int gtpci_bus_maxdevs(pci_chipset_tag_t, int); 72 73 static const char * 74 gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 75 static const struct evcnt * 76 gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t); 77 static void *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 78 int, int (*)(void *), void *); 79 static void gtpci_intr_disestablish(pci_chipset_tag_t, void *); 80 81 #ifdef DEBUG 82 int gtpci_debug = 0; 83 #endif 84 85 struct gtpci_softc { 86 struct device gtpci_dev; 87 struct gtpci_chipset gtpci_gtpc; 88 }; 89 90 static int gtpci_cfprint(void *, const char *); 91 static int gtpci_match(struct device *, struct cfdata *, void *); 92 static void gtpci_attach(struct device *, struct device *, void *); 93 94 CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc), 95 gtpci_match, gtpci_attach, NULL, NULL); 96 97 extern struct cfdriver gtpci_cd; 98 99 const struct pci_chipset_functions gtpci_functions = { 100 gtpci_bus_attach_hook, 101 gtpci_bus_maxdevs, 102 gtpci_md_bus_devorder, 103 104 gtpci_make_tag, 105 gtpci_decompose_tag, 106 107 gtpci_conf_read, 108 gtpci_conf_write, 109 gtpci_md_conf_hook, 110 gtpci_md_conf_interrupt, 111 112 gtpci_md_intr_map, 113 gtpci_intr_string, 114 gtpci_intr_evcnt, 115 gtpci_intr_establish, 116 gtpci_intr_disestablish 117 }; 118 119 static const int pci_irqs[2][3] = { 120 { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 }, 121 { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 }, 122 }; 123 124 static const struct pci_init { 125 int bar_regno; 126 u_int32_t bar_enable; 127 bus_addr_t low_decode; 128 bus_addr_t high_decode; 129 bus_addr_t barsize; 130 bus_addr_t accctl_high; 131 bus_addr_t accctl_low; 132 bus_addr_t accctl_top; 133 } pci_initinfo[2][4] = { 134 { 135 { 136 0x10, PCI_BARE_SCS0En, 137 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 138 PCI_SCS0_BAR_SIZE(0), 139 PCI_ACCESS_CONTROL_BASE_HIGH(0, 0), 140 PCI_ACCESS_CONTROL_BASE_LOW(0, 0), 141 PCI_ACCESS_CONTROL_TOP(0, 0), 142 }, { 143 0x14, PCI_BARE_SCS1En, 144 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 145 PCI_SCS1_BAR_SIZE(0), 146 PCI_ACCESS_CONTROL_BASE_HIGH(0, 1), 147 PCI_ACCESS_CONTROL_BASE_LOW(0, 1), 148 PCI_ACCESS_CONTROL_TOP(0, 1), 149 }, { 150 0x18, PCI_BARE_SCS2En, 151 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 152 PCI_SCS2_BAR_SIZE(0), 153 PCI_ACCESS_CONTROL_BASE_HIGH(0, 2), 154 PCI_ACCESS_CONTROL_BASE_LOW(0, 2), 155 PCI_ACCESS_CONTROL_TOP(0, 2), 156 }, { 157 0x1c, PCI_BARE_SCS3En, 158 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 159 PCI_SCS3_BAR_SIZE(0), 160 PCI_ACCESS_CONTROL_BASE_HIGH(0, 3), 161 PCI_ACCESS_CONTROL_BASE_LOW(0, 3), 162 PCI_ACCESS_CONTROL_TOP(0, 3), 163 }, 164 }, { 165 { 166 0x10, PCI_BARE_SCS0En, 167 GT_SCS0_Low_Decode, GT_SCS0_High_Decode, 168 PCI_SCS0_BAR_SIZE(1), 169 PCI_ACCESS_CONTROL_BASE_HIGH(1, 0), 170 PCI_ACCESS_CONTROL_BASE_LOW(1, 0), 171 PCI_ACCESS_CONTROL_TOP(1, 0), 172 }, { 173 0x14, PCI_BARE_SCS1En, 174 GT_SCS1_Low_Decode, GT_SCS1_High_Decode, 175 PCI_SCS1_BAR_SIZE(1), 176 PCI_ACCESS_CONTROL_BASE_HIGH(1, 1), 177 PCI_ACCESS_CONTROL_BASE_LOW(1, 1), 178 PCI_ACCESS_CONTROL_TOP(1, 1), 179 }, { 180 0x18, PCI_BARE_SCS2En, 181 GT_SCS2_Low_Decode, GT_SCS2_High_Decode, 182 PCI_SCS2_BAR_SIZE(1), 183 PCI_ACCESS_CONTROL_BASE_HIGH(1, 2), 184 PCI_ACCESS_CONTROL_BASE_LOW(1, 2), 185 PCI_ACCESS_CONTROL_TOP(1, 2), 186 }, { 187 0x1c, PCI_BARE_SCS3En, 188 GT_SCS3_Low_Decode, GT_SCS3_High_Decode, 189 PCI_SCS3_BAR_SIZE(1), 190 PCI_ACCESS_CONTROL_BASE_HIGH(1, 3), 191 PCI_ACCESS_CONTROL_BASE_LOW(1, 3), 192 PCI_ACCESS_CONTROL_TOP(1, 3), 193 }, 194 } 195 }; 196 197 int 198 gtpci_match(struct device *parent, struct cfdata *self, void *aux) 199 { 200 struct gt_softc * const gt = device_private(parent); 201 struct gt_attach_args * const ga = aux; 202 203 return GT_PCIOK(gt, ga, >pci_cd); 204 } 205 206 int 207 gtpci_cfprint(void *aux, const char *pnp) 208 { 209 struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux; 210 211 if (pnp) 212 aprint_normal("pci at %s", pnp); 213 214 aprint_normal(" bus %d", pba->pba_bus); 215 216 return (UNCONF); 217 } 218 219 void 220 gtpci_attach(struct device *parent, struct device *self, void *aux) 221 { 222 struct pcibus_attach_args pba; 223 struct gt_attach_args * const ga = aux; 224 struct gt_softc * const gt = device_private(parent); 225 struct gtpci_softc * const gtp = device_private(self); 226 struct gtpci_chipset * const gtpc = >p->gtpci_gtpc; 227 struct pci_chipset * const pc = >pc->gtpc_pc; 228 const int busno = ga->ga_unit; 229 uint32_t data; 230 231 GT_PCIFOUND(gt, ga); 232 233 pc->pc_funcs = >pci_functions; 234 pc->pc_parent = self; 235 236 gtpc->gtpc_busno = busno; 237 gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno); 238 gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno); 239 gtpc->gtpc_syncreg = PCI_SYNC_REG(busno); 240 gtpc->gtpc_gt_memt = ga->ga_memt; 241 gtpc->gtpc_gt_memh = ga->ga_memh; 242 243 /* 244 * Let's find out where we are located. 245 */ 246 data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno)); 247 gtpc->gtpc_self = gtpci_make_tag(>pc->gtpc_pc, 248 PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0); 249 250 251 switch (busno) { 252 case 0: 253 gtpc->gtpc_io_bs = gt->gt_pci0_iot; 254 gtpc->gtpc_mem_bs = gt->gt_pci0_memt; 255 gtpc->gtpc_host = gt->gt_pci0_host; 256 break; 257 case 1: 258 gtpc->gtpc_io_bs = gt->gt_pci1_iot; 259 gtpc->gtpc_mem_bs = gt->gt_pci1_memt; 260 gtpc->gtpc_host = gt->gt_pci1_host; 261 break; 262 default: 263 break; 264 } 265 266 /* 267 * If no bus_spaces exist, then it's been disabled. 268 */ 269 if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) { 270 aprint_normal(": disabled\n"); 271 return; 272 } 273 274 aprint_normal("\n"); 275 276 /* 277 * clear any pre-existing error interrupt(s) 278 * clear latched pci error registers 279 * establish ISRs for PCI errors 280 * enable PCI error interrupts 281 */ 282 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 0); 283 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0); 284 (void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 285 (void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 286 (void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 287 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 288 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 289 if (gtpc->gtpc_host) { 290 intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL, 291 IPL_GTERR, gtpci_error_intr, pc); 292 intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL, 293 IPL_GTERR, gtpci_error_intr, pc); 294 intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL, 295 IPL_GTERR, gtpci_error_intr, pc); 296 aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n", 297 pc->pc_parent->dv_xname, "pci", busno, 298 intr_string(pci_irqs[gtpc->gtpc_busno][0]), 299 intr_string(pci_irqs[gtpc->gtpc_busno][1]), 300 intr_string(pci_irqs[gtpc->gtpc_busno][2])); 301 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 302 PCI_SERRMSK_ALL_ERRS); 303 } 304 305 /* 306 * Fill in the pci_bus_attach_args 307 */ 308 pba.pba_pc = pc; 309 pba.pba_bus = 0; 310 pba.pba_iot = gtpc->gtpc_io_bs; 311 pba.pba_memt = gtpc->gtpc_mem_bs; 312 pba.pba_dmat = gt->gt_dmat; 313 pba.pba_flags = 0; 314 if (pba.pba_iot != NULL) 315 pba.pba_flags |= PCI_FLAGS_IO_ENABLED; 316 if (pba.pba_memt != NULL) 317 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED; 318 319 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 320 if (data & PCI_CMD_MRdMul) 321 pba.pba_flags |= PCI_FLAGS_MRM_OKAY; 322 if (data & PCI_CMD_MRdLine) 323 pba.pba_flags |= PCI_FLAGS_MRL_OKAY; 324 pba.pba_flags |= PCI_FLAGS_MWI_OKAY; 325 326 gt_watchdog_service(); 327 /* 328 * Configure the pci bus. 329 */ 330 config_found_ia(self, "pcibus", &pba, gtpci_cfprint); 331 332 gt_watchdog_service(); 333 334 } 335 336 void 337 gtpci_bus_init(struct gtpci_chipset *gtpc) 338 { 339 const struct pci_init *pi; 340 uint32_t data, datal, datah; 341 pcireg_t pcidata; 342 int i; 343 344 /* 345 * disable all BARs to start. 346 */ 347 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 348 0xffffffff); 349 350 #ifndef GT_PCI0_EXT_ARBITER 351 #define GT_PCI0_EXT_ARBITER 0 352 #endif 353 #ifndef GT_PCI1_EXT_ARBITER 354 #define GT_PCI1_EXT_ARBITER 0 355 #endif 356 357 if (gtpc->gtpc_host && 358 ((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) || 359 (!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) { 360 /* 361 * Enable internal arbiter 362 */ 363 data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno)); 364 data |= PCI_ARBCTL_EN; 365 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data); 366 } else { 367 /* 368 * Make sure the internal arbiter is disabled 369 */ 370 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0); 371 } 372 373 /* 374 * Make the GT reflects reality. 375 * We always enable internal memory. 376 */ 377 if (gtpc->gtpc_host) { 378 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 379 0x20) & 0xfff; 380 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 0x20, 381 GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) | 382 pcidata); 383 } 384 data = PCI_BARE_IntMemEn; 385 386 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) 387 gtpci_write(gtpc, pi->barsize, 0); 388 389 if (gtpc->gtpc_host) { 390 /* 391 * Enable bus master access (needed for config access). 392 */ 393 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 394 PCI_COMMAND_STATUS_REG); 395 pcidata |= PCI_COMMAND_MASTER_ENABLE; 396 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 397 PCI_COMMAND_STATUS_REG, pcidata); 398 } 399 400 /* 401 * Map each SCS BAR to correspond to each SDRAM decode register. 402 */ 403 for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) { 404 datal = gtpci_read(gtpc, pi->low_decode); 405 datah = gtpci_read(gtpc, pi->high_decode); 406 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 407 pi->bar_regno); 408 gtpci_write(gtpc, pi->accctl_high, 0); 409 if (datal < datah) { 410 datal &= 0xfff; 411 pcidata &= 0xfff; 412 pcidata |= datal << 20; 413 data |= pi->bar_enable; 414 datah -= datal; 415 datal |= PCI_ACCCTLBASEL_PrefetchEn| 416 PCI_ACCCTLBASEL_RdPrefetch| 417 PCI_ACCCTLBASEL_RdLinePrefetch| 418 PCI_ACCCTLBASEL_RdMulPrefetch| 419 PCI_ACCCTLBASEL_WBurst_8_QW| 420 PCI_ACCCTLBASEL_PCISwap_NoSwap; 421 gtpci_write(gtpc, pi->accctl_low, datal); 422 } else { 423 pcidata &= 0xfff; 424 datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap; 425 datah = 0; 426 } 427 gtpci_write(gtpc, pi->barsize, 428 datah ? ((datah << 20) | 0xff000) : 0); 429 if (gtpc->gtpc_host) { 430 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 431 pi->bar_regno, pcidata); 432 } 433 gtpci_write(gtpc, pi->accctl_low, datal); 434 gtpci_write(gtpc, pi->accctl_top, datah); 435 } 436 437 /* 438 * Now re-enable those BARs that are real. 439 */ 440 gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno), 441 ~data); 442 443 if (gtpc->gtpc_host) { 444 /* 445 * Enable I/O and memory (bus master is already enabled) access. 446 */ 447 pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 448 PCI_COMMAND_STATUS_REG); 449 pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE; 450 gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 451 PCI_COMMAND_STATUS_REG, pcidata); 452 } 453 } 454 455 void 456 gtpci_bus_attach_hook(struct device *parent, struct device *self, 457 struct pcibus_attach_args *pba) 458 { 459 struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc; 460 uint32_t data; 461 #if defined(DEBUG) 462 pcitag_t tag; 463 int bus, dev; 464 int i; 465 #endif 466 467 if (gtpc->gtpc_pc.pc_parent != parent) 468 return; 469 470 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 471 aprint_normal(": id %d%s%s%s%s%s%s%s%s", 472 PCI_MODE_PciID_GET(data), 473 (data & PCI_MODE_Pci64) ? ", 64bit" : "", 474 (data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "", 475 (data & PCI_MODE_VPD) ? ", VPD" : "", 476 (data & PCI_MODE_MSI) ? ", MSI" : "", 477 (data & PCI_MODE_PMG) ? ", PMG" : "", 478 (data & PCI_MODE_HotSwap) ? ", HotSwap" : "", 479 (data & PCI_MODE_BIST) ? ", BIST" : "", 480 (data & PCI_MODE_PRst) ? "" : ", PRst"); 481 482 #if 0 483 while ((data & PCI_MODE_PRst) == 0) { 484 DELAY(10); 485 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 486 aprint_normal("."); 487 } 488 #endif 489 490 gtpci_bus_init(gtpc); 491 gtpci_bus_configure(gtpc); 492 493 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 494 if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) { 495 aprint_normal("\n%s: ", self->dv_xname); 496 if (data & PCI_CMD_MSwapEn) { 497 switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) { 498 case PCI_CMD_MWordSwap: 499 aprint_normal(" mswap=w"); break; 500 case PCI_CMD_MByteSwap: 501 aprint_normal(" mswap=b"); break; 502 case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap: 503 aprint_normal(" mswap=b+w"); break; 504 case 0: 505 aprint_normal(" mswap=none"); break; 506 } 507 } 508 509 if (data & PCI_CMD_SSwapEn) { 510 switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) { 511 case PCI_CMD_SWordSwap: 512 aprint_normal(" sswap=w"); break; 513 case PCI_CMD_SByteSwap: 514 aprint_normal(" sswap=b"); break; 515 case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap: 516 aprint_normal(" sswap=b+w"); break; 517 case 0: 518 aprint_normal(" sswap=none"); break; 519 } 520 } 521 } 522 523 #if defined(DEBUG) 524 if (gtpci_debug == 0) 525 return; 526 527 data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno)); 528 aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data); 529 530 aprint_normal("\n%s: 0:0:0\n", self->dv_xname); 531 aprint_normal(" %sSCS0=%#010x", 532 (data & 1) ? "-" : "+", 533 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x10)); 534 aprint_normal("/%#010x", gtpci_read(gtpc, 535 PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno))); 536 aprint_normal(" remap %#010x\n", 537 gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 538 539 aprint_normal(" %sSCS1=%#010x", 540 (data & 2) ? "-" : "+", 541 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x14)); 542 aprint_normal("/%#010x", 543 gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno))); 544 aprint_normal(" remap %#010x\n", 545 gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 546 547 aprint_normal(" %sSCS2=%#010x", 548 (data & 4) ? "-" : "+", 549 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x18)); 550 aprint_normal("/%#010x", 551 gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno))); 552 aprint_normal(" remap %#010x\n", 553 gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 554 555 aprint_normal(" %sSCS3=%#010x", 556 (data & 8) ? "-" : "+", 557 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x1c)); 558 aprint_normal("/%#010x", 559 gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno))); 560 aprint_normal(" remap %#010x\n", 561 gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 562 563 aprint_normal(" %sIMem=%#010x", 564 (data & PCI_BARE_IntMemEn) ? "-" : "+", 565 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20)); 566 aprint_normal("\n"); 567 aprint_normal(" %sIIO=%#010x", 568 (data & PCI_BARE_IntIOEn) ? "-" : "+", 569 gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x24)); 570 aprint_normal("\n"); 571 572 gtpci_decompose_tag(>pc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL); 573 tag = gtpci_make_tag(>pc->gtpc_pc, bus, dev, 1); 574 aprint_normal(" %sCS0=%#010x", 575 (data & PCI_BARE_CS0En) ? "-" : "+", 576 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 577 aprint_normal("/%#010x", 578 gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno))); 579 aprint_normal(" remap %#010x\n", 580 gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 581 582 aprint_normal(" %sCS1=%#010x", 583 (data & PCI_BARE_CS1En) ? "-" : "+", 584 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 585 aprint_normal("/%#010x", 586 gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno))); 587 aprint_normal(" remap %#010x\n", 588 gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 589 590 aprint_normal(" %sCS2=%#010x", 591 (data & PCI_BARE_CS2En) ? "-" : "+", 592 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 593 aprint_normal("/%#010x", 594 gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno))); 595 aprint_normal(" remap %#010x\n", 596 gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 597 598 aprint_normal(" %sCS3=%#010x", 599 (data & PCI_BARE_CS3En) ? "-" : "+", 600 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 601 aprint_normal("/%#010x", 602 gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno))); 603 aprint_normal(" remap %#010x\n", 604 gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 605 606 aprint_normal(" %sBootCS=%#010x", 607 (data & PCI_BARE_BootCSEn) ? "-" : "+", 608 gtpci_conf_read(>pc->gtpc_pc, tag, 0x20)); 609 aprint_normal("/%#010x", 610 gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno))); 611 aprint_normal(" remap %#010x\n", 612 gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno))); 613 614 tag = gtpci_make_tag(>pc->gtpc_pc, bus, tag, 2); 615 aprint_normal(" %sP2PM0=%#010x", 616 (data & PCI_BARE_P2PMem0En) ? "-" : "+", 617 gtpci_conf_read(>pc->gtpc_pc, tag, 0x10)); 618 aprint_normal("/%#010x", 619 gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno))); 620 aprint_normal(" remap %#010x.%#010x\n", 621 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 622 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 623 624 aprint_normal(" %sP2PM1=%#010x", 625 (data & PCI_BARE_P2PMem1En) ? "-" : "+", 626 gtpci_conf_read(>pc->gtpc_pc, tag, 0x14)); 627 aprint_normal("/%#010x", 628 gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno))); 629 aprint_normal(" remap %#010x.%#010x\n", 630 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 631 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 632 633 aprint_normal(" %sP2PIO=%#010x", 634 (data & PCI_BARE_P2PIOEn) ? "-" : "+", 635 gtpci_conf_read(>pc->gtpc_pc, tag, 0x18)); 636 aprint_normal("/%#010x", 637 gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno))); 638 aprint_normal(" remap %#010x\n", 639 gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 640 641 aprint_normal(" %sCPU=%#010x", 642 (data & PCI_BARE_CPUEn) ? "-" : "+", 643 gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c)); 644 aprint_normal("/%#010x", 645 gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno))); 646 aprint_normal(" remap %#010x\n", 647 gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 648 649 for (i = 0; i < 8; i++) { 650 aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i); 651 data = gtpci_read(gtpc, 652 PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i)); 653 if (data) 654 aprint_normal("base=0x%08x.", data); 655 else 656 aprint_normal("base=0x"); 657 data = gtpci_read(gtpc, 658 PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i)); 659 printf("%08x cfg=0x%08x", data << 20, data & ~0xfff); 660 aprint_normal(" top=0x%03x00000", 661 gtpci_read(gtpc, 662 PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i))); 663 } 664 #endif 665 } 666 667 static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings; 668 669 int 670 gtpci_error_intr(void *arg) 671 { 672 pci_chipset_tag_t pc = arg; 673 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 674 uint32_t cause, mask, errmask; 675 u_int32_t alo, ahi, dlo, dhi, cmd; 676 int i; 677 678 cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno)); 679 errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno)); 680 cause &= errmask | 0xf8000000; 681 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause); 682 printf("%s: pci%d error: cause=%#x mask=%#x", 683 pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask); 684 if ((cause & 0xf8000000) == 0) { 685 printf(" ?\n"); 686 return 0; 687 } 688 689 for (i = 0, mask = 1; i <= 26; i++, mask += mask) 690 if (mask & cause) 691 printf(" %s", gtpci_error_strings[i]); 692 693 /* 694 * "no new data is latched until the PCI Error Low Address 695 * register is read. This means that PCI Error Low Address 696 * register must be the last register read by the interrupt 697 * handler." 698 */ 699 dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 700 dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 701 cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 702 ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 703 alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 704 printf("\n%s: pci%d error: %s cmd=%#x", 705 pc->pc_parent->dv_xname, gtpc->gtpc_busno, 706 gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd); 707 if (dhi == 0) 708 printf(" data=%08x", dlo); 709 else 710 printf(" data=%08x.%08x", dhi, dlo); 711 if (ahi == 0) 712 printf(" address=%08x\n", alo); 713 else 714 printf(" address=%08x.%08x\n", ahi, alo); 715 716 #if defined(DEBUG) && defined(DDB) 717 if (gtpci_debug > 1) 718 Debugger(); 719 #endif 720 return 1; 721 } 722 723 724 #if 0 725 void 726 gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs, 727 struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi) 728 { 729 /* See how I/O space is configured. Read the base and top 730 * registers. 731 */ 732 paddr_t pbasel, pbaseh; 733 uint32_t datal, datah; 734 735 datal = gtpci_read(gtpc, lo); 736 datah = gtpci_read(gtpc, hi); 737 pbasel = GT_LowAddr_GET(datal); 738 pbaseh = GT_HighAddr_GET(datah); 739 /* 740 * If the start is greater than the end, ignore the region. 741 */ 742 if (pbaseh < pbasel) 743 return; 744 if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase 745 && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) { 746 bs->bs_regions[bs->bs_nregion].br_vbase = 747 gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask); 748 } 749 bs->bs_regions[bs->bs_nregion].br_pbase = pbasel; 750 if (bs->bs_flags & _BUS_SPACE_RELATIVE) { 751 bs->bs_regions[bs->bs_nregion].br_start = 0; 752 bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel; 753 } else { 754 bs->bs_regions[bs->bs_nregion].br_start = pbasel; 755 bs->bs_regions[bs->bs_nregion].br_end = pbaseh; 756 } 757 bs->bs_nregion++; 758 } 759 #endif 760 761 /* 762 * Internal functions. 763 */ 764 int 765 gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 766 { 767 return 32; 768 } 769 770 pcitag_t 771 gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno) 772 { 773 return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0); 774 } 775 776 void 777 gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 778 int *bp, int *dp, int *fp) 779 { 780 if (bp != NULL) 781 *bp = PCI_CFG_GET_BUSNO(tag); 782 if (dp != NULL) 783 *dp = PCI_CFG_GET_DEVNO(tag); 784 if (fp != NULL) 785 *fp = PCI_CFG_GET_FUNCNO(tag); 786 } 787 788 pcireg_t 789 gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno) 790 { 791 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 792 #ifdef DIAGNOSTIC 793 if ((regno & 3) || (regno & ~0xff)) 794 panic("gtpci_conf_read: bad regno %#x\n", regno); 795 #endif 796 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 797 return gtpci_read(gtpc, gtpc->gtpc_cfgdata); 798 } 799 800 void 801 gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data) 802 { 803 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 804 #ifdef DIAGNOSTIC 805 if ((regno & 3) || (regno & ~0xff)) 806 panic("gtpci_conf_write: bad regno %#x\n", regno); 807 #endif 808 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 809 gtpci_write(gtpc, gtpc->gtpc_cfgdata, data); 810 } 811 812 const char * 813 gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih) 814 { 815 return intr_string(pih); 816 } 817 818 const struct evcnt * 819 gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih) 820 { 821 return intr_evcnt(pih); 822 } 823 824 void * 825 gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih, 826 int ipl, int (*handler)(void *), void *arg) 827 { 828 return intr_establish(pih, IST_LEVEL, ipl, handler, arg); 829 } 830 831 void 832 gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 833 { 834 intr_disestablish(cookie); 835 } 836
Indexes created Wed Oct 15 16:09:53 GMT 2025