gtpci.c revision 1.2
1 /* $NetBSD: gtpci.c,v 1.2 2003/03/16 07:05:34 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include "opt_marvell.h" 41 #include <sys/param.h> 42 #include <sys/device.h> 43 #include <sys/extent.h> 44 #include <sys/malloc.h> 45 #include <lib/libkern/libkern.h> 46 47 #define _BUS_SPACE_PRIVATE 48 #define _BUS_DMA_PRIVATE 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pciconf.h> 55 #include <dev/marvell/gtreg.h> 56 #include <dev/marvell/gtvar.h> 57 #include <dev/marvell/gtintrreg.h> 58 #include <dev/marvell/gtpcireg.h> 59 #include <dev/marvell/gtpcivar.h> 60 #include <dev/marvell/gtvar.h> 61 62 static int gtpci_error_intr(void *); 63 64 static void gtpci_bus_attach_hook(struct device *, struct device *, 65 struct pcibus_attach_args *); 66 static int gtpci_bus_maxdevs(pci_chipset_tag_t, int); 67 68 static const char * 69 gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 70 static const struct evcnt * 71 gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t); 72 static void *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 73 int, int (*)(void *), void *); 74 static void gtpci_intr_disestablish(pci_chipset_tag_t, void *); 75 76 #ifdef DEBUG 77 int gtpci_debug = 0; 78 #endif 79 80 struct gtpci_softc { 81 struct device gtpci_dev; 82 struct gtpci_chipset gtpci_gtpc; 83 }; 84 85 static int gtpci_cfprint(void *, const char *); 86 static int gtpci_match(struct device *, struct cfdata *, void *); 87 static void gtpci_attach(struct device *, struct device *, void *); 88 89 CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc), 90 gtpci_match, gtpci_attach, NULL, NULL); 91 92 extern struct cfdriver gtpci_cd; 93 94 static int gtpci_busmask; 95 96 const struct pci_chipset_functions gtpci_functions = { 97 gtpci_bus_attach_hook, 98 gtpci_bus_maxdevs, 99 gtpci_md_bus_devorder, 100 101 gtpci_make_tag, 102 gtpci_decompose_tag, 103 104 gtpci_conf_read, 105 gtpci_conf_write, 106 gtpci_md_conf_hook, 107 gtpci_md_conf_interrupt, 108 109 gtpci_md_intr_map, 110 gtpci_intr_string, 111 gtpci_intr_evcnt, 112 gtpci_intr_establish, 113 gtpci_intr_disestablish 114 }; 115 116 int 117 gtpci_match(struct device *parent, struct cfdata *self, void *aux) 118 { 119 struct gt_softc * const gt = (struct gt_softc *) parent; 120 struct gt_attach_args * const ga = aux; 121 122 return GT_PCIOK(gt, ga, >pci_cd); 123 } 124 125 int 126 gtpci_cfprint(void *aux, const char *pnp) 127 { 128 struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux; 129 130 if (pnp) 131 aprint_normal("pci at %s", pnp); 132 133 aprint_normal(" bus %d", pba->pba_bus); 134 135 return (UNCONF); 136 } 137 138 void 139 gtpci_attach(struct device *parent, struct device *self, void *aux) 140 { 141 struct pcibus_attach_args pba; 142 struct gt_attach_args * const ga = aux; 143 struct gt_softc * const gt = (struct gt_softc *) parent; 144 struct gtpci_softc * const gtp = (struct gtpci_softc *) self; 145 struct gtpci_chipset * const gtpc = >p->gtpci_gtpc; 146 struct pci_chipset * const pc = >pc->gtpc_pc; 147 const int busno = ga->ga_unit; 148 uint32_t data; 149 150 GT_PCIFOUND(gt, ga); 151 152 pc->pc_funcs = >pci_functions; 153 pc->pc_parent = self; 154 155 gtpc->gtpc_busno = busno; 156 gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno); 157 gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno); 158 gtpc->gtpc_syncreg = PCI_SYNC_REG(busno); 159 gtpc->gtpc_gt_memt = ga->ga_memt; 160 gtpc->gtpc_gt_memh = ga->ga_memh; 161 162 switch (busno) { 163 case 0: 164 gtpc->gtpc_io_bs = gt->gt_pci0_iot; 165 gtpc->gtpc_mem_bs = gt->gt_pci0_memt; 166 break; 167 case 1: 168 gtpc->gtpc_io_bs = gt->gt_pci1_iot; 169 gtpc->gtpc_mem_bs = gt->gt_pci1_memt; 170 break; 171 default: 172 break; 173 } 174 175 /* 176 * If no bus_spaces exist, then it's been disabled. 177 */ 178 if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) { 179 aprint_normal(": disabled\n"); 180 return; 181 } 182 183 aprint_normal("\n"); 184 185 pba.pba_pc = pc; 186 pba.pba_bus = 0; 187 pba.pba_busname = "pci"; 188 pba.pba_iot = gtpc->gtpc_io_bs; 189 pba.pba_memt = gtpc->gtpc_mem_bs; 190 pba.pba_dmat = gt->gt_dmat; 191 pba.pba_flags = 0; 192 if (pba.pba_iot != NULL) 193 pba.pba_flags |= PCI_FLAGS_IO_ENABLED; 194 if (pba.pba_memt != NULL) 195 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED; 196 197 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 198 if (data & PCI_CMD_MRdMul) 199 pba.pba_flags |= PCI_FLAGS_MRM_OKAY; 200 if (data & PCI_CMD_MRdLine) 201 pba.pba_flags |= PCI_FLAGS_MRL_OKAY; 202 pba.pba_flags |= PCI_FLAGS_MWI_OKAY; 203 204 gt_watchdog_service(); 205 206 config_found(self, &pba, gtpci_cfprint); 207 208 gt_watchdog_service(); 209 210 /* 211 * clear any pre-existing error interrupt(s) 212 * clear latched pci error registers 213 * establish ISRs for PCI errors 214 * enable PCI error interrupts 215 */ 216 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0); 217 (void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 218 (void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 219 (void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 220 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 221 (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 222 if (gtpc->gtpc_busno == 0) { 223 intr_establish(IRQ_PCI0_0, IST_LEVEL, IPL_GTERR, 224 gtpci_error_intr, pc); 225 intr_establish(IRQ_PCI0_1, IST_LEVEL, IPL_GTERR, 226 gtpci_error_intr, pc); 227 intr_establish(IRQ_PCI0_2, IST_LEVEL, IPL_GTERR, 228 gtpci_error_intr, pc); 229 aprint_normal("%s: %s%d error interrupts at irqs %d, %d, %d\n", 230 pc->pc_parent->dv_xname, "pci", busno, 231 IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2); 232 233 } else { 234 intr_establish(IRQ_PCI1_0, IST_LEVEL, IPL_GTERR, 235 gtpci_error_intr, pc); 236 intr_establish(IRQ_PCI1_1, IST_LEVEL, IPL_GTERR, 237 gtpci_error_intr, pc); 238 intr_establish(IRQ_PCI1_2, IST_LEVEL, IPL_GTERR, 239 gtpci_error_intr, pc); 240 aprint_normal("%s: %s%d error interrupts at irqs %d, %d, %d\n", 241 pc->pc_parent->dv_xname, "pci", busno, 242 IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2); 243 } 244 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), PCI_SERRMSK_ALL_ERRS); 245 246 gtpci_busmask |= (1 << busno); 247 } 248 249 void 250 gtpci_bus_attach_hook(struct device *parent, struct device *self, 251 struct pcibus_attach_args *pba) 252 { 253 pci_chipset_tag_t pc = pba->pba_pc; 254 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 255 pcitag_t tag; 256 uint32_t data; 257 int i; 258 259 if (pc->pc_parent != parent) 260 return; 261 262 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 263 aprint_normal(": id %d%s%s%s%s%s%s%s%s", 264 PCI_MODE_PciID_GET(data), 265 (data & PCI_MODE_Pci64) ? ", 64bit" : "", 266 (data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "", 267 (data & PCI_MODE_VPD) ? ", VPD" : "", 268 (data & PCI_MODE_MSI) ? ", MSI" : "", 269 (data & PCI_MODE_PMG) ? ", PMG" : "", 270 (data & PCI_MODE_HotSwap) ? ", HotSwap" : "", 271 (data & PCI_MODE_BIST) ? ", BIST" : "", 272 (data & PCI_MODE_PRst) ? "" : ", PRst"); 273 274 while ((data & PCI_MODE_PRst) == 0) { 275 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno)); 276 i = (i + 1) & 0x7ffffff; aprint_normal("."); 277 } 278 279 gtpci_config_bus(pc, gtpc->gtpc_busno); 280 281 tag = gtpci_make_tag(pc, 0, 0, 0); 282 data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno)); 283 aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data); 284 285 #if DEBUG 286 aprint_normal("\n%s: 0:0:0\n", self->dv_xname); 287 aprint_normal(" %sSCS0=%#010x", 288 (data & 1) ? "-" : "+", 289 gtpci_conf_read(pc, tag, 0x10)); 290 aprint_normal("/%#010x", gtpci_read(gtpc, 291 PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 292 aprint_normal(" remap %#010x\n", 293 gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 294 295 aprint_normal(" %sSCS1=%#010x", 296 (data & 2) ? "-" : "+", 297 gtpci_conf_read(pc, tag, 0x14)); 298 aprint_normal("/%#010x", 299 gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 300 aprint_normal(" remap %#010x\n", 301 gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 302 303 aprint_normal(" %sSCS2=%#010x", 304 (data & 4) ? "-" : "+", 305 gtpci_conf_read(pc, tag, 0x18)); 306 aprint_normal("/%#010x", 307 gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 308 aprint_normal(" remap %#010x\n", 309 gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 310 311 aprint_normal(" %sSCS3=%#010x", 312 (data & 8) ? "-" : "+", 313 gtpci_conf_read(pc, tag, 0x1c)); 314 aprint_normal("/%#010x", 315 gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 316 aprint_normal(" remap %#010x\n", 317 gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 318 319 aprint_normal(" %sIMem=%#010x", 320 (data & PCI_BARE_IntMemEn) ? "-" : "+", 321 gtpci_conf_read(pc, tag, 0x20)); 322 aprint_normal("\n"); 323 aprint_normal(" %sIIO=%#010x", 324 (data & PCI_BARE_IntIOEn) ? "-" : "+", 325 gtpci_conf_read(pc, tag, 0x24)); 326 aprint_normal("\n"); 327 tag = gtpci_make_tag(pc, 0, 0, 1); 328 aprint_normal(" %sCS0=%#010x", 329 (data & PCI_BARE_CS0En) ? "-" : "+", 330 gtpci_conf_read(pc, tag, 0x10)); 331 aprint_normal("/%#010x", 332 gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 333 aprint_normal(" remap %#010x\n", 334 gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 335 336 aprint_normal(" %sCS1=%#010x", 337 (data & PCI_BARE_CS1En) ? "-" : "+", 338 gtpci_conf_read(pc, tag, 0x14)); 339 aprint_normal("/%#010x", 340 gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 341 aprint_normal(" remap %#010x\n", 342 gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 343 344 aprint_normal(" %sCS2=%#010x", 345 (data & PCI_BARE_CS2En) ? "-" : "+", 346 gtpci_conf_read(pc, tag, 0x18)); 347 aprint_normal("/%#010x", 348 gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 349 aprint_normal(" remap %#010x\n", 350 gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 351 352 aprint_normal(" %sCS3=%#010x", 353 (data & PCI_BARE_CS3En) ? "-" : "+", 354 gtpci_conf_read(pc, tag, 0x1c)); 355 aprint_normal("/%#010x", 356 gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 357 aprint_normal(" remap %#010x\n", 358 gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 359 360 aprint_normal(" %sBootCS=%#010x", 361 (data & PCI_BARE_BootCSEn) ? "-" : "+", 362 gtpci_conf_read(pc, tag, 0x20)); 363 aprint_normal("/%#010x", 364 gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 365 aprint_normal(" remap %#010x\n", 366 gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno))); 367 368 tag = gtpci_make_tag(pc, 0, 0, 2); 369 aprint_normal(" %sP2PM0=%#010x", 370 (data & PCI_BARE_P2PMem0En) ? "-" : "+", 371 gtpci_conf_read(pc, tag, 0x10)); 372 aprint_normal("/%#010x", 373 gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 374 aprint_normal(" remap %#010x.%#010x\n", 375 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 376 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 377 378 aprint_normal(" %sP2PM1=%#010x", 379 (data & PCI_BARE_P2PMem1En) ? "-" : "+", 380 gtpci_conf_read(pc, tag, 0x14)); 381 aprint_normal("/%#010x", 382 gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 383 aprint_normal(" remap %#010x.%#010x\n", 384 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)), 385 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno))); 386 387 aprint_normal(" %sP2PIO=%#010x", 388 (data & PCI_BARE_P2PIOEn) ? "-" : "+", 389 gtpci_conf_read(pc, tag, 0x18)); 390 aprint_normal("/%#010x", 391 gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 392 aprint_normal(" remap %#010x\n", 393 gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 394 395 aprint_normal(" %sCPU=%#010x", 396 (data & PCI_BARE_CPUEn) ? "-" : "+", 397 gtpci_conf_read(pc, tag, 0x1c)); 398 aprint_normal("/%#010x", 399 gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno))+0x1000); 400 aprint_normal(" remap %#010x\n", 401 gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno))); 402 #endif 403 tag = gtpci_make_tag(pc, 0, 0, 0); 404 data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno)); 405 if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) { 406 407 aprint_normal("\n%s: ", self->dv_xname); 408 409 if (data & PCI_CMD_MSwapEn) { 410 switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) { 411 case PCI_CMD_MWordSwap: 412 aprint_normal(" mswap=w"); break; 413 case PCI_CMD_MByteSwap: 414 aprint_normal(" mswap=b"); break; 415 case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap: 416 aprint_normal(" mswap=b+w"); break; 417 case 0: 418 aprint_normal(" mswap=none"); break; 419 } 420 } 421 422 if (data & PCI_CMD_SSwapEn) { 423 switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) { 424 case PCI_CMD_SWordSwap: 425 aprint_normal(" sswap=w"); break; 426 case PCI_CMD_SByteSwap: 427 aprint_normal(" sswap=b"); break; 428 case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap: 429 aprint_normal(" sswap=b+w"); break; 430 case 0: 431 aprint_normal(" sswap=none"); break; 432 } 433 } 434 } 435 436 #if DEBUG 437 for (i = 0; i < 8; i++) { 438 aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i); 439 aprint_normal("base(hi=%#x,lo=%#x)=0x%08x.%03xxxxxx", 440 PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i), 441 PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i), 442 gtpci_read(gtpc, 443 PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i)), 444 gtpci_read(gtpc, 445 PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i)) & 0xfff); 446 aprint_normal(" cfg=%#x", 447 gtpci_read(gtpc, 448 PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i)) & ~0xfff); 449 aprint_normal(" top(%#x)=%#x", 450 PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i), 451 gtpci_read(gtpc, 452 PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i))); 453 } 454 #endif 455 456 #if 0 457 gtpci_write(gtpc, PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, 0), 0); 458 gtpci_write(gtpc, PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, 0), 459 0x01001000); 460 gtpci_write(gtpc, PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, 0), 461 0x00000020); 462 #endif 463 } 464 465 static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings; 466 467 int 468 gtpci_error_intr(void *arg) 469 { 470 pci_chipset_tag_t pc = arg; 471 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 472 uint32_t cause, mask, errmask; 473 u_int32_t alo, ahi, dlo, dhi, cmd; 474 int i; 475 476 cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno)); 477 errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno)); 478 cause &= (errmask | (0x1f << 27)); 479 gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause); 480 printf("%s: pci%d error: cause=%#x mask=%#x", 481 pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask); 482 if ((cause & ~(0x1f << 27)) == 0) { 483 printf(" ?\n"); 484 return 0; 485 } 486 487 for (i = 0, mask = 1; i <= 26; i++, mask += mask) 488 if (mask & cause) 489 printf(" %s", gtpci_error_strings[i]); 490 491 /* 492 * "no new data is latched until the PCI Error Low Address 493 * register is read. This means that PCI Error Low Address 494 * register must be the last register read by the interrupt 495 * handler." 496 */ 497 dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno)); 498 dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno)); 499 cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno)); 500 ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno)); 501 alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno)); 502 printf("\n%s: pci%d error: %s cmd %#x data %#x.%#x address=%#x.%#x\n", 503 pc->pc_parent->dv_xname, gtpc->gtpc_busno, 504 gtpci_error_strings[PCI_IC_SEL_GET(cause)], 505 cmd, dhi, dlo, ahi, alo); 506 507 #if defined(DEBUG) && defined(DDB) 508 if (gtpci_debug > 0) 509 Debugger(); 510 #endif 511 return 1; 512 } 513 514 515 #if 0 516 void 517 gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs, 518 struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi) 519 { 520 /* See how I/O space is configured. Read the base and top 521 * registers. 522 */ 523 paddr_t pbasel, pbaseh; 524 uint32_t datal, datah; 525 526 datal = gtpci_read(gtpc, lo); 527 datah = gtpci_read(gtpc, hi); 528 pbasel = GT_LowAddr_GET(datal); 529 pbaseh = GT_HighAddr_GET(datah); 530 /* 531 * If the start is greater than the end, ignore the region. 532 */ 533 if (pbaseh < pbasel) 534 return; 535 if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase 536 && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) { 537 bs->bs_regions[bs->bs_nregion].br_vbase = 538 gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask); 539 } 540 bs->bs_regions[bs->bs_nregion].br_pbase = pbasel; 541 if (bs->bs_flags & _BUS_SPACE_RELATIVE) { 542 bs->bs_regions[bs->bs_nregion].br_start = 0; 543 bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel; 544 } else { 545 bs->bs_regions[bs->bs_nregion].br_start = pbasel; 546 bs->bs_regions[bs->bs_nregion].br_end = pbaseh; 547 } 548 bs->bs_nregion++; 549 } 550 #endif 551 552 /* 553 * Internal functions. 554 */ 555 int 556 gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 557 { 558 return 32; 559 } 560 561 pcitag_t 562 gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno) 563 { 564 return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0); 565 } 566 567 void 568 gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 569 int *bp, int *dp, int *fp) 570 { 571 if (bp != NULL) 572 *bp = PCI_CFG_GET_BUSNO(tag); 573 if (dp != NULL) 574 *dp = PCI_CFG_GET_DEVNO(tag); 575 if (fp != NULL) 576 *fp = PCI_CFG_GET_FUNCNO(tag); 577 } 578 579 pcireg_t 580 gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno) 581 { 582 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 583 #ifdef DIAGNOSTIC 584 if ((regno & 3) || ((regno + 3) & ~0xff)) 585 panic("gtpci_conf_read: bad regno %#x\n", regno); 586 #endif 587 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 588 return gtpci_read(gtpc, gtpc->gtpc_cfgdata); 589 } 590 591 void 592 gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data) 593 { 594 struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc; 595 #ifdef DIAGNOSTIC 596 if ((regno & 3) || ((regno + 3) & ~0xff)) 597 panic("gtpci_conf_write: bad regno %#x\n", regno); 598 #endif 599 gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno); 600 gtpci_write(gtpc, gtpc->gtpc_cfgdata, data); 601 } 602 603 const char * 604 gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih) 605 { 606 return intr_string(pih); 607 } 608 609 const struct evcnt * 610 gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih) 611 { 612 return intr_evcnt(pih); 613 } 614 615 void * 616 gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih, 617 int ipl, int (*handler)(void *), void *arg) 618 { 619 return intr_establish(pih, IST_LEVEL, ipl, handler, arg); 620 } 621 622 void 623 gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 624 { 625 intr_disestablish(cookie); 626 } 627
Indexes created Wed Oct 22 13:09:56 GMT 2025