gtpci.c revision 1.23
1 /* $NetBSD: gtpci.c,v 1.23 2010/06/02 06:24:59 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008, 2009 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.23 2010/06/02 06:24:59 kiyohara Exp $"); 30 31 #include "opt_pci.h" 32 #include "pci.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 41 #include <prop/proplib.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pciconf.h> 46 47 #include <dev/marvell/gtpcireg.h> 48 #include <dev/marvell/gtpcivar.h> 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 52 #include <machine/pci_machdep.h> 53 54 #include "locators.h" 55 56 57 #define GTPCI_READ(sc, r) \ 58 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit)) 59 #define GTPCI_WRITE(sc, r, v) \ 60 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit), (v)) 61 #define GTPCI_WRITE_AC(sc, r, n, v) \ 62 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit, (n)), (v)) 63 64 65 static int gtpci_match(device_t, struct cfdata *, void *); 66 static void gtpci_attach(device_t, device_t, void *); 67 68 static void gtpci_init(struct gtpci_softc *); 69 static void gtpci_barinit(struct gtpci_softc *); 70 static void gtpci_protinit(struct gtpci_softc *); 71 #if NPCI > 0 72 static void gtpci_pci_config(struct gtpci_softc *, bus_space_tag_t, 73 bus_space_tag_t, bus_dma_tag_t, pci_chipset_tag_t, 74 u_long, u_long, u_long, u_long, int); 75 #endif 76 77 78 CFATTACH_DECL_NEW(gtpci_gt, sizeof(struct gtpci_softc), 79 gtpci_match, gtpci_attach, NULL, NULL); 80 CFATTACH_DECL_NEW(gtpci_mbus, sizeof(struct gtpci_softc), 81 gtpci_match, gtpci_attach, NULL, NULL); 82 83 84 /* ARGSUSED */ 85 static int 86 gtpci_match(device_t parent, struct cfdata *match, void *aux) 87 { 88 struct marvell_attach_args *mva = aux; 89 90 if (strcmp(mva->mva_name, match->cf_name) != 0) 91 return 0; 92 93 switch (mva->mva_model) { 94 case MARVELL_DISCOVERY: 95 case MARVELL_DISCOVERY_II: 96 case MARVELL_DISCOVERY_III: 97 #if 0 /* XXXXX */ 98 case MARVELL_DISCOVERY_LT: 99 case MARVELL_DISCOVERY_V: 100 case MARVELL_DISCOVERY_VI: 101 #endif 102 if (mva->mva_unit == GTCF_UNIT_DEFAULT || 103 mva->mva_offset != GTCF_OFFSET_DEFAULT) 104 return 0; 105 break; 106 107 case MARVELL_ORION_1_88F5180N: 108 case MARVELL_ORION_1_88F5181: 109 case MARVELL_ORION_1_88F5182: 110 case MARVELL_ORION_2_88F5281: 111 case MARVELL_ORION_1_88W8660: 112 if (mva->mva_offset == GTCF_OFFSET_DEFAULT) 113 return 0; 114 mva->mva_unit = 0; /* unit 0 only */ 115 break; 116 117 default: 118 return 0; 119 } 120 121 mva->mva_size = GTPCI_SIZE; 122 return 1; 123 } 124 125 /* ARGSUSED */ 126 static void 127 gtpci_attach(device_t parent, device_t self, void *aux) 128 { 129 struct gtpci_softc *sc = device_private(self); 130 struct marvell_attach_args *mva = aux; 131 #if NPCI > 0 132 prop_dictionary_t dict = device_properties(self); 133 prop_object_t pc, iot, memt; 134 prop_array_t int2gpp; 135 prop_object_t gpp; 136 pci_chipset_tag_t gtpci_chipset; 137 bus_space_tag_t gtpci_io_bs_tag, gtpci_mem_bs_tag; 138 uint64_t iostart = 0, ioend = 0, memstart = 0, memend = 0; 139 int cl_size = 0, intr; 140 #endif 141 142 aprint_normal(": Marvell PCI Interface\n"); 143 aprint_naive("\n"); 144 145 #if NPCI > 0 146 iot = prop_dictionary_get(dict, "io-bus-tag"); 147 if (iot == NULL) 148 aprint_error_dev(self, "no io-bus-tag property\n"); 149 KASSERT(prop_object_type(iot) == PROP_TYPE_DATA); 150 gtpci_io_bs_tag = __UNCONST(prop_data_data_nocopy(iot)); 151 memt = prop_dictionary_get(dict, "mem-bus-tag"); 152 if (memt == NULL) 153 aprint_error_dev(self, "no mem-bus-tag property\n"); 154 KASSERT(prop_object_type(memt) == PROP_TYPE_DATA); 155 gtpci_mem_bs_tag = __UNCONST(prop_data_data_nocopy(memt)); 156 pc = prop_dictionary_get(dict, "pci-chipset"); 157 if (pc == NULL) { 158 aprint_error_dev(self, "no pci-chipset property\n"); 159 return; 160 } 161 KASSERT(prop_object_type(pc) == PROP_TYPE_DATA); 162 gtpci_chipset = __UNCONST(prop_data_data_nocopy(pc)); 163 #ifdef PCI_NETBSD_CONFIGURE 164 if (!prop_dictionary_get_uint64(dict, "iostart", &iostart)) { 165 aprint_error_dev(self, "no iostart property\n"); 166 return; 167 } 168 if (!prop_dictionary_get_uint64(dict, "ioend", &ioend)) { 169 aprint_error_dev(self, "no ioend property\n"); 170 return; 171 } 172 if (!prop_dictionary_get_uint64(dict, "memstart", &memstart)) { 173 aprint_error_dev(self, "no memstart property\n"); 174 return; 175 } 176 if (!prop_dictionary_get_uint64(dict, "memend", &memend)) { 177 aprint_error_dev(self, "no memend property\n"); 178 return; 179 } 180 if (!prop_dictionary_get_uint32(dict, "cache-line-size", &cl_size)) { 181 aprint_error_dev(self, "no cache-line-size property\n"); 182 return; 183 } 184 #endif 185 #endif 186 187 sc->sc_dev = self; 188 sc->sc_model = mva->mva_model; 189 sc->sc_rev = mva->mva_revision; 190 sc->sc_unit = mva->mva_unit; 191 sc->sc_iot = mva->mva_iot; 192 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 193 (mva->mva_offset != GTCF_OFFSET_DEFAULT) ? mva->mva_offset : 0, 194 mva->mva_size, &sc->sc_ioh)) { 195 aprint_error_dev(self, "can't map registers\n"); 196 return; 197 } 198 sc->sc_pc = gtpci_chipset; 199 gtpci_init(sc); 200 201 #if NPCI > 0 202 int2gpp = prop_dictionary_get(dict, "int2gpp"); 203 if (int2gpp != NULL) { 204 if (prop_object_type(int2gpp) != PROP_TYPE_ARRAY) { 205 aprint_error_dev(self, "int2gpp not an array\n"); 206 return; 207 } 208 aprint_normal_dev(self, "use intrrupt pin:"); 209 for (intr = PCI_INTERRUPT_PIN_A; 210 intr <= PCI_INTERRUPT_PIN_D && 211 intr < prop_array_count(int2gpp); 212 intr++) { 213 gpp = prop_array_get(int2gpp, intr); 214 if (prop_object_type(gpp) != PROP_TYPE_NUMBER) { 215 aprint_error_dev(self, 216 "int2gpp[%d] not an number\n", intr); 217 return; 218 } 219 aprint_normal(" %d", 220 (int)prop_number_integer_value(gpp)); 221 } 222 aprint_normal("\n"); 223 } 224 225 gtpci_pci_config(sc, gtpci_io_bs_tag, gtpci_mem_bs_tag, mva->mva_dmat, 226 gtpci_chipset, iostart, ioend, memstart, memend, cl_size); 227 #endif 228 } 229 230 static void 231 gtpci_init(struct gtpci_softc *sc) 232 { 233 uint32_t reg; 234 235 /* First, all disable. Also WA CQ 4382 (bit15 must set 1)*/ 236 GTPCI_WRITE(sc, GTPCI_BARE, GTPCI_BARE_ALLDISABLE | (1 << 15)); 237 238 /* Enable Internal Arbiter */ 239 reg = GTPCI_READ(sc, GTPCI_AC); 240 reg |= GTPCI_AC_EN; 241 GTPCI_WRITE(sc, GTPCI_AC, reg); 242 243 gtpci_barinit(sc); 244 gtpci_protinit(sc); 245 246 reg = GTPCI_READ(sc, GTPCI_ADC); 247 reg |= GTPCI_ADC_REMAPWRDIS; 248 GTPCI_WRITE(sc, GTPCI_ADC, reg); 249 250 /* enable CPU-2-PCI ordering */ 251 reg = GTPCI_READ(sc, GTPCI_C); 252 reg |= GTPCI_C_CPU2PCIORDERING; 253 GTPCI_WRITE(sc, GTPCI_C, reg); 254 } 255 256 static void 257 gtpci_barinit(struct gtpci_softc *sc) 258 { 259 static const struct { 260 int tag; 261 int bars[2]; /* BAR Size registers */ 262 int bare; /* Bits of Base Address Registers Enable */ 263 int func; 264 int balow; 265 int bahigh; 266 } maps[] = { 267 { MARVELL_TAG_SDRAM_CS0, 268 { GTPCI_CS0BARS(0), GTPCI_CS0BARS(1) }, 269 GTPCI_BARE_CS0EN, 0, 0x10, 0x14 }, 270 { MARVELL_TAG_SDRAM_CS1, 271 { GTPCI_CS1BARS(0), GTPCI_CS1BARS(1) }, 272 GTPCI_BARE_CS1EN, 0, 0x18, 0x1c }, 273 { MARVELL_TAG_SDRAM_CS2, 274 { GTPCI_CS2BARS(0), GTPCI_CS2BARS(1) }, 275 GTPCI_BARE_CS2EN, 1, 0x10, 0x14 }, 276 { MARVELL_TAG_SDRAM_CS3, 277 { GTPCI_CS3BARS(0), GTPCI_CS3BARS(1) }, 278 GTPCI_BARE_CS3EN, 1, 0x18, 0x1c }, 279 #if 0 280 { ORION_TARGETID_INTERNALREG, 281 { -1, -1 }, 282 GTPCI_BARE_INTMEMEN, 0, 0x20, 0x24 }, 283 284 { ORION_TARGETID_DEVICE_CS0, 285 { GTPCI_DCS0BARS(0), GTPCI_DCS0BARS(1) }, 286 GTPCI_BARE_DEVCS0EN, 2, 0x10, 0x14 }, 287 { ORION_TARGETID_DEVICE_CS1, 288 { GTPCI_DCS1BARS(0), GTPCI_DCS1BARS(1) }, 289 GTPCI_BARE_DEVCS1EN, 2, 0x18, 0x1c }, 290 { ORION_TARGETID_DEVICE_CS2, 291 { GTPCI_DCS2BARS(0), GTPCI_DCS2BARS(1) }, 292 GTPCI_BARE_DEVCS2EN, 2, 0x20, 0x24 }, 293 { ORION_TARGETID_DEVICE_BOOTCS, 294 { GTPCI_BCSBARS(0), GTPCI_BCSBARS(1) }, 295 GTPCI_BARE_BOOTCSEN, 3, 0x18, 0x1c }, 296 { P2P Mem0 BAR, 297 { GTPCI_P2PM0BARS(0), GTPCI_P2PM0BARS(1) }, 298 GTPCI_BARE_P2PMEM0EN, 4, 0x10, 0x14 }, 299 { P2P I/O BAR, 300 { GTPCI_P2PIOBARS(0), GTPCI_P2PIOBARS(1) }, 301 GTPCI_BARE_P2PIO0EN, 4, 0x20, 0x24 }, 302 { Expansion ROM BAR, 303 { GTPCI_EROMBARS(0), GTPCI_EROMBARS(1) }, 304 0, }, 305 #endif 306 307 { MARVELL_TAG_UNDEFINED, 308 { -1, -1 }, 309 -1, -1, 0x00, 0x00 }, 310 }; 311 device_t pdev = device_parent(sc->sc_dev); 312 uint64_t base; 313 uint32_t p2pc, size, bare; 314 int map, bus, dev, rv; 315 316 p2pc = GTPCI_READ(sc, GTPCI_P2PC); 317 bus = GTPCI_P2PC_BUSNUMBER(p2pc); 318 dev = GTPCI_P2PC_DEVNUM(p2pc); 319 320 bare = GTPCI_BARE_ALLDISABLE; 321 for (map = 0; maps[map].tag != MARVELL_TAG_UNDEFINED; map++) { 322 rv = marvell_winparams_by_tag(pdev, maps[map].tag, NULL, NULL, 323 &base, &size); 324 if (rv != 0 || size == 0) 325 continue; 326 327 if (maps[map].bars[sc->sc_unit] != -1) 328 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 329 maps[map].bars[sc->sc_unit], GTPCI_BARSIZE(size)); 330 bare &= ~maps[map].bare; 331 332 #if 0 /* shall move to pchb(4)? */ 333 if (maps[map].func != -1) { 334 pcitag_t tag; 335 pcireg_t reg; 336 337 tag = gtpci_make_tag(NULL, bus, dev, maps[map].func); 338 reg = gtpci_conf_read(sc, tag, maps[map].balow); 339 reg &= ~GTPCI_BARLOW_MASK; 340 reg |= GTPCI_BARLOW_BASE(base); 341 gtpci_conf_write(sc, tag, maps[map].balow, reg); 342 reg = gtpci_conf_read(sc, tag, maps[map].bahigh); 343 reg = (base >> 16) >> 16; 344 gtpci_conf_write(sc, tag, maps[map].bahigh, reg); 345 } 346 #endif 347 } 348 GTPCI_WRITE(sc, GTPCI_BARE, bare); 349 } 350 351 static void 352 gtpci_protinit(struct gtpci_softc *sc) 353 { 354 enum { 355 gt64260 = 0, 356 mv64360, 357 soc, 358 }; 359 const struct gtpci_prot { 360 uint32_t acbl_flags; 361 uint32_t acbl_base_rshift; 362 uint32_t acs_flags; 363 uint32_t acs_size_rshift; 364 } gtpci_prots[] = { 365 { /* GT64260 */ 366 #if 0 367 GTPCI_GT64260_ACBL_PCISWAP_NOSWAP | 368 GTPCI_GT64260_ACBL_WBURST_4_QW | 369 GTPCI_GT64260_ACBL_RDMULPREFETCH | 370 GTPCI_GT64260_ACBL_RDLINEPREFETCH | 371 GTPCI_GT64260_ACBL_RDPREFETCH | 372 GTPCI_GT64260_ACBL_DREADEN, 373 #else 374 GTPCI_GT64260_ACBL_PCISWAP_NOSWAP | 375 GTPCI_GT64260_ACBL_WBURST_8_QW | 376 GTPCI_GT64260_ACBL_RDMULPREFETCH | 377 GTPCI_GT64260_ACBL_RDLINEPREFETCH | 378 GTPCI_GT64260_ACBL_RDPREFETCH | 379 GTPCI_GT64260_ACBL_PREFETCHEN, 380 #endif 381 20, 382 0, 383 20 384 }, 385 { /* MV64360 and after */ 386 GTPCI_ACBL_RDSIZE_256BYTE | 387 GTPCI_ACBL_RDMBURST_128BYTE | 388 GTPCI_ACBL_PCISWAP_NOSWAP | 389 GTPCI_ACBL_SNOOP_NONE | 390 GTPCI_ACBL_EN, 391 0, 392 0, 393 0 394 }, 395 { /* Orion */ 396 GTPCI_ACBL_RDSIZE_256BYTE | 397 GTPCI_ACBL_RDMBURST_128BYTE | 398 GTPCI_ACBL_PCISWAP_BYTESWAP, 399 0, 400 GTPCI_ACS_WRMBURST_128BYTE, 401 0 402 }, 403 }; 404 const uint32_t prot_tags[] = { 405 MARVELL_TAG_SDRAM_CS0, 406 MARVELL_TAG_SDRAM_CS1, 407 MARVELL_TAG_SDRAM_CS2, 408 MARVELL_TAG_SDRAM_CS3, 409 MARVELL_TAG_UNDEFINED 410 }; 411 device_t pdev = device_parent(sc->sc_dev); 412 uint64_t acbase, base; 413 uint32_t acsize, size; 414 int acbl_base_rshift, acbl_flags, acs_size_rshift, acs_flags; 415 int prot, rv, p, t; 416 417 switch (sc->sc_model) { 418 case MARVELL_DISCOVERY: 419 p = gt64260; 420 break; 421 422 case MARVELL_DISCOVERY_II: 423 case MARVELL_DISCOVERY_III: 424 #if 0 425 case MARVELL_DISCOVERY_LT: 426 case MARVELL_DISCOVERY_V: 427 case MARVELL_DISCOVERY_VI: 428 #endif 429 p = mv64360; 430 break; 431 432 default: 433 p = soc; 434 break; 435 } 436 acbl_base_rshift = gtpci_prots[p].acbl_base_rshift; 437 acbl_flags = gtpci_prots[p].acbl_flags; 438 acs_size_rshift = gtpci_prots[p].acs_size_rshift; 439 acs_flags = gtpci_prots[p].acs_flags; 440 441 t = 0; 442 for (prot = 0; prot < GTPCI_NPCIAC; prot++) { 443 acbase = acsize = 0; 444 445 for ( ; prot_tags[t] != MARVELL_TAG_UNDEFINED; t++) { 446 rv = marvell_winparams_by_tag(pdev, prot_tags[t], 447 NULL, NULL, &base, &size); 448 if (rv != 0 || size == 0) 449 continue; 450 451 if (acsize == 0 || base + size == acbase) 452 acbase = base; 453 else if (acbase + acsize != base) 454 break; 455 acsize += size; 456 } 457 458 if (acsize != 0) { 459 GTPCI_WRITE_AC(sc, GTPCI_ACBL, prot, 460 ((acbase & 0xffffffff) >> acbl_base_rshift) | 461 acbl_flags); 462 GTPCI_WRITE_AC(sc, GTPCI_ACBH, prot, 463 (acbase >> 32) & 0xffffffff); 464 GTPCI_WRITE_AC(sc, GTPCI_ACS, prot, 465 ((acsize - 1) >> acs_size_rshift) | acs_flags); 466 } else { 467 GTPCI_WRITE_AC(sc, GTPCI_ACBL, prot, 0); 468 GTPCI_WRITE_AC(sc, GTPCI_ACBH, prot, 0); 469 GTPCI_WRITE_AC(sc, GTPCI_ACS, prot, 0); 470 } 471 } 472 return; 473 } 474 475 #if NPCI > 0 476 static void 477 gtpci_pci_config(struct gtpci_softc *sc, bus_space_tag_t iot, 478 bus_space_tag_t memt, bus_dma_tag_t dmat, pci_chipset_tag_t pc, 479 u_long iostart, u_long ioend, u_long memstart, u_long memend, 480 int cacheline_size) 481 { 482 struct pcibus_attach_args pba; 483 #ifdef PCI_NETBSD_CONFIGURE 484 struct extent *ioext = NULL, *memext = NULL; 485 #endif 486 uint32_t p2pc, command; 487 488 p2pc = GTPCI_READ(sc, GTPCI_P2PC); 489 490 #ifdef PCI_NETBSD_CONFIGURE 491 ioext = extent_create("pciio", iostart, ioend, M_DEVBUF, NULL, 0, 492 EX_NOWAIT); 493 memext = extent_create("pcimem", memstart, memend, M_DEVBUF, NULL, 0, 494 EX_NOWAIT); 495 if (ioext != NULL && memext != NULL) 496 pci_configure_bus(pc, ioext, memext, NULL, 497 GTPCI_P2PC_BUSNUMBER(p2pc), cacheline_size); 498 else 499 aprint_error_dev(sc->sc_dev, "can't create extent %s%s%s\n", 500 ioext == NULL ? "io" : "", 501 ioext == NULL && memext == NULL ? " and " : "", 502 memext == NULL ? "mem" : ""); 503 if (ioext != NULL) 504 extent_destroy(ioext); 505 if (memext != NULL) 506 extent_destroy(memext); 507 #endif 508 509 pba.pba_iot = iot; 510 pba.pba_memt = memt; 511 pba.pba_dmat = dmat; 512 pba.pba_dmat64 = NULL; 513 pba.pba_pc = pc; 514 if (iot == NULL || memt == NULL) { 515 pba.pba_flags = 0; 516 aprint_error_dev(sc->sc_dev, ""); 517 if (iot == NULL) 518 aprint_error("io "); 519 else 520 pba.pba_flags |= PCI_FLAGS_IO_ENABLED; 521 if (iot == NULL && memt == NULL) 522 aprint_error("and "); 523 if (memt == NULL) 524 aprint_error("mem"); 525 else 526 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED; 527 aprint_error(" access disabled\n"); 528 } else 529 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 530 command = GTPCI_READ(sc, GTPCI_C); 531 if (command & GTPCI_C_MRDMUL) 532 pba.pba_flags |= PCI_FLAGS_MRM_OKAY; 533 if (command & GTPCI_C_MRDLINE) 534 pba.pba_flags |= PCI_FLAGS_MRL_OKAY; 535 pba.pba_flags |= PCI_FLAGS_MWI_OKAY; 536 pba.pba_bus = GTPCI_P2PC_BUSNUMBER(p2pc); 537 pba.pba_bridgetag = NULL; 538 config_found_ia(sc->sc_dev, "pcibus", &pba, NULL); 539 } 540 541 542 /* 543 * Dependent code of PCI Interface of Marvell 544 */ 545 546 /* ARGSUSED */ 547 void 548 gtpci_attach_hook(device_t parent, device_t self, 549 struct pcibus_attach_args *pba) 550 { 551 552 /* Nothing */ 553 } 554 555 /* 556 * Bit map for configuration register: 557 * [31] ConfigEn 558 * [30:24] Reserved 559 * [23:16] BusNum 560 * [15:11] DevNum 561 * [10: 8] FunctNum 562 * [ 7: 2] RegNum 563 * [ 1: 0] reserved 564 */ 565 566 /* ARGSUSED */ 567 int 568 gtpci_bus_maxdevs(void *v, int busno) 569 { 570 571 return 32; /* 32 device/bus */ 572 } 573 574 /* ARGSUSED */ 575 pcitag_t 576 gtpci_make_tag(void *v, int bus, int dev, int func) 577 { 578 579 #if DIAGNOSTIC 580 if (bus >= 256 || dev >= 32 || func >= 8) 581 panic("pci_make_tag: bad request"); 582 #endif 583 584 return (bus << 16) | (dev << 11) | (func << 8); 585 } 586 587 /* ARGSUSED */ 588 void 589 gtpci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 590 { 591 592 if (bp != NULL) 593 *bp = (tag >> 16) & 0xff; 594 if (dp != NULL) 595 *dp = (tag >> 11) & 0x1f; 596 if (fp != NULL) 597 *fp = (tag >> 8) & 0x07; 598 } 599 600 pcireg_t 601 gtpci_conf_read(void *v, pcitag_t tag, int reg) 602 { 603 struct gtpci_softc *sc = v; 604 const pcireg_t addr = tag | reg; 605 606 GTPCI_WRITE(sc, GTPCI_CA, addr | GTPCI_CA_CONFIGEN); 607 if ((addr | GTPCI_CA_CONFIGEN) != GTPCI_READ(sc, GTPCI_CA)) 608 return -1; 609 610 return GTPCI_READ(sc, GTPCI_CD); 611 } 612 613 void 614 gtpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 615 { 616 struct gtpci_softc *sc = v; 617 pcireg_t addr = tag | (reg & 0xfc); 618 619 GTPCI_WRITE(sc, GTPCI_CA, addr | GTPCI_CA_CONFIGEN); 620 if ((addr | GTPCI_CA_CONFIGEN) != GTPCI_READ(sc, GTPCI_CA)) 621 return; 622 623 GTPCI_WRITE(sc, GTPCI_CD, data); 624 } 625 626 /* ARGSUSED */ 627 int 628 gtpci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id) 629 { 630 /* Oops, We have two PCI buses. */ 631 if (dev == 0 && 632 PCI_VENDOR(id) == PCI_VENDOR_MARVELL) { 633 switch (PCI_PRODUCT(id)) { 634 case MARVELL_DISCOVERY: 635 case MARVELL_DISCOVERY_II: 636 case MARVELL_DISCOVERY_III: 637 #if 0 638 case MARVELL_DISCOVERY_LT: 639 case MARVELL_DISCOVERY_V: 640 case MARVELL_DISCOVERY_VI: 641 #endif 642 case MARVELL_ORION_1_88F5180N: 643 case MARVELL_ORION_1_88F5181: 644 case MARVELL_ORION_1_88F5182: 645 case MARVELL_ORION_2_88F5281: 646 case MARVELL_ORION_1_88W8660: 647 /* Don't configure us. */ 648 return 0; 649 } 650 } 651 652 return PCI_CONF_DEFAULT; 653 } 654 #endif /* NPCI > 0 */ 655
Indexes created Sun Oct 19 02:09:48 GMT 2025