gtpci.c revision 1.24
1 /* $NetBSD: gtpci.c,v 1.24 2010/06/02 06:33:40 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008, 2009 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.24 2010/06/02 06:33:40 kiyohara Exp $"); 30 31 #include "opt_pci.h" 32 #include "pci.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 41 #include <prop/proplib.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pciconf.h> 46 47 #include <dev/marvell/gtpcireg.h> 48 #include <dev/marvell/gtpcivar.h> 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 52 #include <machine/pci_machdep.h> 53 54 #include "locators.h" 55 56 57 #define GTPCI_READ(sc, r) \ 58 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit)) 59 #define GTPCI_WRITE(sc, r, v) \ 60 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit), (v)) 61 #define GTPCI_WRITE_AC(sc, r, n, v) \ 62 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, r((sc)->sc_unit, (n)), (v)) 63 64 65 static int gtpci_match(device_t, struct cfdata *, void *); 66 static void gtpci_attach(device_t, device_t, void *); 67 68 static void gtpci_init(struct gtpci_softc *); 69 static void gtpci_barinit(struct gtpci_softc *); 70 static void gtpci_protinit(struct gtpci_softc *); 71 #if NPCI > 0 72 static void gtpci_pci_config(struct gtpci_softc *, bus_space_tag_t, 73 bus_space_tag_t, bus_dma_tag_t, pci_chipset_tag_t, 74 u_long, u_long, u_long, u_long, int); 75 #endif 76 77 78 CFATTACH_DECL_NEW(gtpci_gt, sizeof(struct gtpci_softc), 79 gtpci_match, gtpci_attach, NULL, NULL); 80 CFATTACH_DECL_NEW(gtpci_mbus, sizeof(struct gtpci_softc), 81 gtpci_match, gtpci_attach, NULL, NULL); 82 83 84 /* ARGSUSED */ 85 static int 86 gtpci_match(device_t parent, struct cfdata *match, void *aux) 87 { 88 struct marvell_attach_args *mva = aux; 89 90 if (strcmp(mva->mva_name, match->cf_name) != 0) 91 return 0; 92 93 switch (mva->mva_model) { 94 case MARVELL_DISCOVERY: 95 case MARVELL_DISCOVERY_II: 96 case MARVELL_DISCOVERY_III: 97 #if 0 /* XXXXX */ 98 case MARVELL_DISCOVERY_LT: 99 case MARVELL_DISCOVERY_V: 100 case MARVELL_DISCOVERY_VI: 101 #endif 102 if (mva->mva_unit == GTCF_UNIT_DEFAULT || 103 mva->mva_offset != GTCF_OFFSET_DEFAULT) 104 return 0; 105 break; 106 107 case MARVELL_ORION_1_88F5180N: 108 case MARVELL_ORION_1_88F5181: 109 case MARVELL_ORION_1_88F5182: 110 case MARVELL_ORION_2_88F5281: 111 case MARVELL_ORION_1_88W8660: 112 if (mva->mva_offset == GTCF_OFFSET_DEFAULT) 113 return 0; 114 mva->mva_unit = 0; /* unit 0 only */ 115 break; 116 117 default: 118 return 0; 119 } 120 121 mva->mva_size = GTPCI_SIZE; 122 return 1; 123 } 124 125 /* ARGSUSED */ 126 static void 127 gtpci_attach(device_t parent, device_t self, void *aux) 128 { 129 struct gtpci_softc *sc = device_private(self); 130 struct marvell_attach_args *mva = aux; 131 #if NPCI > 0 132 prop_dictionary_t dict = device_properties(self); 133 prop_object_t pc, iot, memt; 134 prop_array_t int2gpp; 135 prop_object_t gpp; 136 pci_chipset_tag_t gtpci_chipset; 137 bus_space_tag_t gtpci_io_bs_tag, gtpci_mem_bs_tag; 138 uint64_t iostart = 0, ioend = 0, memstart = 0, memend = 0; 139 int cl_size = 0, intr; 140 #endif 141 142 aprint_normal(": Marvell PCI Interface\n"); 143 aprint_naive("\n"); 144 145 #if NPCI > 0 146 iot = prop_dictionary_get(dict, "io-bus-tag"); 147 if (iot != NULL) { 148 KASSERT(prop_object_type(iot) == PROP_TYPE_DATA); 149 gtpci_io_bs_tag = __UNCONST(prop_data_data_nocopy(iot)); 150 } else { 151 aprint_error_dev(self, "no io-bus-tag property\n"); 152 gtpci_io_bs_tag = NULL; 153 } 154 memt = prop_dictionary_get(dict, "mem-bus-tag"); 155 if (memt != NULL) { 156 KASSERT(prop_object_type(memt) == PROP_TYPE_DATA); 157 gtpci_mem_bs_tag = __UNCONST(prop_data_data_nocopy(memt)); 158 } else { 159 aprint_error_dev(self, "no mem-bus-tag property\n"); 160 gtpci_mem_bs_tag = NULL; 161 } 162 pc = prop_dictionary_get(dict, "pci-chipset"); 163 if (pc == NULL) { 164 aprint_error_dev(self, "no pci-chipset property\n"); 165 return; 166 } 167 KASSERT(prop_object_type(pc) == PROP_TYPE_DATA); 168 gtpci_chipset = __UNCONST(prop_data_data_nocopy(pc)); 169 #ifdef PCI_NETBSD_CONFIGURE 170 if (!prop_dictionary_get_uint64(dict, "iostart", &iostart)) { 171 aprint_error_dev(self, "no iostart property\n"); 172 return; 173 } 174 if (!prop_dictionary_get_uint64(dict, "ioend", &ioend)) { 175 aprint_error_dev(self, "no ioend property\n"); 176 return; 177 } 178 if (!prop_dictionary_get_uint64(dict, "memstart", &memstart)) { 179 aprint_error_dev(self, "no memstart property\n"); 180 return; 181 } 182 if (!prop_dictionary_get_uint64(dict, "memend", &memend)) { 183 aprint_error_dev(self, "no memend property\n"); 184 return; 185 } 186 if (!prop_dictionary_get_uint32(dict, "cache-line-size", &cl_size)) { 187 aprint_error_dev(self, "no cache-line-size property\n"); 188 return; 189 } 190 #endif 191 #endif 192 193 sc->sc_dev = self; 194 sc->sc_model = mva->mva_model; 195 sc->sc_rev = mva->mva_revision; 196 sc->sc_unit = mva->mva_unit; 197 sc->sc_iot = mva->mva_iot; 198 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 199 (mva->mva_offset != GTCF_OFFSET_DEFAULT) ? mva->mva_offset : 0, 200 mva->mva_size, &sc->sc_ioh)) { 201 aprint_error_dev(self, "can't map registers\n"); 202 return; 203 } 204 sc->sc_pc = gtpci_chipset; 205 gtpci_init(sc); 206 207 #if NPCI > 0 208 int2gpp = prop_dictionary_get(dict, "int2gpp"); 209 if (int2gpp != NULL) { 210 if (prop_object_type(int2gpp) != PROP_TYPE_ARRAY) { 211 aprint_error_dev(self, "int2gpp not an array\n"); 212 return; 213 } 214 aprint_normal_dev(self, "use intrrupt pin:"); 215 for (intr = PCI_INTERRUPT_PIN_A; 216 intr <= PCI_INTERRUPT_PIN_D && 217 intr < prop_array_count(int2gpp); 218 intr++) { 219 gpp = prop_array_get(int2gpp, intr); 220 if (prop_object_type(gpp) != PROP_TYPE_NUMBER) { 221 aprint_error_dev(self, 222 "int2gpp[%d] not an number\n", intr); 223 return; 224 } 225 aprint_normal(" %d", 226 (int)prop_number_integer_value(gpp)); 227 } 228 aprint_normal("\n"); 229 } 230 231 gtpci_pci_config(sc, gtpci_io_bs_tag, gtpci_mem_bs_tag, mva->mva_dmat, 232 gtpci_chipset, iostart, ioend, memstart, memend, cl_size); 233 #endif 234 } 235 236 static void 237 gtpci_init(struct gtpci_softc *sc) 238 { 239 uint32_t reg; 240 241 /* First, all disable. Also WA CQ 4382 (bit15 must set 1)*/ 242 GTPCI_WRITE(sc, GTPCI_BARE, GTPCI_BARE_ALLDISABLE | (1 << 15)); 243 244 /* Enable Internal Arbiter */ 245 reg = GTPCI_READ(sc, GTPCI_AC); 246 reg |= GTPCI_AC_EN; 247 GTPCI_WRITE(sc, GTPCI_AC, reg); 248 249 gtpci_barinit(sc); 250 gtpci_protinit(sc); 251 252 reg = GTPCI_READ(sc, GTPCI_ADC); 253 reg |= GTPCI_ADC_REMAPWRDIS; 254 GTPCI_WRITE(sc, GTPCI_ADC, reg); 255 256 /* enable CPU-2-PCI ordering */ 257 reg = GTPCI_READ(sc, GTPCI_C); 258 reg |= GTPCI_C_CPU2PCIORDERING; 259 GTPCI_WRITE(sc, GTPCI_C, reg); 260 } 261 262 static void 263 gtpci_barinit(struct gtpci_softc *sc) 264 { 265 static const struct { 266 int tag; 267 int bars[2]; /* BAR Size registers */ 268 int bare; /* Bits of Base Address Registers Enable */ 269 int func; 270 int balow; 271 int bahigh; 272 } maps[] = { 273 { MARVELL_TAG_SDRAM_CS0, 274 { GTPCI_CS0BARS(0), GTPCI_CS0BARS(1) }, 275 GTPCI_BARE_CS0EN, 0, 0x10, 0x14 }, 276 { MARVELL_TAG_SDRAM_CS1, 277 { GTPCI_CS1BARS(0), GTPCI_CS1BARS(1) }, 278 GTPCI_BARE_CS1EN, 0, 0x18, 0x1c }, 279 { MARVELL_TAG_SDRAM_CS2, 280 { GTPCI_CS2BARS(0), GTPCI_CS2BARS(1) }, 281 GTPCI_BARE_CS2EN, 1, 0x10, 0x14 }, 282 { MARVELL_TAG_SDRAM_CS3, 283 { GTPCI_CS3BARS(0), GTPCI_CS3BARS(1) }, 284 GTPCI_BARE_CS3EN, 1, 0x18, 0x1c }, 285 #if 0 286 { ORION_TARGETID_INTERNALREG, 287 { -1, -1 }, 288 GTPCI_BARE_INTMEMEN, 0, 0x20, 0x24 }, 289 290 { ORION_TARGETID_DEVICE_CS0, 291 { GTPCI_DCS0BARS(0), GTPCI_DCS0BARS(1) }, 292 GTPCI_BARE_DEVCS0EN, 2, 0x10, 0x14 }, 293 { ORION_TARGETID_DEVICE_CS1, 294 { GTPCI_DCS1BARS(0), GTPCI_DCS1BARS(1) }, 295 GTPCI_BARE_DEVCS1EN, 2, 0x18, 0x1c }, 296 { ORION_TARGETID_DEVICE_CS2, 297 { GTPCI_DCS2BARS(0), GTPCI_DCS2BARS(1) }, 298 GTPCI_BARE_DEVCS2EN, 2, 0x20, 0x24 }, 299 { ORION_TARGETID_DEVICE_BOOTCS, 300 { GTPCI_BCSBARS(0), GTPCI_BCSBARS(1) }, 301 GTPCI_BARE_BOOTCSEN, 3, 0x18, 0x1c }, 302 { P2P Mem0 BAR, 303 { GTPCI_P2PM0BARS(0), GTPCI_P2PM0BARS(1) }, 304 GTPCI_BARE_P2PMEM0EN, 4, 0x10, 0x14 }, 305 { P2P I/O BAR, 306 { GTPCI_P2PIOBARS(0), GTPCI_P2PIOBARS(1) }, 307 GTPCI_BARE_P2PIO0EN, 4, 0x20, 0x24 }, 308 { Expansion ROM BAR, 309 { GTPCI_EROMBARS(0), GTPCI_EROMBARS(1) }, 310 0, }, 311 #endif 312 313 { MARVELL_TAG_UNDEFINED, 314 { -1, -1 }, 315 -1, -1, 0x00, 0x00 }, 316 }; 317 device_t pdev = device_parent(sc->sc_dev); 318 uint64_t base; 319 uint32_t p2pc, size, bare; 320 int map, bus, dev, rv; 321 322 p2pc = GTPCI_READ(sc, GTPCI_P2PC); 323 bus = GTPCI_P2PC_BUSNUMBER(p2pc); 324 dev = GTPCI_P2PC_DEVNUM(p2pc); 325 326 bare = GTPCI_BARE_ALLDISABLE; 327 for (map = 0; maps[map].tag != MARVELL_TAG_UNDEFINED; map++) { 328 rv = marvell_winparams_by_tag(pdev, maps[map].tag, NULL, NULL, 329 &base, &size); 330 if (rv != 0 || size == 0) 331 continue; 332 333 if (maps[map].bars[sc->sc_unit] != -1) 334 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 335 maps[map].bars[sc->sc_unit], GTPCI_BARSIZE(size)); 336 bare &= ~maps[map].bare; 337 338 #if 0 /* shall move to pchb(4)? */ 339 if (maps[map].func != -1) { 340 pcitag_t tag; 341 pcireg_t reg; 342 343 tag = gtpci_make_tag(NULL, bus, dev, maps[map].func); 344 reg = gtpci_conf_read(sc, tag, maps[map].balow); 345 reg &= ~GTPCI_BARLOW_MASK; 346 reg |= GTPCI_BARLOW_BASE(base); 347 gtpci_conf_write(sc, tag, maps[map].balow, reg); 348 reg = gtpci_conf_read(sc, tag, maps[map].bahigh); 349 reg = (base >> 16) >> 16; 350 gtpci_conf_write(sc, tag, maps[map].bahigh, reg); 351 } 352 #endif 353 } 354 GTPCI_WRITE(sc, GTPCI_BARE, bare); 355 } 356 357 static void 358 gtpci_protinit(struct gtpci_softc *sc) 359 { 360 enum { 361 gt64260 = 0, 362 mv64360, 363 soc, 364 }; 365 const struct gtpci_prot { 366 uint32_t acbl_flags; 367 uint32_t acbl_base_rshift; 368 uint32_t acs_flags; 369 uint32_t acs_size_rshift; 370 } gtpci_prots[] = { 371 { /* GT64260 */ 372 #if 0 373 GTPCI_GT64260_ACBL_PCISWAP_NOSWAP | 374 GTPCI_GT64260_ACBL_WBURST_4_QW | 375 GTPCI_GT64260_ACBL_RDMULPREFETCH | 376 GTPCI_GT64260_ACBL_RDLINEPREFETCH | 377 GTPCI_GT64260_ACBL_RDPREFETCH | 378 GTPCI_GT64260_ACBL_DREADEN, 379 #else 380 GTPCI_GT64260_ACBL_PCISWAP_NOSWAP | 381 GTPCI_GT64260_ACBL_WBURST_8_QW | 382 GTPCI_GT64260_ACBL_RDMULPREFETCH | 383 GTPCI_GT64260_ACBL_RDLINEPREFETCH | 384 GTPCI_GT64260_ACBL_RDPREFETCH | 385 GTPCI_GT64260_ACBL_PREFETCHEN, 386 #endif 387 20, 388 0, 389 20 390 }, 391 { /* MV64360 and after */ 392 GTPCI_ACBL_RDSIZE_256BYTE | 393 GTPCI_ACBL_RDMBURST_128BYTE | 394 GTPCI_ACBL_PCISWAP_NOSWAP | 395 GTPCI_ACBL_SNOOP_NONE | 396 GTPCI_ACBL_EN, 397 0, 398 0, 399 0 400 }, 401 { /* Orion */ 402 GTPCI_ACBL_RDSIZE_256BYTE | 403 GTPCI_ACBL_RDMBURST_128BYTE | 404 GTPCI_ACBL_PCISWAP_BYTESWAP, 405 0, 406 GTPCI_ACS_WRMBURST_128BYTE, 407 0 408 }, 409 }; 410 const uint32_t prot_tags[] = { 411 MARVELL_TAG_SDRAM_CS0, 412 MARVELL_TAG_SDRAM_CS1, 413 MARVELL_TAG_SDRAM_CS2, 414 MARVELL_TAG_SDRAM_CS3, 415 MARVELL_TAG_UNDEFINED 416 }; 417 device_t pdev = device_parent(sc->sc_dev); 418 uint64_t acbase, base; 419 uint32_t acsize, size; 420 int acbl_base_rshift, acbl_flags, acs_size_rshift, acs_flags; 421 int prot, rv, p, t; 422 423 switch (sc->sc_model) { 424 case MARVELL_DISCOVERY: 425 p = gt64260; 426 break; 427 428 case MARVELL_DISCOVERY_II: 429 case MARVELL_DISCOVERY_III: 430 #if 0 431 case MARVELL_DISCOVERY_LT: 432 case MARVELL_DISCOVERY_V: 433 case MARVELL_DISCOVERY_VI: 434 #endif 435 p = mv64360; 436 break; 437 438 default: 439 p = soc; 440 break; 441 } 442 acbl_base_rshift = gtpci_prots[p].acbl_base_rshift; 443 acbl_flags = gtpci_prots[p].acbl_flags; 444 acs_size_rshift = gtpci_prots[p].acs_size_rshift; 445 acs_flags = gtpci_prots[p].acs_flags; 446 447 t = 0; 448 for (prot = 0; prot < GTPCI_NPCIAC; prot++) { 449 acbase = acsize = 0; 450 451 for ( ; prot_tags[t] != MARVELL_TAG_UNDEFINED; t++) { 452 rv = marvell_winparams_by_tag(pdev, prot_tags[t], 453 NULL, NULL, &base, &size); 454 if (rv != 0 || size == 0) 455 continue; 456 457 if (acsize == 0 || base + size == acbase) 458 acbase = base; 459 else if (acbase + acsize != base) 460 break; 461 acsize += size; 462 } 463 464 if (acsize != 0) { 465 GTPCI_WRITE_AC(sc, GTPCI_ACBL, prot, 466 ((acbase & 0xffffffff) >> acbl_base_rshift) | 467 acbl_flags); 468 GTPCI_WRITE_AC(sc, GTPCI_ACBH, prot, 469 (acbase >> 32) & 0xffffffff); 470 GTPCI_WRITE_AC(sc, GTPCI_ACS, prot, 471 ((acsize - 1) >> acs_size_rshift) | acs_flags); 472 } else { 473 GTPCI_WRITE_AC(sc, GTPCI_ACBL, prot, 0); 474 GTPCI_WRITE_AC(sc, GTPCI_ACBH, prot, 0); 475 GTPCI_WRITE_AC(sc, GTPCI_ACS, prot, 0); 476 } 477 } 478 return; 479 } 480 481 #if NPCI > 0 482 static void 483 gtpci_pci_config(struct gtpci_softc *sc, bus_space_tag_t iot, 484 bus_space_tag_t memt, bus_dma_tag_t dmat, pci_chipset_tag_t pc, 485 u_long iostart, u_long ioend, u_long memstart, u_long memend, 486 int cacheline_size) 487 { 488 struct pcibus_attach_args pba; 489 #ifdef PCI_NETBSD_CONFIGURE 490 struct extent *ioext = NULL, *memext = NULL; 491 #endif 492 uint32_t p2pc, command; 493 494 p2pc = GTPCI_READ(sc, GTPCI_P2PC); 495 496 #ifdef PCI_NETBSD_CONFIGURE 497 ioext = extent_create("pciio", iostart, ioend, M_DEVBUF, NULL, 0, 498 EX_NOWAIT); 499 memext = extent_create("pcimem", memstart, memend, M_DEVBUF, NULL, 0, 500 EX_NOWAIT); 501 if (ioext != NULL && memext != NULL) 502 pci_configure_bus(pc, ioext, memext, NULL, 503 GTPCI_P2PC_BUSNUMBER(p2pc), cacheline_size); 504 else 505 aprint_error_dev(sc->sc_dev, "can't create extent %s%s%s\n", 506 ioext == NULL ? "io" : "", 507 ioext == NULL && memext == NULL ? " and " : "", 508 memext == NULL ? "mem" : ""); 509 if (ioext != NULL) 510 extent_destroy(ioext); 511 if (memext != NULL) 512 extent_destroy(memext); 513 #endif 514 515 pba.pba_iot = iot; 516 pba.pba_memt = memt; 517 pba.pba_dmat = dmat; 518 pba.pba_dmat64 = NULL; 519 pba.pba_pc = pc; 520 if (iot == NULL || memt == NULL) { 521 pba.pba_flags = 0; 522 aprint_error_dev(sc->sc_dev, ""); 523 if (iot == NULL) 524 aprint_error("io "); 525 else 526 pba.pba_flags |= PCI_FLAGS_IO_ENABLED; 527 if (iot == NULL && memt == NULL) 528 aprint_error("and "); 529 if (memt == NULL) 530 aprint_error("mem"); 531 else 532 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED; 533 aprint_error(" access disabled\n"); 534 } else 535 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 536 command = GTPCI_READ(sc, GTPCI_C); 537 if (command & GTPCI_C_MRDMUL) 538 pba.pba_flags |= PCI_FLAGS_MRM_OKAY; 539 if (command & GTPCI_C_MRDLINE) 540 pba.pba_flags |= PCI_FLAGS_MRL_OKAY; 541 pba.pba_flags |= PCI_FLAGS_MWI_OKAY; 542 pba.pba_bus = GTPCI_P2PC_BUSNUMBER(p2pc); 543 pba.pba_bridgetag = NULL; 544 config_found_ia(sc->sc_dev, "pcibus", &pba, NULL); 545 } 546 547 548 /* 549 * Dependent code of PCI Interface of Marvell 550 */ 551 552 /* ARGSUSED */ 553 void 554 gtpci_attach_hook(device_t parent, device_t self, 555 struct pcibus_attach_args *pba) 556 { 557 558 /* Nothing */ 559 } 560 561 /* 562 * Bit map for configuration register: 563 * [31] ConfigEn 564 * [30:24] Reserved 565 * [23:16] BusNum 566 * [15:11] DevNum 567 * [10: 8] FunctNum 568 * [ 7: 2] RegNum 569 * [ 1: 0] reserved 570 */ 571 572 /* ARGSUSED */ 573 int 574 gtpci_bus_maxdevs(void *v, int busno) 575 { 576 577 return 32; /* 32 device/bus */ 578 } 579 580 /* ARGSUSED */ 581 pcitag_t 582 gtpci_make_tag(void *v, int bus, int dev, int func) 583 { 584 585 #if DIAGNOSTIC 586 if (bus >= 256 || dev >= 32 || func >= 8) 587 panic("pci_make_tag: bad request"); 588 #endif 589 590 return (bus << 16) | (dev << 11) | (func << 8); 591 } 592 593 /* ARGSUSED */ 594 void 595 gtpci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 596 { 597 598 if (bp != NULL) 599 *bp = (tag >> 16) & 0xff; 600 if (dp != NULL) 601 *dp = (tag >> 11) & 0x1f; 602 if (fp != NULL) 603 *fp = (tag >> 8) & 0x07; 604 } 605 606 pcireg_t 607 gtpci_conf_read(void *v, pcitag_t tag, int reg) 608 { 609 struct gtpci_softc *sc = v; 610 const pcireg_t addr = tag | reg; 611 612 GTPCI_WRITE(sc, GTPCI_CA, addr | GTPCI_CA_CONFIGEN); 613 if ((addr | GTPCI_CA_CONFIGEN) != GTPCI_READ(sc, GTPCI_CA)) 614 return -1; 615 616 return GTPCI_READ(sc, GTPCI_CD); 617 } 618 619 void 620 gtpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 621 { 622 struct gtpci_softc *sc = v; 623 pcireg_t addr = tag | (reg & 0xfc); 624 625 GTPCI_WRITE(sc, GTPCI_CA, addr | GTPCI_CA_CONFIGEN); 626 if ((addr | GTPCI_CA_CONFIGEN) != GTPCI_READ(sc, GTPCI_CA)) 627 return; 628 629 GTPCI_WRITE(sc, GTPCI_CD, data); 630 } 631 632 /* ARGSUSED */ 633 int 634 gtpci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id) 635 { 636 /* Oops, We have two PCI buses. */ 637 if (dev == 0 && 638 PCI_VENDOR(id) == PCI_VENDOR_MARVELL) { 639 switch (PCI_PRODUCT(id)) { 640 case MARVELL_DISCOVERY: 641 case MARVELL_DISCOVERY_II: 642 case MARVELL_DISCOVERY_III: 643 #if 0 644 case MARVELL_DISCOVERY_LT: 645 case MARVELL_DISCOVERY_V: 646 case MARVELL_DISCOVERY_VI: 647 #endif 648 case MARVELL_ORION_1_88F5180N: 649 case MARVELL_ORION_1_88F5181: 650 case MARVELL_ORION_1_88F5182: 651 case MARVELL_ORION_2_88F5281: 652 case MARVELL_ORION_1_88W8660: 653 /* Don't configure us. */ 654 return 0; 655 } 656 } 657 658 return PCI_CONF_DEFAULT; 659 } 660 #endif /* NPCI > 0 */ 661
Indexes created Fri Oct 17 03:10:13 GMT 2025