gtpcireg.h revision 1.5
1 /* $NetBSD: gtpcireg.h,v 1.5 2010/04/28 13:51:56 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2008, 2009 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _GTPCIREG_H_ 29 #define _GTPCIREG_H_ 30 31 32 /* 33 * PCI Interface Registers 34 */ 35 #define GTPCI_SIZE 0x2000 36 37 #define GTPCI_NINTERFACE 2 38 39 40 /* PCI Slave Address Decording Registers */ 41 /* BAR Sizes */ 42 #define GTPCI_CS0BARS(p) (0x0c08 | ((p) << 7)) /* CSn[0] */ 43 #define GTPCI_CS1BARS(p) (0x0d08 | ((p) << 7)) /* CSn[1] */ 44 #define GTPCI_CS2BARS(p) (0x0c0c | ((p) << 7)) /* CSn[2] */ 45 #define GTPCI_CS3BARS(p) (0x0d0c | ((p) << 7)) /* CSn[3] */ 46 #define GTPCI_DCS0BARS(p) (0x0c10 | ((p) << 7)) /* DevCSn[0] */ 47 #define GTPCI_DCS1BARS(p) (0x0d10 | ((p) << 7)) /* DevCSn[1] */ 48 #define GTPCI_DCS2BARS(p) (0x0d18 | ((p) << 7)) /* DevCSn[2] */ 49 #define GTPCI_BCSBARS(p) (0x0d14 | ((p) << 7)) /* Boot CSn */ 50 #define GTPCI_P2PM0BARS(p) (0x0d1c | ((p) << 7)) /* P2P Mem0 */ 51 #define GTPCI_P2PIOBARS(p) (0x0d24 | ((p) << 7)) /* P2P I/O */ 52 #define GTPCI_EROMBARS(p) (0x0d2c | ((p) << 7)) /* Expansion ROM */ 53 #define GTPCI_BARSIZE(s) (((s) - 1) & 0xfffff000) 54 #define GTPCI_BARE(p) (0x0c3c | ((p) << 7)) /* Base Addr Reg En */ 55 #define GTPCI_BARE_ALLDISABLE 0xffffffff 56 #define GTPCI_BARE_CS0EN (1 << 0) 57 #define GTPCI_BARE_CS1EN (1 << 1) 58 #define GTPCI_BARE_CS2EN (1 << 2) 59 #define GTPCI_BARE_CS3EN (1 << 3) 60 #define GTPCI_BARE_DEVCS0EN (1 << 4) 61 #define GTPCI_BARE_DEVCS1EN (1 << 5) 62 #define GTPCI_BARE_DEVCS2EN (1 << 6) 63 #define GTPCI_BARE_BOOTCSEN (1 << 8) 64 #define GTPCI_BARE_INTMEMEN (1 << 9) 65 #define GTPCI_BARE_INTIOEN (1 << 10) 66 #define GTPCI_BARE_P2PMEM0EN (1 << 11) 67 #define GTPCI_BARE_P2PIO0EN (1 << 13) 68 #define GTPCI_REMAP(a) ((a) & 0xfffff000) 69 /* Base Addr Remaps */ 70 #define GTPCI_CS0BAR(p) (0x0c48 | ((p) << 7)) /* CSn[0] */ 71 #define GTPCI_CS1BAR(p) (0x0d48 | ((p) << 7)) /* CSn[1] */ 72 #define GTPCI_CS2BAR(p) (0x0c4c | ((p) << 7)) /* CSn[2] */ 73 #define GTPCI_CS3BAR(p) (0x0d4c | ((p) << 7)) /* CSn[3] */ 74 #define GTPCI_DCS0BAR(p) (0x0c50 | ((p) << 7)) /* DevCSn[0] */ 75 #define GTPCI_DCS1BAR(p) (0x0d50 | ((p) << 7)) /* DevCSn[1] */ 76 #define GTPCI_DCS2BAR(p) (0x0d58 | ((p) << 7)) /* DevCSn[2] */ 77 #define GTPCI_BCSBAR(p) (0x0d54 | ((p) << 7)) /* Boot CSn */ 78 #define GTPCI_P2PM0BARL(p) (0x0d5c | ((p) << 7)) /* P2P Mem0 (Low) */ 79 #define GTPCI_P2PM0BARH(p) (0x0d60 | ((p) << 7)) /* P2P Mem0 (High) */ 80 #define GTPCI_P2PIOBAR(p) (0x0d6c | ((p) << 7)) /* P2P I/O */ 81 #define GTPCI_EROMBAR(p) (0x0f38 | ((p) << 7)) /* Expresion ROM */ 82 #define GTPCI_DRAMBARBS(p) (0x0c1c | ((p) << 7)) /*DRAM BAR Bank Select*/ 83 #define GTPCI_ADC(p) (0x0d3c | ((p) << 7)) /* Addr Decode Ctrl */ 84 #define GTPCI_ADC_REMAPWRDIS (1 << 0) 85 86 /* PCI Control Register Map */ 87 #define GTPCI_DLLC(p) (0x1d20 | ((p) << 7)) /* PCI DLL Control */ 88 #define GTPCI_MPPPC(p) (0x1d1c | ((p) << 7)) /*PCI/MPP Pads Calibrt*/ 89 #define GTPCI_C(p) (0x0c00 | ((p) << 7)) /* Command */ 90 #define GTPCI_C_MBYTESWAP (1 << 0) /* Master Byte Swap */ 91 #define GTPCI_C_MWRCOM (1 << 4) /* Master Wr Combine Enable */ 92 #define GTPCI_C_MRDCOM (1 << 5) /* Master Rd Combine Enable */ 93 #define GTPCI_C_MWRTRIG (1 << 6) /*Master Write Trigger*/ 94 #define GTPCI_C_MRDTRIG (1 << 7) /*Master Read Trigger */ 95 #define GTPCI_C_MRDLINE (1 << 8) /* Master Mem Rd Line Enable */ 96 #define GTPCI_C_MRDMUL (1 << 9) /* Master Mem Rd Mult Enable */ 97 #define GTPCI_C_MWORDSWAP (1 << 10) /* Master Word Swap */ 98 #define GTPCI_C_SWORDSWAP (1 << 11) /* Slave Word Swap */ 99 #define GTPCI_C_SBYTESWAP (1 << 16) /* Slave Byte Swap */ 100 #define GTPCI_C_MDACEN (1 << 17) /* Master DAC Enable */ 101 #define GTPCI_C_PERRPROP (1 << 19)/*Pari/ECC Err Propagation En*/ 102 #define GTPCI_C_SSWAPEN (1 << 20) /* Slave Swap Enable */ 103 #define GTPCI_C_MSWAPEN (1 << 21) /* Master Swap Enable */ 104 #define GTPCI_C_SINTSWAP_BYTESWAP (0 << 24) 105 #define GTPCI_C_SINTSWAP_NOSWAP (1 << 24) 106 #define GTPCI_C_SINTSWAP_BOTH (2 << 24) 107 #define GTPCI_C_SINTSWAP_WORDSWAP (3 << 24) 108 #define GTPCI_C_SSBINT (1 << 28) 109 #define GTPCI_C_CPU2PCIORDERING (1 << 29) /* PCI2CPU Ordering En*/ 110 #define GTPCI_M(p) (0x0d00 | ((p) << 7)) /* Mode */ 111 #define GTPCI_R(p) (0x0c04 | ((p) << 7)) /* Retry */ 112 #define GTPCI_DT(p) (0x0d04 | ((p) << 7)) /* Discard Timer */ 113 #define GTPCI_MSITT(p) (0x0c38 | ((p) << 7)) /* MSI Trigger Timer */ 114 #define GTPCI_AC(p) (0x1d00 | ((p) << 7)) /* Arviter Control */ 115 #define GTPCI_AC_BDEN (1 << 0) /* Broken Detection Enable */ 116 #define GTPCI_AC_BV(v) ((v) << 3) /* Broken Value */ 117 #define GTPCI_AC_PD(v) ((v) << 14) /* Parking Disable */ 118 #define GTPCI_AC_EN (1 << 31) /* En Inter Arb Ope */ 119 #define GTPCI_P2PC(p) (0x1d14 | ((p) << 7)) /* P2P Configuration */ 120 #define GTPCI_P2PC_BUSNUMBER(x) (((x) >> 16) & 0xff) 121 #define GTPCI_P2PC_DEVNUM(x) (((x) >> 24) & 0x1f) 122 #define GTPCI_NPCIAC 6 123 #define GTPCI_ACBL(p, N) (0x1e00 | ((p) << 7) | ((N) << 4)) 124 /* Access Control Base N (Low) */ 125 #define GTPCI_ACBL_EN (1 << 0) 126 #define GTPCI_ACBL_REQ64 (1 << 1) 127 #define GTPCI_ACBL_SNOOP_MASK (3 << 2) 128 #define GTPCI_ACBL_SNOOP_NONE (0 << 2) 129 #define GTPCI_ACBL_SNOOP_WT (1 << 2) 130 #define GTPCI_ACBL_SNOOP_WB (2 << 2) 131 #define GTPCI_ACBL_ACCPROT (1 << 4) 132 #define GTPCI_ACBL_WRPROT (1 << 5) 133 #define GTPCI_ACBL_PCISWAP_MASK (3 << 6) 134 #define GTPCI_ACBL_PCISWAP_BYTESWAP (0 << 6) 135 #define GTPCI_ACBL_PCISWAP_NOSWAP (1 << 6) 136 #define GTPCI_ACBL_PCISWAP_BOTHSWAP (2 << 6) 137 #define GTPCI_ACBL_PCISWAP_WORDSWAP (3 << 6) 138 #define GTPCI_ACBL_RDMBURST_MASK (3 << 8) 139 #define GTPCI_ACBL_RDMBURST_32BYTE (0 << 8) 140 #define GTPCI_ACBL_RDMBURST_64BYTE (1 << 8) 141 #define GTPCI_ACBL_RDMBURST_128BYTE (2 << 8) 142 #define GTPCI_ACBL_RDSIZE_MASK (3 << 10) 143 #define GTPCI_ACBL_RDSIZE_32BYTE (0 << 10) 144 #define GTPCI_ACBL_RDSIZE_64BYTE (1 << 10) 145 #define GTPCI_ACBL_RDSIZE_128BYTE (2 << 10) 146 #define GTPCI_ACBL_RDSIZE_256BYTE (3 << 10) 147 #define GTPCI_ACBL_BASE(b) ((b) & 0xfffff000) 148 149 #define GTPCI_GT64260_ACBL_BASE(b) ((b) & 0x00000fff) 150 #define GTPCI_GT64260_ACBL_PREFETCHEN (1 << 12) 151 #define GTPCI_GT64260_ACBL_DREADEN (1 << 13) 152 #define GTPCI_GT64260_ACBL_RDPREFETCH (1 << 16) 153 #define GTPCI_GT64260_ACBL_RDLINEPREFETCH (1 << 17) 154 #define GTPCI_GT64260_ACBL_RDMULPREFETCH (1 << 18) 155 #define GTPCI_GT64260_ACBL_WBURST_MASK (3 << 20) 156 #define GTPCI_GT64260_ACBL_WBURST_4_QW (0 << 20) 157 #define GTPCI_GT64260_ACBL_WBURST_8_QW (1 << 20) 158 #define GTPCI_GT64260_ACBL_WBURST_16_QW (2 << 20) 159 #define PCI_ACCCTLBASEL_PCISwap PCI__EXT(v, 24, 2) 160 #define PCI_ACCCTLBASEL_PCISwap_NoSwap PCI__INS(24, PCI_PCISWAP_NoSwap) 161 #define GTPCI_GT64260_ACBL_PCISWAP_BYTESWAP (0 << 24) 162 #define GTPCI_GT64260_ACBL_PCISWAP_NOSWAP (1 << 24) 163 #define GTPCI_GT64260_ACBL_PCISWAP_BYTEWORDSWAP (3 << 24) 164 #define GTPCI_GT64260_ACBL_PCISWAP_WORDSWAP (3 << 24) 165 #define GTPCI_GT64260_ACBL_ACCPROT (1 << 28) 166 #define GTPCI_GT64260_ACBL_WRPROT (1 << 29) 167 168 #define GTPCI_ACBH(p, N) (0x1e04 | ((p) << 7) | ((N) << 4)) 169 /* Access Control Base N (High) */ 170 #define GTPCI_ACS(p, N) (0x1e08 | ((p) << 7) | ((N) << 4)) 171 /* Access Ctrl Size N */ 172 #define GTPCI_ACS_AGGRWM1 (1 << 4) 173 #define GTPCI_ACS_WRMBURST_MASK (3 << 8) 174 #define GTPCI_ACS_WRMBURST_32BYTE (0 << 8) 175 #define GTPCI_ACS_WRMBURST_64BYTE (1 << 8) 176 #define GTPCI_ACS_WRMBURST_128BYTE (2 << 8) 177 #define GTPCI_ACS_AGGR (1 << 10) 178 #define GTPCI_ACS_PCIOR (1 << 11) 179 #define GTPCI_ACS_SIZE(s) (((s) - 1) & 0xfffff000) 180 181 /* PCI Configuration Access Register Map */ 182 #define GTPCI_CA(p) (0x0cf8 ^ ((p) << 7)) /* Configuration Addr */ 183 #define GTPCI_CA_CONFIGEN (1 << 31) 184 #define GTPCI_CD(p) (0x0cfc ^ ((p) << 7)) /* Configuration Data */ 185 186 #define GTPCI_IA(p) (0x0c34 | ((p) << 7) /* Intr Acknowledge */ 187 188 /* PCI Error Report Register Map */ 189 #define GTPCI_SERRM(p) (0x0c28 | ((p) << 7) /* SERRn Mask */ 190 #define GTPCI_IC(p) (0x0d58 | ((p) << 7) /* Interrupt Cause */ 191 #define GTPCI_IM(p) (0x0d5c | ((p) << 7) /* Interrupt Mask */ 192 #define GTPCI_EAL(p) (0x0d40 | ((p) << 7) /* Error Addr (Low) */ 193 #define GTPCI_EAH(p) (0x0d44 | ((p) << 7) /* Error Addr (High) */ 194 #define GTPCI_EC(p) (0x0d50 | ((p) << 7) /* Error Command */ 195 196 /* PCI Configuration, Function 0, Register Map */ 197 /* see at dev/pci/pcireg.h from 0x00 to 0x3c. */ 198 199 #define GTPCI_BARLOW_MASK 0xfffff000 200 #define GTPCI_BARLOW_BASE(b) ((b) & GTPCI_BARLOW_MASK) 201 202 #endif /* _GTPCIREG_H_ */ 203
Indexes created Sun Sep 28 16:09:52 GMT 2025