gtreg.h revision 1.4
1 /* $NetBSD: gtreg.h,v 1.4 2010/04/28 13:51:56 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _DISCOVERY_DEV_GTREG_H_ 41 #define _DISCOVERY_DEV_GTREG_H_ 42 43 #define GT__BIT(bit) (1U << (bit)) 44 #define GT__MASK(bit) (GT__BIT(bit) - 1) 45 #define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) 46 #define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) 47 #define GT__INS(new, bit) ((new) << (bit)) 48 49 #define GT_SIZE 0x10000 50 51 /* 52 * Table 30: CPU Address Decode Register Map 53 */ 54 #define GT_SCS0_Low_Decode 0x0008 55 #define GT_SCS0_High_Decode 0x0010 56 #define GT_SCS1_Low_Decode 0x0208 57 #define GT_SCS1_High_Decode 0x0210 58 #define GT_SCS2_Low_Decode 0x0018 59 #define GT_SCS2_High_Decode 0x0020 60 #define GT_SCS3_Low_Decode 0x0218 61 #define GT_SCS3_High_Decode 0x0220 62 #define GT_CS0_Low_Decode 0x0028 63 #define GT_CS0_High_Decode 0x0030 64 #define GT_CS1_Low_Decode 0x0228 65 #define GT_CS1_High_Decode 0x0230 66 #define GT_CS2_Low_Decode 0x0248 67 #define GT_CS2_High_Decode 0x0250 68 #define GT_CS3_Low_Decode 0x0038 69 #define GT_CS3_High_Decode 0x0040 70 #define GT_BootCS_Low_Decode 0x0238 71 #define GT_BootCS_High_Decode 0x0240 72 #define GT_PCI0_IO_Low_Decode 0x0048 73 #define GT_PCI0_IO_High_Decode 0x0050 74 #define GT_PCI0_Mem0_Low_Decode 0x0058 75 #define GT_PCI0_Mem0_High_Decode 0x0060 76 #define GT_PCI0_Mem1_Low_Decode 0x0080 77 #define GT_PCI0_Mem1_High_Decode 0x0088 78 #define GT_PCI0_Mem2_Low_Decode 0x0258 79 #define GT_PCI0_Mem2_High_Decode 0x0260 80 #define GT_PCI0_Mem3_Low_Decode 0x0280 81 #define GT_PCI0_Mem3_High_Decode 0x0288 82 #define GT_PCI1_IO_Low_Decode 0x0090 83 #define GT_PCI1_IO_High_Decode 0x0098 84 #define GT_PCI1_Mem0_Low_Decode 0x00a0 85 #define GT_PCI1_Mem0_High_Decode 0x00a8 86 #define GT_PCI1_Mem1_Low_Decode 0x00b0 87 #define GT_PCI1_Mem1_High_Decode 0x00b8 88 #define GT_PCI1_Mem2_Low_Decode 0x02a0 89 #define GT_PCI1_Mem2_High_Decode 0x02a8 90 #define GT_PCI1_Mem3_Low_Decode 0x02b0 91 #define GT_PCI1_Mem3_High_Decode 0x02b8 92 #define GT_Internal_Decode 0x0068 93 #define GT_CPU0_Low_Decode 0x0290 94 #define GT_CPU0_High_Decode 0x0298 95 #define GT_CPU1_Low_Decode 0x02c0 96 #define GT_CPU1_High_Decode 0x02c8 97 #define GT_PCI0_IO_Remap 0x00f0 98 #define GT_PCI0_Mem0_Remap_Low 0x00f8 99 #define GT_PCI0_Mem0_Remap_High 0x0320 100 #define GT_PCI0_Mem1_Remap_Low 0x0100 101 #define GT_PCI0_Mem1_Remap_High 0x0328 102 #define GT_PCI0_Mem2_Remap_Low 0x02f8 103 #define GT_PCI0_Mem2_Remap_High 0x0330 104 #define GT_PCI0_Mem3_Remap_Low 0x0300 105 #define GT_PCI0_Mem3_Remap_High 0x0338 106 #define GT_PCI1_IO_Remap 0x0108 107 #define GT_PCI1_Mem0_Remap_Low 0x0110 108 #define GT_PCI1_Mem0_Remap_High 0x0340 109 #define GT_PCI1_Mem1_Remap_Low 0x0118 110 #define GT_PCI1_Mem1_Remap_High 0x0348 111 #define GT_PCI1_Mem2_Remap_Low 0x0310 112 #define GT_PCI1_Mem2_Remap_High 0x0350 113 #define GT_PCI1_Mem3_Remap_Low 0x0318 114 #define GT_PCI1_Mem3_Remap_High 0x0358 115 116 117 /* 118 * Table 31: CPU Control Register Map 119 */ 120 #define GT_CPU_Cfg 0x0000 121 #define GT_CPU_Mode 0x0120 122 #define GT_CPU_Master_Ctl 0x0160 123 #define GT_CPU_If_Xbar_Ctl_Low 0x0150 124 #define GT_CPU_If_Xbar_Ctl_High 0x0158 125 #define GT_CPU_If_Xbar_Timeout 0x0168 126 #define GT_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 127 #define GT_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 128 129 /* 130 * Table 32: CPU Sync Barrier Register Map 131 */ 132 #define GT_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) 133 #define GT_PCI0_Sync_Barrier 0x00c0 134 #define GT_PCI1_Sync_Barrier 0x00c8 135 136 /* 137 * Table 33: CPU Access Protection Register Map 138 */ 139 #define GT_Protect_Low_0 0x0180 140 #define GT_Protect_High_0 0x0188 141 #define GT_Protect_Low_1 0x0190 142 #define GT_Protect_High_1 0x0198 143 #define GT_Protect_Low_2 0x01a0 144 #define GT_Protect_High_2 0x01a8 145 #define GT_Protect_Low_3 0x01b0 146 #define GT_Protect_High_3 0x01b8 147 #define GT_Protect_Low_4 0x01c0 148 #define GT_Protect_High_4 0x01c8 149 #define GT_Protect_Low_5 0x01d0 150 #define GT_Protect_High_5 0x01d8 151 #define GT_Protect_Low_6 0x01e0 152 #define GT_Protect_High_6 0x01e8 153 #define GT_Protect_Low_7 0x01f0 154 #define GT_Protect_High_7 0x01f8 155 156 /* 157 * Table 34: Snoop Control Register Map 158 */ 159 #define GT_Snoop_Base_0 0x0380 160 #define GT_Snoop_Top_0 0x0388 161 #define GT_Snoop_Base_1 0x0390 162 #define GT_Snoop_Top_1 0x0398 163 #define GT_Snoop_Base_2 0x03a0 164 #define GT_Snoop_Top_2 0x03a8 165 #define GT_Snoop_Base_3 0x03b0 166 #define GT_Snoop_Top_3 0x03b8 167 168 /* 169 * Table 35: CPU Error Report Register Map 170 */ 171 #define GT_CPU_Error_Address_Low 0x0070 172 #define GT_CPU_Error_Address_High 0x0078 173 #define GT_CPU_Error_Data_Low 0x0128 174 #define GT_CPU_Error_Data_High 0x0130 175 #define GT_CPU_Error_Parity 0x0138 176 #define GT_CPU_Error_Cause 0x0140 177 #define GT_CPU_Error_Mask 0x0148 178 179 #define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) 180 #define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) 181 182 #define GT_MPP_Control0 0xf000 183 #define GT_MPP_Control1 0xf004 184 #define GT_MPP_Control2 0xf008 185 #define GT_MPP_Control3 0xf00c 186 187 #define GT_GPP_IO_Control 0xf100 188 #define GT_GPP_Value 0xf104 189 #define GT_GPP_Interrupt_Cause 0xf108 190 #define GT_GPP_Interrupt_Mask 0xf10c 191 #define GT_GPP_Level_Control 0xf110 192 #define GT_GPP_Interrupt_Mask1 0xf114 193 #define GT_GPP_Value_Set 0xf118 194 #define GT_GPP_Value_Clear 0xf11c 195 /* 196 * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 197 * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 198 * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 199 * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 200 * Table 44: CS[0]* Low Decode Address, Offset: 0x028 201 * Table 46: CS[1]* Low Decode Address, Offset: 0x228 202 * Table 48: CS[2]* Low Decode Address, Offset: 0x248 203 * Table 50: CS[3]* Low Decode Address, Offset: 0x038 204 * Table 52: BootCS* Low Decode Address, Offset: 0x238 205 * Table 75: CPU 0 Low Decode Address, Offset: 0x290 206 * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 207 * 208 * 11:00 LowAddr SCS[0] Base Address 209 * 31:12 Reserved Must be 0. 210 */ 211 212 /* 213 * Table 37: SCS[0]* High Decode Address, Offset: 0x010 214 * Table 39: SCS[1]* High Decode Address, Offset: 0x210 215 * Table 41: SCS[2]* High Decode Address, Offset: 0x020 216 * Table 43: SCS[3]* High Decode Address, Offset: 0x220 217 * Table 45: CS[0]* High Decode Address, Offset: 0x030 218 * Table 47: CS[1]* High Decode Address, Offset: 0x230 219 * Table 49: CS[2]* High Decode Address, Offset: 0x250 220 * Table 51: CS[3]* High Decode Address, Offset: 0x040 221 * Table 53: BootCS* High Decode Address, Offset: 0x240 222 * Table 76: CPU 0 High Decode Address, Offset: 0x298 223 * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 224 * 225 * 11:00 HighAddr SCS[0] Top Address 226 * 31:12 Reserved 227 */ 228 229 /* 230 * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 231 * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 232 * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 233 * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 234 * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 235 * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 236 * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 237 * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 238 * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 239 * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 240 * 241 * 11:00 LowAddr PCI IO/Memory Space Base Address 242 * 23:12 Reserved 243 * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; 244 * 1: No swapping; 2: Both byte and word swap; 245 * 3: Word swap; 4..7: Reserved) 246 * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when 247 * configured to 64-bit PCI bus and not I/O) 248 * 0: Assert s REQ64* only when transaction 249 * is longer than 64-bits. 250 * 1: Always assert REQ64*. 251 * 31:28 Reserved 252 */ 253 #define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) 254 #define GT_PCISwap_ByteSwap 0 255 #define GT_PCISwap_NoSwap 1 256 #define GT_PCISwap_ByteWordSwap 2 257 #define GT_PCISwap_WordSwap 3 258 #define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) 259 260 /* 261 * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 262 * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 263 * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 264 * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 265 * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 266 * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 267 * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 268 * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 269 * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 270 * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 271 * 272 * 11:00 HighAddr PCI_0 I/O Space Top Address 273 * 31:12 Reserved 274 */ 275 276 /* 277 * Table 74: Internal Space Decode, Offset: 0x068 278 * 15:00 IntDecode GT64260 Internal Space Base Address 279 * 23:16 Reserved 280 * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. 281 * NOTE: Reserved for Galileo Technology usage. 282 * Relevant only for PCI master configuration 283 * transactions on the PCI bus. 284 * 31:27 Reserved 285 */ 286 287 /* 288 * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 289 * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 290 * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 291 * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 292 * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 293 * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 294 * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 295 * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 296 * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 297 * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 298 * 299 * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) 300 * 31:12 Reserved 301 */ 302 303 /* 304 * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 305 * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 306 * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 307 * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 308 * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 309 * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 310 * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 311 * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 312 * 313 * 31:00 Remap PCI Memory Address Remap (high 32 bits) 314 */ 315 316 /* 317 * Table 97: CPU Configuration, Offset: 0x000 318 * 07:00 NoMatchCnt CPU Address Miss Counter 319 * 08:08 NoMatchCntEn CPU Address Miss Counter Enable 320 * NOTE: Relevant only if multi-GT is enabled. 321 * (0: Disabled; 1: Enabled) 322 * 09:09 NoMatchCntExt CPU address miss counter MSB 323 * 10:10 Reserved 324 * 11:11 AACKDelay Address Acknowledge Delay 325 * 0: AACK* is asserted one cycle after TS*. 326 * 1: AACK* is asserted two cycles after TS*. 327 * 12:12 Endianess Must be 0 328 * NOTE: The GT64260 does not support the PowerPC 329 * Little Endian convention 330 * 13:13 Pipeline Pipeline Enable 331 * 0: Disabled. The GT64260 will not respond with 332 * AACK* to a new CPU transaction, before the 333 * previous transaction data phase completes. 334 * 1: Enabled. 335 * 14:14 Reserved 336 * 15:15 TADelay Transfer Acknowledge Delay 337 * 0: TA* is asserted one cycle after AACK* 338 * 1: TA* is asserted two cycles after AACK* 339 * 16:16 RdOOO Read Out of Order Completion 340 * 0: Not Supported, Data is always returned in 341 * order (DTI[0-2] is always driven 342 * 1: Supported 343 * 17:17 StopRetry Relevant only if PCI Retry is enabled 344 * 0: Keep Retry all PCI transactions targeted 345 * to the GT64260. 346 * 1: Stop Retry of PCI transactions. 347 * 18:18 MultiGTDec Multi-GT Address Decode 348 * 0: Normal address decoding 349 * 1: Multi-GT address decoding 350 * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... 351 * 0: is not checked. (Not connected) 352 * 1: is checked (Connected) 353 * 21:20 Reserved 354 * 22:22 PErrProp Parity Error Propagation 355 * 0: GT64260 always drives good parity on 356 * DP[0-7] during CPU reads. 357 * 1: GT64260 drives bad parity on DP[0-7] in case 358 * the read response from the target interface 359 * comes with erroneous data indication 360 * (e.g. ECC error from SDRAM interface). 361 * 25:23 Reserved 362 * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... 363 * 0: is not checked. (Not connected) 364 * 1: is checked (Connected) 365 * 27:27 RemapWrDis Address Remap Registers Write Control 366 * 0: Write to Low Address decode register. 367 * Results in writing of the corresponding 368 * Remap register. 369 * 1: Write to Low Address decode register. No 370 * affect on the corresponding Remap register. 371 * 28:28 ConfSBDis Configuration Read Sync Barrier Disable 372 * 0: enabled; 1: disabled 373 * 29:29 IOSBDis I/O Read Sync Barrier Disable 374 * 0: enabled; 1: disabled 375 * 30:30 ClkSync Clocks Synchronization 376 * 0: The CPU interface is running with SysClk, 377 * which is asynchronous to TClk. 378 * 1: The CPU interface is running with TClk. 379 * 31:31 Reserved 380 */ 381 #define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) 382 #define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) 383 #define GT_CPUCfg_NoMatchCntExt GT__BIT(10) 384 #define GT_CPUCfg_AACKDelay GT__BIT(11) 385 #define GT_CPUCfg_Endianess GT__BIT(12) 386 #define GT_CPUCfg_Pipeline GT__BIT(13) 387 #define GT_CPUCfg_TADelay GT__BIT(15) 388 #define GT_CPUCfg_RdOOO GT__BIT(16) 389 #define GT_CPUCfg_StopRetry GT__BIT(17) 390 #define GT_CPUCfg_MultiGTDec GT__BIT(18) 391 #define GT_CPUCfg_DPValid GT__BIT(19) 392 #define GT_CPUCfg_PErrProp GT__BIT(22) 393 #define GT_CPUCfg_APValid GT__BIT(26) 394 #define GT_CPUCfg_RemapWrDis GT__BIT(27) 395 #define GT_CPUCfg_ConfSBDis GT__BIT(28) 396 #define GT_CPUCfg_IOSBDis GT__BIT(29) 397 #define GT_CPUCfg_ClkSync GT__BIT(30) 398 399 /* 400 * Table 98: CPU Mode, Offset: 0x120, Read only 401 * 01:00 MultiGTID Multi-GT ID 402 * Represents the ID to which the GT64260 responds 403 * to during a multi-GT address decoding period. 404 * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration 405 * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions 406 * 07:04 CPUType 407 * 0x0-0x3: Reserved 408 * 0x4: 64-bit PowerPC CPU, 60x bus 409 * 0x5: 64-bit PowerPC CPU, MPX bus 410 * 0x6-0xf: Reserved 411 * 31:08 Reserved 412 */ 413 #define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) 414 #define GT_CPUMode_MultiGT GT__BIT(2) 415 #define GT_CPUMode_RetryEn GT__BIT(3) 416 #define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) 417 418 /* 419 * Table 99: CPU Master Control, Offset: 0x160 420 * 07:00 Reserved 421 * 08:08 IntArb CPU Bus Internal Arbiter Enable 422 * NOTE: Only relevant to 60x bus mode. When 423 * running MPX bus, the GT64260 internal 424 * arbiter must be used. 425 * 0: Disabled. External arbiter is required. 426 * 1: Enabled. Use the GT64260 CPU bus arbiter. 427 * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control 428 * NOTE: This bit must be set to 1. It is reserved 429 * for Galileo Technology usage. 430 * 0: Enable internal bus sharing between master 431 * and slave interfaces. 432 * 1: Disable internal bus sharing between master 433 * and slave interfaces. 434 * 10:10 MWrTrig Master Write Transaction Trigger 435 * 0: With first valid write data 436 * 1: With last valid write data 437 * 11:11 MRdTrig Master Read Response Trigger 438 * 0: With first valid read data 439 * 1: With last valid read data 440 * 12:12 CleanBlock Clean Block Snoop Transaction Support 441 * 0: CPU does not support clean block (603e,750) 442 * 1: CPU supports clean block (604e,G4) 443 * 13:13 FlushBlock Flush Block Snoop Transaction Support 444 * 0: CPU does not support flush block (603e,750) 445 * 1: CPU supports flush block (604e,G4) 446 * 31:14 Reserved 447 */ 448 #define GT_CPUMstrCtl_IntArb GT__BIT(8) 449 #define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) 450 #define GT_CPUMstrCtl_MWrTrig GT__BIT(10) 451 #define GT_CPUMstrCtl_MRdTrig GT__BIT(11) 452 #define GT_CPUMstrCtl_CleanBlock GT__BIT(12) 453 #define GT_CPUMstrCtl_FlushBlock GT__BIT(13) 454 455 #define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ 456 #define GT_ArbSlice_DEVICE 0x1 /* Device request */ 457 #define GT_ArbSlice_NULL 0x2 /* NULL request */ 458 #define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ 459 #define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ 460 #define GT_ArbSlice_COMM 0x5 /* Comm unit access */ 461 #define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ 462 #define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ 463 /* 0x8-0xf: Reserved */ 464 465 /* Pass in the slice number (from 0..16) as 'n' 466 */ 467 #define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) 468 469 /* 470 * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 471 * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter 472 * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter 473 * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter 474 * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter 475 * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter 476 * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter 477 * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter 478 * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter 479 */ 480 481 /* 482 * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 483 * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter 484 * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter 485 * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter 486 * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter 487 * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter 488 * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter 489 * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter 490 * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter 491 */ 492 493 /* 494 * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 495 * NOTE: Reserved for Galileo Technology usage. 496 * 07:00 Timeout Crossbar Arbiter Timeout Preset Value 497 * 15:08 Reserved 498 * 16:16 TimeoutEn Crossbar Arbiter Timer Enable 499 * (0: Enable; 1: Disable) 500 * 31:17 Reserved 501 */ 502 503 /* 504 * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 505 * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter 506 * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter 507 * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter 508 * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter 509 * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter 510 * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter 511 * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter 512 * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter 513 */ 514 /* 515 * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 516 * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter 517 * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter 518 * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter 519 * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter 520 * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter 521 * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter 522 * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter 523 * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter 524 */ 525 526 /* 527 * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 528 * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 529 * NOTE: The read data is random and should be ignored. 530 * 31:00 SyncBarrier A CPU read from this register creates a 531 * synchronization barrier cycle. 532 */ 533 534 /* 535 * Table 107: CPU Protect Address 0 Low, Offset: 0x180 536 * Table 109: CPU Protect Address 1 Low, Offset: 0x190 537 * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 538 * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 539 * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 540 * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 541 * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 542 * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 543 * 544 * 11:00 LowAddr CPU Protect Region Base Address 545 * Corresponds to address bits[31:20]. 546 * 15:12 Reserved. Must be 0 547 * 16:16 AccProtect CPU Access Protect 548 * Access is (0: allowed; 1: forbidden) 549 * 17:17 WrProtect CPU Write Protect 550 * Writes are (0: allowed; 1: forbidden) 551 * 18:18 CacheProtect CPU caching protect. Caching (block read) 552 * is (0: allowed; 1: forbidden) 553 * 31:19 Reserved 554 */ 555 #define GT_CPU_AccProtect GT__BIT(16) 556 #define GT_CPU_WrProtect GT__BIT(17) 557 #define GT_CPU_CacheProtect GT__BIT(18) 558 559 /* 560 * Table 108: CPU Protect Address 0 High, Offset: 0x188 561 * Table 110: CPU Protect Address 1 High, Offset: 0x198 562 * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 563 * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 564 * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 565 * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 566 * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 567 * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 568 * 569 * 11:00 HighAddr CPU Protect Region Top Address 570 * Corresponds to address bits[31:20] 571 * 31:12 Reserved 572 */ 573 574 /* 575 * Table 123: Snoop Base Address 0, Offset: 0x380 576 * Table 125: Snoop Base Address 1, Offset: 0x390 577 * Table 127: Snoop Base Address 2, Offset: 0x3a0 578 * Table 129: Snoop Base Address 3, Offset: 0x3b0 579 * 580 * 11:00 LowAddr Snoop Region Base Address [31:20] 581 * 15:12 Reserved Must be 0. 582 * 17:16 Snoop Snoop Type 583 * 0x0: No Snoop 584 * 0x1: Snoop to WT region 585 * 0x2: Snoop to WB region 586 * 0x3: Reserved 587 * 31:18 Reserved 588 */ 589 #define GT_Snoop_GET(v) GT__EXT((v), 16, 2) 590 #define GT_Snoop_INS(v) GT__INS((v), 16) 591 #define GT_Snoop_None 0 592 #define GT_Snoop_WT 1 593 #define GT_Snoop_WB 2 594 595 596 /* 597 * Table 124: Snoop Top Address 0, Offset: 0x388 598 * Table 126: Snoop Top Address 1, Offset: 0x398 599 * Table 128: Snoop Top Address 2, Offset: 0x3a8 600 * Table 130: Snoop Top Address 3, Offset: 0x3b8 601 * 11:00 HighAddr Snoop Region Top Address [31:20] 602 * 31:12 Reserved 603 */ 604 605 606 /* 607 * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. 608 * In case of multiple errors, only the first one is latched. New error 609 * report latching is enabled only after the CPU Error Address Low register 610 * is being read. 611 * 31:00 ErrAddr Latched address bits [31:0] of a CPU 612 * transaction in case of: 613 * o illegal address (failed address decoding) 614 * o access protection violation 615 * o bad data parity 616 * o bad address parity 617 * Upon address latch, no new address are 618 * registered (due to additional error condition), 619 * until the register is being read. 620 */ 621 622 /* 623 * Table 132: CPU Error Address High, Offset: 0x078, Read Only. 624 * Once data is latched, no new data can be registered (due to additional 625 * error condition), until CPU Error Low Address is being read (which 626 * implies, it should be the last being read by the interrupt handler). 627 * 03:00 Reserved 628 * 07:04 ErrPar Latched address parity bits in case 629 * of bad CPU address parity detection. 630 * 31:08 Reserved 631 */ 632 #define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) 633 634 /* 635 * Table 133: CPU Error Data Low, Offset: 0x128, Read only. 636 * 31:00 PErrData Latched data bits [31:0] in case of bad data 637 * parity sampled on write transactions or on 638 * master read transactions. 639 */ 640 641 /* 642 * Table 134: CPU Error Data High, Offset: 0x130, Read only. 643 * 31:00 PErrData Latched data bits [63:32] in case of bad data 644 * parity sampled on write transactions or on 645 * master read transactions. 646 */ 647 648 /* 649 * Table 135: CPU Error Parity, Offset: 0x138, Read only. 650 * 07:00 PErrPar Latched data parity bus in case of bad data 651 * parity sampled on write transactions or on 652 * master read transactions. 653 * 31:10 Reserved 654 */ 655 #define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) 656 657 /* 658 * Table 136: CPU Error Cause, Offset: 0x140 659 * Bits[7:0] are clear only. A cause bit is set upon an error condition 660 * occurrence. Write a 0 value to clear the bit. Writing a 1 value has 661 * no affect. 662 * 00:00 AddrOut CPU Address Out of Range 663 * 01:01 AddrPErr Bad Address Parity Detected 664 * 02:02 TTErr Transfer Type Violation. 665 * The CPU attempts to burst (read or write) to an 666 * internal register. 667 * 03:03 AccErr Access to a Protected Region 668 * 04:04 WrErr Write to a Write Protected Region 669 * 05:05 CacheErr Read from a Caching protected region 670 * 06:06 WrDataPErr Bad Write Data Parity Detected 671 * 07:07 RdDataPErr Bad Read Data Parity Detected 672 * 26:08 Reserved 673 * 31:27 Sel Specifies the error event currently being 674 * reported in Error Address, Error Data, and 675 * Error Parity registers. 676 * 0x0: AddrOut 677 * 0x1: AddrPErr 678 * 0x2: TTErr 679 * 0x3: AccErr 680 * 0x4: WrErr 681 * 0x5: CacheErr 682 * 0x6: WrDataPErr 683 * 0x7: RdDataPErr 684 * 0x8-0x1f: Reserved 685 */ 686 #define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) 687 #define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) 688 #define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) 689 #define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) 690 #define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) 691 #define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) 692 #define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) 693 #define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) 694 695 #define GT_CPUError_Sel_AddrOut 0 696 #define GT_CPUError_Sel_AddrPErr 1 697 #define GT_CPUError_Sel_TTErr 2 698 #define GT_CPUError_Sel_AccErr 3 699 #define GT_CPUError_Sel_WrErr 4 700 #define GT_CPUError_Sel_CacheErr 5 701 #define GT_CPUError_Sel_WrDataPErr 6 702 #define GT_CPUError_Sel_RdDataPErr 7 703 704 #define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) 705 706 /* 707 * Table 137: CPU Error Mask, Offset: 0x148 708 * 00:00 AddrOut If set to 1, enables AddrOut interrupt. 709 * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. 710 * 02:02 TTErr If set to 1, enables TTErr interrupt. 711 * 03:03 AccErr If set to 1, enables AccErr interrupt. 712 * 04:04 WrErr If set to 1, enables WrErr interrupt. 713 * 05:05 CacheErr If set to 1, enables CacheErr interrupt. 714 * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. 715 * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. 716 * 31:08 Reserved 717 */ 718 719 /* 720 * Comm Unit Interrupt registers 721 */ 722 #define GT_CommUnitIntr_Cause 0xf310 723 #define GT_CommUnitIntr_Mask 0xf314 724 #define GT_CommUnitIntr_ErrAddr 0xf318 725 726 #define GT_CommUnitIntr_E0 0x00000007 727 #define GT_CommUnitIntr_E1 0x00000070 728 #define GT_CommUnitIntr_E2 0x00000700 729 #define GT_CommUnitIntr_S0 0x00070000 730 #define GT_CommUnitIntr_S1 0x00700000 731 #define GT_CommUnitIntr_Sel 0x70000000 732 733 /* 734 * SDRAM Error Report (ECC) Registers 735 */ 736 #define GT_ECC_Data_Lo 0x484 /* latched Error Data (low) */ 737 #define GT_ECC_Data_Hi 0x480 /* latched Error Data (high) */ 738 #define GT_ECC_Addr 0x490 /* latched Error Address */ 739 #define GT_ECC_Rec 0x488 /* latched ECC code from SDRAM */ 740 #define GT_ECC_Calc 0x48c /* latched ECC code from SDRAM */ 741 #define GT_ECC_Ctl 0x494 /* ECC Control */ 742 #define GT_ECC_Count 0x498 /* ECC 1-bit error count */ 743 744 /* 745 * Watchdog Registers 746 */ 747 #define GT_WDOG_Config 0xb410 748 #define GT_WDOG_Value 0xb414 749 #define GT_WDOG_Value_NMI GT__MASK(24) 750 #define GT_WDOG_Config_Preset GT__MASK(24) 751 #define GT_WDOG_Config_Ctl1a GT__BIT(24) 752 #define GT_WDOG_Config_Ctl1b GT__BIT(25) 753 #define GT_WDOG_Config_Ctl2a GT__BIT(26) 754 #define GT_WDOG_Config_Ctl2b GT__BIT(27) 755 #define GT_WDOG_Config_Enb GT__BIT(31) 756 757 #define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) 758 #define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) 759 760 /* 761 * Device Bus Interrupts 762 */ 763 #define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ 764 #define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ 765 #define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ 766 767 /* 768 * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK 769 */ 770 #define GT_DEVBUS_DBurstErr GT__BIT(0) 771 #define GT_DEVBUS_DRdyErr GT__BIT(1) 772 #define GT_DEVBUS_Sel GT__BIT(27) 773 #define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) 774 775 776 #define ETH0_BASE 0x2400 777 #define ETH1_BASE 0x2800 778 #define ETH2_BASE 0x2c00 779 #define MPSC0_BASE 0x8000 780 #define MPSC1_BASE 0x9000 781 782 #endif /* !_DISCOVERY_DEV_GTREG_H */ 783
Indexes created Mon Sep 29 21:09:56 GMT 2025