gtsdmareg.h revision 1.5
1 /* $NetBSD: gtsdmareg.h,v 1.5 2010/04/28 13:51:56 kiyohara Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * gtsdmareg.h - register defines for GT-64260 SDMA 42 * 43 * creation Sun Apr 8 20:22:51 PDT 2001 cliff 44 */ 45 46 #ifndef _GTSDMAREG_H 47 #define _GTSDMAREG_H 48 49 #ifndef BIT 50 #define BIT(bitno) (1U << (bitno)) 51 #endif 52 #ifndef BITS 53 #define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo))) 54 #endif 55 56 #define GTSDMA_BASE(u) ((u) == 0 ? 0x4000 : 0x6000) 57 #define GTSDMA_SIZE 0x1000 58 59 /******************************************************************************* 60 * 61 * SDMA register address offsets relative to the base mapping 62 */ 63 #define SDMA_SDC 0x000 /* SDMA Configuration Register */ 64 #define SDMA_SDCM 0x008 /* SDMA Command Register */ 65 #define SDMA_SCRDP 0x810 /* SDMA Current RX Desc. Pointer */ 66 #define SDMA_SCTDP 0xc10 /* SDMA Current TX Desc. Pointer */ 67 #define SDMA_SFTDP 0xc14 /* SDMA First TX Desc. Pointer */ 68 69 #define SDMA_ICAUSE 0xb800 /* Interrupt Cause Register */ 70 #define SDMA_IMASK 0xb880 /* Interrupt Mask Register */ 71 72 73 /******************************************************************************* 74 * 75 * SDMA register values and bit definitions 76 */ 77 /* 78 * SDMA Configuration Register 79 */ 80 #define SDMA_SDC_RFT BIT(0) /* RX FIFO Threshold */ 81 #define SDMA_SDC_SFM BIT(1) /* Single Frame Mode */ 82 #define SDMA_SDC_RC_MASK BITS(5,2) /* Re-TX count */ 83 #define SDMA_SDC_RC_SHIFT 2 84 #define SDMA_SDC_BLMR BIT(6) /* RX Big=0 Lil=1 Endian mode */ 85 #define SDMA_SDC_BLMT BIT(7) /* TX Big=0 Lil=1 Endian mode */ 86 #define SDMA_SDC_POVR BIT(8) /* PCI Override */ 87 #define SDMA_SDC_RIFB BIT(9) /* RX Intr on Frame boundaries */ 88 #define SDMA_SDC_RESa BITS(11,10) 89 #define SDMA_SDC_BSZ_MASK BITS(13,12) /* Maximum Burst Size */ 90 #define SDMA_SDC_BSZ_1x64 (0 << 12) /* 1 64 bit word */ 91 #define SDMA_SDC_BSZ_2x64 (1 << 12) /* 2 64 bit words */ 92 #define SDMA_SDC_BSZ_4x64 (2 << 12) /* 4 64 bit words */ 93 #define SDMA_SDC_BSZ_8x64 (3 << 12) /* 8 64 bit words */ 94 #define SDMA_SDC_RESb BITS(31,14) 95 #define SDMA_SDC_RES (SDMA_SDC_RESa|SDMA_SDC_RESb) 96 /* 97 * SDMA Command Register 98 */ 99 #define SDMA_SDCM_RESa BITS(6,0) 100 #define SDMA_SDCM_ERD BIT(7) /* Enable RX DMA */ 101 #define SDMA_SDCM_RESb BITS(14,8) 102 #define SDMA_SDCM_AR BIT(15) /* Abort Receive */ 103 #define SDMA_SDCM_STD BIT(16) /* Stop TX */ 104 #define SDMA_SDCM_RESc BITS(22,17) 105 #define SDMA_SDCM_TXD BIT(23) /* TX Demand */ 106 #define SDMA_SDCM_RESd BITS(30,24) 107 #define SDMA_SDCM_AT BIT(31) /* Abort TX */ 108 #define SDMA_SDCM_RES \ 109 (SDMA_SDCM_RESa|SDMA_SDCM_RESb|SDMA_SDCM_RESc|SDMA_SDCM_RESd) 110 /* 111 * SDMA Interrupt Cause and Mask Register bits 112 */ 113 #define U__(bits,u) ((bits) << (((u) % 2) * 8)) 114 #define SDMA_INTR_RXBUF(u) U__(BIT(0),u) /* SDMA #0 Rx Buffer Return */ 115 #define SDMA_INTR_RXERR(u) U__(BIT(1),u) /* SDMA #0 Rx Error */ 116 #define SDMA_INTR_TXBUF(u) U__(BIT(2),u) /* SDMA #0 Tx Buffer Return */ 117 #define SDMA_INTR_TXEND(u) U__(BIT(3),u) /* SDMA #0 Tx End */ 118 #define SDMA_INTR_RESa BITS(7,4) 119 #define SDMA_INTR_RESb BITS(31,12) 120 #define SDMA_INTR_RES (SDMA_INTR_RESa|SDMA_INTR_RESb) 121 #define SDMA_U_INTR_MASK(u) U__(BITS(3,0),u) 122 123 124 /******************************************************************************* 125 * 126 * SDMA descriptor structure and definitions 127 */ 128 /* 129 * SDMA descriptor structure used for both TX and RX 130 * the `sdma_csr' and `sdma_cnt' fields differ for RX and TX 131 * `sdma_csr' varies depending on how it is tasked; 132 * see "gtmpscreg.h" for defines on SDMA descriptor CSR values 133 * for MPSC UART mode. Note that pointer fields are physical addrs. 134 */ 135 typedef struct sdma_desc { 136 uint32_t sdma_cnt; /* size (rx) or shadow (tx) and count */ 137 uint32_t sdma_csr; /* command/status */ 138 uint32_t sdma_next; /* next descriptor link */ 139 uint32_t sdma_bufp; /* buffer pointer */ 140 } sdma_desc_t; 141 142 #define SDMA_RX_CNT_BCNT_SHIFT 0 /* byte count */ 143 #define SDMA_RX_CNT_BCNT_MASK BITS(15,0) /* " " */ 144 #define SDMA_RX_CNT_BUFSZ_SHIFT 16 /* buffer size */ 145 #define SDMA_RX_CNT_BUFSZNT_SIZE_MASK BITS(31,19) /* " " */ 146 #define SDMA_RX_CNT_BUFP_MASK BITS(31,3) /* buffer pointer */ 147 #define SDMA_RX_CNT_NEXT_MASK BITS(31,4) /* next desc. pointer */ 148 149 #define SDMA_TX_CNT_SBC_SHIFT 0 /* shadow byte count */ 150 #define SDMA_TX_CNT_SBC_MASK BITS(15,0) /* " " " */ 151 #define SDMA_TX_CNT_BCNT_SHIFT 16 /* byte count */ 152 #define SDMA_TX_CNT_BCNT_MASK BITS(31,16 /* " " */ 153 #define SDMA_TX_CNT_NEXT_MASK BITS(31,4) /* next desc. pointer */ 154 155 156 #endif /* _GTSDMAREG_H */ 157
Indexes created Sat Nov 01 21:09:44 GMT 2025