gttwsi.c revision 1.1.4.2 1 1.1.4.2 rmind /* $NetBSD: gttwsi.c,v 1.1.4.2 2010/05/30 05:17:30 rmind Exp $ */
2 1.1.4.2 rmind /*
3 1.1.4.2 rmind * Copyright (c) 2008 Eiji Kawauchi.
4 1.1.4.2 rmind * All rights reserved.
5 1.1.4.2 rmind *
6 1.1.4.2 rmind * Redistribution and use in source and binary forms, with or without
7 1.1.4.2 rmind * modification, are permitted provided that the following conditions
8 1.1.4.2 rmind * are met:
9 1.1.4.2 rmind * 1. Redistributions of source code must retain the above copyright
10 1.1.4.2 rmind * notice, this list of conditions and the following disclaimer.
11 1.1.4.2 rmind * 2. Redistributions in binary form must reproduce the above copyright
12 1.1.4.2 rmind * notice, this list of conditions and the following disclaimer in the
13 1.1.4.2 rmind * documentation and/or other materials provided with the distribution.
14 1.1.4.2 rmind * 3. All advertising materials mentioning features or use of this software
15 1.1.4.2 rmind * must display the following acknowledgement:
16 1.1.4.2 rmind * This product includes software developed for the NetBSD Project by
17 1.1.4.2 rmind * Eiji Kawauchi.
18 1.1.4.2 rmind * 4. The name of the author may not be used to endorse or promote products
19 1.1.4.2 rmind * derived from this software without specific prior written permission
20 1.1.4.2 rmind *
21 1.1.4.2 rmind * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.1.4.2 rmind * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.1.4.2 rmind * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.1.4.2 rmind * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.1.4.2 rmind * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.1.4.2 rmind * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.1.4.2 rmind * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.1.4.2 rmind * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.1.4.2 rmind * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.1.4.2 rmind * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.1.4.2 rmind */
32 1.1.4.2 rmind /*
33 1.1.4.2 rmind * Copyright (c) 2005 Brocade Communcations, inc.
34 1.1.4.2 rmind * All rights reserved.
35 1.1.4.2 rmind *
36 1.1.4.2 rmind * Written by Matt Thomas for Brocade Communcations, Inc.
37 1.1.4.2 rmind *
38 1.1.4.2 rmind * Redistribution and use in source and binary forms, with or without
39 1.1.4.2 rmind * modification, are permitted provided that the following conditions
40 1.1.4.2 rmind * are met:
41 1.1.4.2 rmind * 1. Redistributions of source code must retain the above copyright
42 1.1.4.2 rmind * notice, this list of conditions and the following disclaimer.
43 1.1.4.2 rmind * 2. Redistributions in binary form must reproduce the above copyright
44 1.1.4.2 rmind * notice, this list of conditions and the following disclaimer in the
45 1.1.4.2 rmind * documentation and/or other materials provided with the distribution.
46 1.1.4.2 rmind * 3. The name of Brocade Communications, Inc. may not be used to endorse
47 1.1.4.2 rmind * or promote products derived from this software without specific prior
48 1.1.4.2 rmind * written permission.
49 1.1.4.2 rmind *
50 1.1.4.2 rmind * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
51 1.1.4.2 rmind * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 1.1.4.2 rmind * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 1.1.4.2 rmind * ARE DISCLAIMED. IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
54 1.1.4.2 rmind * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 1.1.4.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 1.1.4.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 1.1.4.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 1.1.4.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 1.1.4.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
60 1.1.4.2 rmind * OF THE POSSIBILITY OF SUCH DAMAGE.
61 1.1.4.2 rmind */
62 1.1.4.2 rmind //#define TWSI_DEBUG
63 1.1.4.2 rmind
64 1.1.4.2 rmind /*
65 1.1.4.2 rmind * Marvell Two-Wire Serial Interface (aka I2C) master driver
66 1.1.4.2 rmind */
67 1.1.4.2 rmind
68 1.1.4.2 rmind #include <sys/cdefs.h>
69 1.1.4.2 rmind __KERNEL_RCSID(0, "$NetBSD: gttwsi.c,v 1.1.4.2 2010/05/30 05:17:30 rmind Exp $");
70 1.1.4.2 rmind #include "locators.h"
71 1.1.4.2 rmind
72 1.1.4.2 rmind #include <sys/param.h>
73 1.1.4.2 rmind #include <sys/bus.h>
74 1.1.4.2 rmind #include <sys/condvar.h>
75 1.1.4.2 rmind #include <sys/device.h>
76 1.1.4.2 rmind #include <sys/errno.h>
77 1.1.4.2 rmind #include <sys/kernel.h>
78 1.1.4.2 rmind #include <sys/mutex.h>
79 1.1.4.2 rmind #include <sys/systm.h>
80 1.1.4.2 rmind
81 1.1.4.2 rmind #include <machine/cpu.h>
82 1.1.4.2 rmind #include <machine/param.h>
83 1.1.4.2 rmind
84 1.1.4.2 rmind #include <dev/i2c/i2cvar.h>
85 1.1.4.2 rmind
86 1.1.4.2 rmind #include <dev/marvell/marvellvar.h>
87 1.1.4.2 rmind #include <dev/marvell/gttwsireg.h>
88 1.1.4.2 rmind
89 1.1.4.2 rmind struct gttwsi_softc {
90 1.1.4.2 rmind device_t sc_dev;
91 1.1.4.2 rmind bus_space_tag_t sc_bust;
92 1.1.4.2 rmind bus_space_handle_t sc_bush;
93 1.1.4.2 rmind uint8_t sc_started;
94 1.1.4.2 rmind struct i2c_controller sc_i2c;
95 1.1.4.2 rmind kmutex_t sc_buslock;
96 1.1.4.2 rmind kmutex_t sc_mtx;
97 1.1.4.2 rmind kcondvar_t sc_cv;
98 1.1.4.2 rmind };
99 1.1.4.2 rmind
100 1.1.4.2 rmind static int gttwsi_match(device_t, cfdata_t, void *);
101 1.1.4.2 rmind static void gttwsi_attach(device_t, device_t, void *);
102 1.1.4.2 rmind
103 1.1.4.2 rmind static int gttwsi_intr(void *);
104 1.1.4.2 rmind
105 1.1.4.2 rmind static int gttwsi_acquire_bus(void *, int);
106 1.1.4.2 rmind static void gttwsi_release_bus(void *, int);
107 1.1.4.2 rmind static int gttwsi_send_start(void *v, int flags);
108 1.1.4.2 rmind static int gttwsi_send_stop(void *v, int flags);
109 1.1.4.2 rmind static int gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags);
110 1.1.4.2 rmind static int gttwsi_read_byte(void *v, uint8_t *valp, int flags);
111 1.1.4.2 rmind static int gttwsi_write_byte(void *v, uint8_t val, int flags);
112 1.1.4.2 rmind
113 1.1.4.2 rmind static int gttwsi_wait(struct gttwsi_softc *, uint32_t, uint32_t, int);
114 1.1.4.2 rmind
115 1.1.4.2 rmind static __inline u_int32_t RREG(struct gttwsi_softc *, u_int32_t);
116 1.1.4.2 rmind static __inline void WREG(struct gttwsi_softc *, u_int32_t, u_int32_t);
117 1.1.4.2 rmind
118 1.1.4.2 rmind
119 1.1.4.2 rmind CFATTACH_DECL_NEW(gttwsi_gt, sizeof(struct gttwsi_softc),
120 1.1.4.2 rmind gttwsi_match, gttwsi_attach, NULL, NULL);
121 1.1.4.2 rmind CFATTACH_DECL_NEW(gttwsi_mbus, sizeof(struct gttwsi_softc),
122 1.1.4.2 rmind gttwsi_match, gttwsi_attach, NULL, NULL);
123 1.1.4.2 rmind
124 1.1.4.2 rmind
125 1.1.4.2 rmind static __inline u_int32_t
126 1.1.4.2 rmind RREG(struct gttwsi_softc *sc, u_int32_t reg)
127 1.1.4.2 rmind {
128 1.1.4.2 rmind u_int32_t val;
129 1.1.4.2 rmind
130 1.1.4.2 rmind val = bus_space_read_4(sc->sc_bust, sc->sc_bush, reg);
131 1.1.4.2 rmind #ifdef TWSI_DEBUG
132 1.1.4.2 rmind printf("I2C:R:%02x:%02x\n", reg, val);
133 1.1.4.2 rmind #else
134 1.1.4.2 rmind DELAY(TWSI_READ_DELAY);
135 1.1.4.2 rmind #endif
136 1.1.4.2 rmind return val;
137 1.1.4.2 rmind }
138 1.1.4.2 rmind
139 1.1.4.2 rmind static __inline void
140 1.1.4.2 rmind WREG(struct gttwsi_softc *sc, u_int32_t reg, u_int32_t val)
141 1.1.4.2 rmind {
142 1.1.4.2 rmind bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
143 1.1.4.2 rmind #ifdef TWSI_DEBUG
144 1.1.4.2 rmind printf("I2C:W:%02x:%02x\n", reg, val);
145 1.1.4.2 rmind #else
146 1.1.4.2 rmind DELAY(TWSI_WRITE_DELAY);
147 1.1.4.2 rmind #endif
148 1.1.4.2 rmind return;
149 1.1.4.2 rmind }
150 1.1.4.2 rmind
151 1.1.4.2 rmind
152 1.1.4.2 rmind /* ARGSUSED */
153 1.1.4.2 rmind static int
154 1.1.4.2 rmind gttwsi_match(device_t parent, cfdata_t match, void *aux)
155 1.1.4.2 rmind {
156 1.1.4.2 rmind struct marvell_attach_args *mva = aux;
157 1.1.4.2 rmind
158 1.1.4.2 rmind if (strcmp(mva->mva_name, match->cf_name) != 0)
159 1.1.4.2 rmind return 0;
160 1.1.4.2 rmind
161 1.1.4.2 rmind if (mva->mva_offset == GTCF_OFFSET_DEFAULT ||
162 1.1.4.2 rmind mva->mva_irq == GTCF_IRQ_DEFAULT)
163 1.1.4.2 rmind return 0;
164 1.1.4.2 rmind
165 1.1.4.2 rmind mva->mva_size = GTTWSI_SIZE;
166 1.1.4.2 rmind return 1;
167 1.1.4.2 rmind }
168 1.1.4.2 rmind
169 1.1.4.2 rmind /* ARGSUSED */
170 1.1.4.2 rmind static void
171 1.1.4.2 rmind gttwsi_attach(device_t parent, device_t self, void *args)
172 1.1.4.2 rmind {
173 1.1.4.2 rmind struct gttwsi_softc *sc = device_private(self);
174 1.1.4.2 rmind struct marvell_attach_args *mva = args;
175 1.1.4.2 rmind struct i2cbus_attach_args iba;
176 1.1.4.2 rmind
177 1.1.4.2 rmind aprint_naive("\n");
178 1.1.4.2 rmind aprint_normal(": Marvell TWSI controller\n");
179 1.1.4.2 rmind
180 1.1.4.2 rmind sc->sc_dev = self;
181 1.1.4.2 rmind sc->sc_bust = mva->mva_iot;
182 1.1.4.2 rmind if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
183 1.1.4.2 rmind mva->mva_size, &sc->sc_bush)) {
184 1.1.4.2 rmind aprint_error_dev(self, "Cannot map registers\n");
185 1.1.4.2 rmind return;
186 1.1.4.2 rmind }
187 1.1.4.2 rmind
188 1.1.4.2 rmind mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
189 1.1.4.2 rmind mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_BIO);
190 1.1.4.2 rmind cv_init(&sc->sc_cv, "gttwsi");
191 1.1.4.2 rmind
192 1.1.4.2 rmind sc->sc_started = 0;
193 1.1.4.2 rmind sc->sc_i2c.ic_cookie = sc;
194 1.1.4.2 rmind sc->sc_i2c.ic_acquire_bus = gttwsi_acquire_bus;
195 1.1.4.2 rmind sc->sc_i2c.ic_release_bus = gttwsi_release_bus;
196 1.1.4.2 rmind sc->sc_i2c.ic_exec = NULL;
197 1.1.4.2 rmind sc->sc_i2c.ic_send_start = gttwsi_send_start;
198 1.1.4.2 rmind sc->sc_i2c.ic_send_stop = gttwsi_send_stop;
199 1.1.4.2 rmind sc->sc_i2c.ic_initiate_xfer = gttwsi_initiate_xfer;
200 1.1.4.2 rmind sc->sc_i2c.ic_read_byte = gttwsi_read_byte;
201 1.1.4.2 rmind sc->sc_i2c.ic_write_byte = gttwsi_write_byte;
202 1.1.4.2 rmind
203 1.1.4.2 rmind marvell_intr_establish(mva->mva_irq, IPL_BIO, gttwsi_intr, sc);
204 1.1.4.2 rmind
205 1.1.4.2 rmind /*
206 1.1.4.2 rmind * Put the controller into Soft Reset.
207 1.1.4.2 rmind */
208 1.1.4.2 rmind /* reset */
209 1.1.4.2 rmind WREG(sc, TWSI_SOFTRESET, SOFTRESET_VAL);
210 1.1.4.2 rmind
211 1.1.4.2 rmind memset(&iba, 0, sizeof(iba));
212 1.1.4.2 rmind iba.iba_tag = &sc->sc_i2c;
213 1.1.4.2 rmind (void) config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
214 1.1.4.2 rmind }
215 1.1.4.2 rmind
216 1.1.4.2 rmind static int
217 1.1.4.2 rmind gttwsi_intr(void *arg)
218 1.1.4.2 rmind {
219 1.1.4.2 rmind struct gttwsi_softc *sc = arg;
220 1.1.4.2 rmind uint32_t val;
221 1.1.4.2 rmind
222 1.1.4.2 rmind val = RREG(sc, TWSI_CONTROL);
223 1.1.4.2 rmind if (val & CONTROL_IFLG) {
224 1.1.4.2 rmind WREG(sc, TWSI_CONTROL, val & ~CONTROL_INTEN);
225 1.1.4.2 rmind mutex_enter(&sc->sc_mtx);
226 1.1.4.2 rmind cv_signal(&sc->sc_cv);
227 1.1.4.2 rmind mutex_exit(&sc->sc_mtx);
228 1.1.4.2 rmind
229 1.1.4.2 rmind return 1; /* handled */
230 1.1.4.2 rmind }
231 1.1.4.2 rmind return 0;
232 1.1.4.2 rmind }
233 1.1.4.2 rmind
234 1.1.4.2 rmind /* ARGSUSED */
235 1.1.4.2 rmind static int
236 1.1.4.2 rmind gttwsi_acquire_bus(void *arg, int flags)
237 1.1.4.2 rmind {
238 1.1.4.2 rmind struct gttwsi_softc *sc = arg;
239 1.1.4.2 rmind
240 1.1.4.2 rmind mutex_enter(&sc->sc_buslock);
241 1.1.4.2 rmind return 0;
242 1.1.4.2 rmind }
243 1.1.4.2 rmind
244 1.1.4.2 rmind /* ARGSUSED */
245 1.1.4.2 rmind static void
246 1.1.4.2 rmind gttwsi_release_bus(void *arg, int flags)
247 1.1.4.2 rmind {
248 1.1.4.2 rmind struct gttwsi_softc *sc = arg;
249 1.1.4.2 rmind
250 1.1.4.2 rmind mutex_exit(&sc->sc_buslock);
251 1.1.4.2 rmind }
252 1.1.4.2 rmind
253 1.1.4.2 rmind static int
254 1.1.4.2 rmind gttwsi_send_start(void *v, int flags)
255 1.1.4.2 rmind {
256 1.1.4.2 rmind struct gttwsi_softc *sc = v;
257 1.1.4.2 rmind int expect;
258 1.1.4.2 rmind
259 1.1.4.2 rmind if (sc->sc_started)
260 1.1.4.2 rmind expect = STAT_RSCT;
261 1.1.4.2 rmind else
262 1.1.4.2 rmind expect = STAT_SCT;
263 1.1.4.2 rmind sc->sc_started = 1;
264 1.1.4.2 rmind return gttwsi_wait(sc, CONTROL_START, expect, flags);
265 1.1.4.2 rmind }
266 1.1.4.2 rmind
267 1.1.4.2 rmind static int
268 1.1.4.2 rmind gttwsi_send_stop(void *v, int flags)
269 1.1.4.2 rmind {
270 1.1.4.2 rmind struct gttwsi_softc *sc = v;
271 1.1.4.2 rmind int retry = TWSI_RETRY_COUNT;
272 1.1.4.2 rmind
273 1.1.4.2 rmind sc->sc_started = 0;
274 1.1.4.2 rmind
275 1.1.4.2 rmind /* Interrupt is not generated for STAT_NRS. */
276 1.1.4.2 rmind WREG(sc, TWSI_CONTROL, CONTROL_STOP | CONTROL_TWSIEN);
277 1.1.4.2 rmind while (retry > 0) {
278 1.1.4.2 rmind if (RREG(sc, TWSI_STATUS) == STAT_NRS)
279 1.1.4.2 rmind return 0;
280 1.1.4.2 rmind retry--;
281 1.1.4.2 rmind DELAY(TWSI_STAT_DELAY);
282 1.1.4.2 rmind }
283 1.1.4.2 rmind
284 1.1.4.2 rmind aprint_error_dev(sc->sc_dev, "send STOP failed\n");
285 1.1.4.2 rmind return -1;
286 1.1.4.2 rmind }
287 1.1.4.2 rmind
288 1.1.4.2 rmind static int
289 1.1.4.2 rmind gttwsi_initiate_xfer(void *v, i2c_addr_t addr, int flags)
290 1.1.4.2 rmind {
291 1.1.4.2 rmind struct gttwsi_softc *sc = v;
292 1.1.4.2 rmind uint32_t data, expect;
293 1.1.4.2 rmind int error, read;
294 1.1.4.2 rmind
295 1.1.4.2 rmind gttwsi_send_start(v, flags);
296 1.1.4.2 rmind
297 1.1.4.2 rmind read = (flags & I2C_F_READ) != 0;
298 1.1.4.2 rmind if (read)
299 1.1.4.2 rmind expect = STAT_ARBT_AR;
300 1.1.4.2 rmind else
301 1.1.4.2 rmind expect = STAT_AWBT_AR;
302 1.1.4.2 rmind
303 1.1.4.2 rmind /*
304 1.1.4.2 rmind * First byte contains whether this xfer is a read or write.
305 1.1.4.2 rmind */
306 1.1.4.2 rmind data = read;
307 1.1.4.2 rmind if (addr > 0x7f) {
308 1.1.4.2 rmind /*
309 1.1.4.2 rmind * If this is a 10bit request, the first address byte is
310 1.1.4.2 rmind * 0b11110<b9><b8><r/w>.
311 1.1.4.2 rmind */
312 1.1.4.2 rmind data |= 0xf0 | ((addr & 0x300) >> 7);
313 1.1.4.2 rmind WREG(sc, TWSI_DATA, data);
314 1.1.4.2 rmind error = gttwsi_wait(sc, 0, expect, flags);
315 1.1.4.2 rmind if (error)
316 1.1.4.2 rmind return error;
317 1.1.4.2 rmind /*
318 1.1.4.2 rmind * The first address byte has been sent, now to send
319 1.1.4.2 rmind * the second one.
320 1.1.4.2 rmind */
321 1.1.4.2 rmind if (read)
322 1.1.4.2 rmind expect = STAT_SARBT_AR;
323 1.1.4.2 rmind else
324 1.1.4.2 rmind expect = STAT_SAWBT_AR;
325 1.1.4.2 rmind data = (uint8_t)addr;
326 1.1.4.2 rmind } else
327 1.1.4.2 rmind data |= (addr << 1);
328 1.1.4.2 rmind
329 1.1.4.2 rmind WREG(sc, TWSI_DATA, data);
330 1.1.4.2 rmind return gttwsi_wait(sc, 0, expect, flags);
331 1.1.4.2 rmind }
332 1.1.4.2 rmind
333 1.1.4.2 rmind static int
334 1.1.4.2 rmind gttwsi_read_byte(void *v, uint8_t *valp, int flags)
335 1.1.4.2 rmind {
336 1.1.4.2 rmind struct gttwsi_softc *sc = v;
337 1.1.4.2 rmind int error;
338 1.1.4.2 rmind
339 1.1.4.2 rmind error = gttwsi_wait(sc, CONTROL_ACK, STAT_MRRD_AT, flags);
340 1.1.4.2 rmind if (!error)
341 1.1.4.2 rmind *valp = RREG(sc, TWSI_DATA);
342 1.1.4.2 rmind if (flags & I2C_F_LAST)
343 1.1.4.2 rmind WREG(sc, TWSI_CONTROL, 0);
344 1.1.4.2 rmind return error;
345 1.1.4.2 rmind }
346 1.1.4.2 rmind
347 1.1.4.2 rmind static int
348 1.1.4.2 rmind gttwsi_write_byte(void *v, uint8_t val, int flags)
349 1.1.4.2 rmind {
350 1.1.4.2 rmind struct gttwsi_softc *sc = v;
351 1.1.4.2 rmind
352 1.1.4.2 rmind WREG(sc, TWSI_DATA, val);
353 1.1.4.2 rmind return gttwsi_wait(sc, 0, STAT_MTDB_AR, flags);
354 1.1.4.2 rmind }
355 1.1.4.2 rmind
356 1.1.4.2 rmind static int
357 1.1.4.2 rmind gttwsi_wait(struct gttwsi_softc *sc, uint32_t control, uint32_t expect,
358 1.1.4.2 rmind int flags)
359 1.1.4.2 rmind {
360 1.1.4.2 rmind uint32_t status;
361 1.1.4.2 rmind int error = 0;
362 1.1.4.2 rmind
363 1.1.4.2 rmind DELAY(5);
364 1.1.4.2 rmind if (!(flags & I2C_F_POLL))
365 1.1.4.2 rmind control |= CONTROL_INTEN;
366 1.1.4.2 rmind WREG(sc, TWSI_CONTROL, control | CONTROL_TWSIEN);
367 1.1.4.2 rmind
368 1.1.4.2 rmind for (;;) {
369 1.1.4.2 rmind control = RREG(sc, TWSI_CONTROL);
370 1.1.4.2 rmind if (control & CONTROL_IFLG)
371 1.1.4.2 rmind break;
372 1.1.4.2 rmind if (!(flags & I2C_F_POLL)) {
373 1.1.4.2 rmind mutex_enter(&sc->sc_mtx);
374 1.1.4.2 rmind error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_mtx, hz);
375 1.1.4.2 rmind mutex_exit(&sc->sc_mtx);
376 1.1.4.2 rmind if (error)
377 1.1.4.2 rmind return error;
378 1.1.4.2 rmind }
379 1.1.4.2 rmind DELAY(TWSI_RETRY_DELAY);
380 1.1.4.2 rmind }
381 1.1.4.2 rmind
382 1.1.4.2 rmind status = RREG(sc, TWSI_STATUS);
383 1.1.4.2 rmind if (status != expect) {
384 1.1.4.2 rmind aprint_error_dev(sc->sc_dev,
385 1.1.4.2 rmind "unexpected status 0x%x: expect 0x%x\n", status, expect);
386 1.1.4.2 rmind return EIO;
387 1.1.4.2 rmind }
388 1.1.4.2 rmind
389 1.1.4.2 rmind if ((flags & I2C_F_STOP) && expect != STAT_MRRD_AT)
390 1.1.4.2 rmind error = gttwsi_send_stop(sc, flags);
391 1.1.4.2 rmind
392 1.1.4.2 rmind return error;
393 1.1.4.2 rmind }
394