if_gfe.c revision 1.1
1 /* $NetBSD: if_gfe.c,v 1.1 2003/03/05 22:08:23 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #define PKT_DUMP 0 45 46 #include "opt_inet.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/types.h> 51 #include <sys/inttypes.h> 52 #include <sys/queue.h> 53 54 #include <sys/callout.h> 55 #include <sys/device.h> 56 #include <sys/errno.h> 57 #include <sys/ioctl.h> 58 #include <sys/mbuf.h> 59 #include <sys/socket.h> 60 61 #include <machine/bus.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <dev/mii/miivar.h> 77 78 #include <dev/marvell/gtintrreg.h> 79 #include <dev/marvell/gtethreg.h> 80 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/if_gfevar.h> 83 84 #define GE_READ(sc, reg) \ 85 gt_read((sc)->sc_dev.dv_parent, ETH_ ## reg ((sc)->sc_macno)) 86 #define GE_WRITE(sc, reg, v) \ 87 gt_write((sc)->sc_dev.dv_parent, ETH_ ## reg ((sc)->sc_macno), (v)) 88 89 #define GE_DEBUG 90 #if 0 91 #define GE_NOHASH 92 #define GE_NORX 93 #endif 94 95 #ifdef GE_DEBUG 96 #define GE_DPRINTF(sc, a) do \ 97 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 98 printf a; \ 99 while (0) 100 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 101 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 102 #else 103 #define GE_DPRINTF(sc, a) do { } while (0) 104 #define GE_FUNC_ENTER(sc, func) do { } while (0) 105 #define GE_FUNC_EXIT(sc, str) do { } while (0) 106 #endif 107 enum gfe_whack_op { 108 GE_WHACK_START, GE_WHACK_RESTART, 109 GE_WHACK_CHANGE, GE_WHACK_STOP 110 }; 111 112 enum gfe_hash_op { 113 GE_HASH_ADD, GE_HASH_REMOVE, 114 }; 115 116 #define STATIC 117 118 STATIC int gfe_match (struct device *, struct cfdata *, void *); 119 STATIC void gfe_attach (struct device *, struct device *, void *); 120 121 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, size_t); 122 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 123 124 STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); 125 STATIC void gfe_ifstart (struct ifnet *); 126 STATIC void gfe_ifwatchdog (struct ifnet *); 127 128 STATIC int gfe_mii_mediachange (struct ifnet *); 129 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 130 STATIC int gfe_mii_read (struct device *, int, int); 131 STATIC void gfe_mii_write (struct device *, int, int, int); 132 STATIC void gfe_mii_statchg (struct device *); 133 134 STATIC void gfe_tick(void *arg); 135 136 STATIC void gfe_tx_restart(void *); 137 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 138 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 139 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 140 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 141 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 142 143 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 144 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 145 STATIC int gfe_rx_prime(struct gfe_softc *); 146 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 147 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 148 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 149 150 STATIC int gfe_intr(void *); 151 152 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 153 154 STATIC int gfe_hash_compute(struct gfe_softc *, const u_int8_t [ETHER_ADDR_LEN]); 155 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 156 enum gfe_rxprio, const u_int8_t [ETHER_ADDR_LEN]); 157 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 158 u_long); 159 STATIC int gfe_hash_fill(struct gfe_softc *); 160 STATIC int gfe_hash_alloc(struct gfe_softc *); 161 162 /* Linkup to the rest of the kernel */ 163 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 164 gfe_match, gfe_attach, NULL, NULL); 165 166 int 167 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 168 { 169 struct gt_softc *gt = (struct gt_softc *) parent; 170 struct gt_attach_args *ga = aux; 171 uint8_t enaddr[6]; 172 173 if (ga->ga_unit > 2) 174 return 0; 175 176 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 177 return 0; 178 179 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 180 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 181 return 0; 182 183 return 1; 184 } 185 186 /* 187 * Attach this instance, and then all the sub-devices 188 */ 189 void 190 gfe_attach(struct device *parent, struct device *self, void *aux) 191 { 192 struct gt_attach_args *ga = aux; 193 struct gt_softc *gt = (struct gt_softc *) parent; 194 struct gfe_softc *sc = (struct gfe_softc *) self; 195 struct ifnet *ifp; 196 uint32_t data; 197 uint8_t enaddr[6]; 198 int phyaddr; 199 uint32_t sdcr; 200 201 sc->sc_memt = ga->ga_memt; 202 sc->sc_dmat = ga->ga_dmat; 203 sc->sc_macno = ga->ga_unit; 204 205 callout_init(&sc->sc_co); 206 207 data = gt_read(parent, ETH_EPAR); 208 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 209 210 gtget_macaddr(gt, sc->sc_macno, enaddr); 211 212 sc->sc_pcr = GE_READ(sc, EPCR); 213 sc->sc_pcxr = GE_READ(sc, EPCXR); 214 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 215 216 printf(": address %s, phy %d", ether_sprintf(enaddr), phyaddr); 217 218 #if defined(DEBUG) 219 printf(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 220 #endif 221 222 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 223 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 224 sc->sc_pcxr &= ~(3 << 14); 225 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 226 227 if (sc->sc_pcr & ETH_EPCR_EN) { 228 int tries = 1000; 229 /* 230 * Abort transmitter and receiver and wait for them to quiese 231 */ 232 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 233 do { 234 delay(100); 235 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 236 } 237 238 sc->sc_pcr &= ~ETH_EPCR_EN; 239 240 #if defined(DEBUG) 241 printf(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 242 #endif 243 244 /* 245 * Now turn off the GT. If it didn't quiese, too ***ing bad. 246 */ 247 GE_WRITE(sc, EPCR, sc->sc_pcr); 248 GE_WRITE(sc, EIMR, sc->sc_intrmask); 249 sdcr = GE_READ(sc, ESDCR); 250 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 251 sdcr |= ETH_ESDCR_RIFB; 252 GE_WRITE(sc, ESDCR, sdcr); 253 sc->sc_max_frame_length = 1536; 254 255 printf("\n"); 256 sc->sc_mii.mii_ifp = &sc->sc_ec.ec_if; 257 sc->sc_mii.mii_readreg = gfe_mii_read; 258 sc->sc_mii.mii_writereg = gfe_mii_write; 259 sc->sc_mii.mii_statchg = gfe_mii_statchg; 260 261 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 262 gfe_mii_mediastatus); 263 264 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 265 MII_OFFSET_ANY, MIIF_NOISOLATE); 266 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 267 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 268 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 269 } else { 270 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 271 } 272 273 ifp = &sc->sc_ec.ec_if; 274 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 275 ifp->if_softc = sc; 276 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 277 #if 0 278 ifp->if_flags |= IFF_DEBUG; 279 #endif 280 ifp->if_ioctl = gfe_ifioctl; 281 ifp->if_start = gfe_ifstart; 282 ifp->if_watchdog = gfe_ifwatchdog; 283 284 if_attach(ifp); 285 ether_ifattach(ifp, enaddr); 286 #if NBPFILTER > 0 287 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 288 #endif 289 #if NRND > 0 290 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 291 #endif 292 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 293 gfe_intr, sc); 294 } 295 296 int 297 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 298 size_t size) 299 { 300 int error = 0; 301 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 302 gdm->gdm_size = size; 303 gdm->gdm_maxsegs = maxsegs; 304 305 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, NBPG, 306 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 307 BUS_DMA_NOWAIT); 308 if (error) 309 goto fail; 310 311 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 312 gdm->gdm_size, &gdm->gdm_kva, BUS_DMA_COHERENT|BUS_DMA_NOWAIT); 313 if (error) 314 goto fail; 315 316 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 317 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 318 if (error) 319 goto fail; 320 321 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 322 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 323 324 #if 1 325 { 326 size_t i; 327 for (i = 0; i < gdm->gdm_size; i += 32) 328 __asm __volatile("dcbf 0,%0" :: "r" (gdm->gdm_kva + i)); 329 } 330 #endif 331 fail: 332 if (error) { 333 gfe_dmamem_free(sc, gdm); 334 GE_DPRINTF(sc, (":err=%d", error)); 335 } 336 GE_FUNC_EXIT(sc, ""); 337 return error; 338 } 339 340 void 341 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 342 { 343 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 344 if (gdm->gdm_map) 345 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 346 if (gdm->gdm_kva) 347 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 348 if (gdm->gdm_nsegs > 0) 349 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 350 gdm->gdm_map = NULL; 351 gdm->gdm_kva = NULL; 352 gdm->gdm_nsegs = 0; 353 GE_FUNC_EXIT(sc, ""); 354 } 355 356 int 357 gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 358 { 359 struct gfe_softc * const sc = ifp->if_softc; 360 struct ifreq *ifr = (struct ifreq *) data; 361 struct ifaddr *ifa = (struct ifaddr *) data; 362 int s, error = 0; 363 364 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 365 s = splnet(); 366 367 switch (cmd) { 368 case SIOCSIFADDR: 369 ifp->if_flags |= IFF_UP; 370 switch (ifa->ifa_addr->sa_family) { 371 #ifdef INET 372 case AF_INET: 373 error = gfe_whack(sc, GE_WHACK_START); 374 if (error == 0) 375 arp_ifinit(ifp, ifa); 376 break; 377 #endif 378 default: 379 error = gfe_whack(sc, GE_WHACK_START); 380 break; 381 } 382 break; 383 384 case SIOCSIFFLAGS: 385 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 386 case IFF_UP|IFF_RUNNING:/* active->active, update */ 387 error = gfe_whack(sc, GE_WHACK_CHANGE); 388 break; 389 case IFF_RUNNING: /* not up, so we stop */ 390 error = gfe_whack(sc, GE_WHACK_STOP); 391 break; 392 case IFF_UP: /* not running, so we start */ 393 error = gfe_whack(sc, GE_WHACK_START); 394 break; 395 case 0: /* idle->idle: do nothing */ 396 break; 397 } 398 break; 399 400 case SIOCADDMULTI: 401 case SIOCDELMULTI: 402 error = (cmd == SIOCADDMULTI) 403 ? ether_addmulti(ifr, &sc->sc_ec) 404 : ether_delmulti(ifr, &sc->sc_ec); 405 if (error == ENETRESET) { 406 if (ifp->if_flags & IFF_RUNNING) 407 error = gfe_whack(sc, GE_WHACK_CHANGE); 408 else 409 error = 0; 410 } 411 break; 412 413 case SIOCSIFMTU: 414 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 415 error = EINVAL; 416 break; 417 } 418 ifp->if_mtu = ifr->ifr_mtu; 419 break; 420 421 case SIOCSIFMEDIA: 422 case SIOCGIFMEDIA: 423 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 424 break; 425 426 default: 427 error = EINVAL; 428 break; 429 } 430 splx(s); 431 GE_FUNC_EXIT(sc, ""); 432 return error; 433 } 434 435 void 436 gfe_ifstart(struct ifnet *ifp) 437 { 438 struct gfe_softc * const sc = ifp->if_softc; 439 struct mbuf *m; 440 441 GE_FUNC_ENTER(sc, "gfe_ifstart"); 442 443 if ((ifp->if_flags & IFF_RUNNING) == 0) { 444 GE_FUNC_EXIT(sc, "$"); 445 return; 446 } 447 448 if (sc->sc_txq[GE_TXPRIO_HI] == NULL) { 449 ifp->if_flags |= IFF_OACTIVE; 450 #if defined(DEBUG) || defined(DIAGNOSTIC) 451 printf("%s: ifstart: txq not yet created\n", ifp->if_xname); 452 #endif 453 GE_FUNC_EXIT(sc, ""); 454 return; 455 } 456 457 for (;;) { 458 IF_DEQUEUE(&ifp->if_snd, m); 459 if (m == NULL) { 460 ifp->if_flags &= ~IFF_OACTIVE; 461 GE_FUNC_EXIT(sc, ""); 462 return; 463 } 464 465 /* 466 * No space in the pending queue? try later. 467 */ 468 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq)) 469 break; 470 471 /* 472 * Try to enqueue a mbuf to the device. If that fails, we 473 * can always try to map the next mbuf. 474 */ 475 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq, m); 476 GE_DPRINTF(sc, (">")); 477 #ifndef GE_NOTX 478 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 479 #endif 480 } 481 482 /* 483 * Attempt to queue the mbuf for send failed. 484 */ 485 IF_PREPEND(&ifp->if_snd, m); 486 ifp->if_flags |= IFF_OACTIVE; 487 GE_FUNC_EXIT(sc, "%%"); 488 } 489 490 void 491 gfe_ifwatchdog(struct ifnet *ifp) 492 { 493 struct gfe_softc * const sc = ifp->if_softc; 494 struct gfe_txqueue *txq; 495 496 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 497 printf("%s: device timeout", 498 sc->sc_dev.dv_xname); 499 if ((txq = sc->sc_txq[GE_TXPRIO_HI]) != NULL) { 500 unsigned int curtxdnum = (gt_read(sc->sc_dev.dv_parent, txq->txq_ectdp) - txq->txq_desc_busaddr) / 16; 501 printf(" (fi=%d,lo=%d,cur=%d(%#x),icm=%#x) ", 502 txq->txq_fi, txq->txq_lo, curtxdnum, 503 txq->txq_descs[curtxdnum].ed_cmdsts, 504 GE_READ(sc, EICR)); 505 } 506 printf("\n"); 507 ifp->if_oerrors++; 508 (void) gfe_whack(sc, GE_WHACK_RESTART); 509 GE_FUNC_EXIT(sc, ""); 510 } 511 512 int 514 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 515 { 516 struct gfe_rxqueue *rxq; 517 volatile struct gt_eth_desc *rxd; 518 const bus_dma_segment_t *ds; 519 int error; 520 int idx; 521 bus_addr_t nxtaddr; 522 bus_size_t boff; 523 524 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 525 if (sc->sc_rxq[rxprio] != NULL) { 526 GE_FUNC_EXIT(sc, ""); 527 return 0; 528 } 529 530 rxq = (struct gfe_rxqueue *) malloc(sizeof(*rxq), M_DEVBUF, M_NOWAIT); 531 if (rxq == NULL) { 532 GE_FUNC_EXIT(sc, "!"); 533 return ENOMEM; 534 } 535 536 memset(rxq, 0, sizeof(*rxq)); 537 538 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, GE_RXDESC_MEMSIZE); 539 if (error) { 540 free(rxq, M_DEVBUF); 541 GE_FUNC_EXIT(sc, "!!"); 542 return error; 543 } 544 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 545 GE_RXBUF_MEMSIZE); 546 if (error) { 547 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 548 free(rxq, M_DEVBUF); 549 GE_FUNC_EXIT(sc, "!!!"); 550 return error; 551 } 552 553 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_TXMEM_SIZE); 554 555 sc->sc_rxq[rxprio] = rxq; 556 rxq->rxq_descs = 557 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 558 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 559 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 560 rxq->rxq_fi = 0; 561 rxq->rxq_active = GE_RXDESC_MAX; 562 for (idx = 0, rxd = rxq->rxq_descs, 563 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 564 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 565 idx < GE_RXDESC_MAX; 566 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 567 rxd->ed_cmdsts = htobe32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 568 rxd->ed_lencnt = htobe32(GE_RXBUF_SIZE << 16); 569 rxd->ed_bufptr = htobe32(ds->ds_addr + boff); 570 /* 571 * update the nxtptr to point to the next txd. 572 */ 573 if (idx == GE_RXDESC_MAX - 1) 574 nxtaddr = rxq->rxq_desc_busaddr; 575 rxd->ed_nxtptr = htobe32(nxtaddr); 576 boff += GE_RXBUF_SIZE; 577 if (boff == ds->ds_len) { 578 ds++; 579 boff = 0; 580 } 581 __asm __volatile("dcbf 0,%0" :: "r" (rxd)); 582 } 583 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 584 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 585 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 586 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 587 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 588 BUS_DMASYNC_PREWRITE); 589 590 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 591 switch (rxprio) { 592 case GE_RXPRIO_HI: 593 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 594 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 595 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 596 break; 597 case GE_RXPRIO_MEDHI: 598 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 599 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 600 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 601 break; 602 case GE_RXPRIO_MEDLO: 603 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 604 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 605 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 606 break; 607 case GE_RXPRIO_LO: 608 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 609 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 610 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 611 break; 612 } 613 GE_FUNC_EXIT(sc, ""); 614 return error; 615 } 616 617 #if PKT_DUMP 618 static void pkt_dump(struct gfe_softc *sc, unsigned char *p, int l); 619 static void 620 pkt_dump(struct gfe_softc *sc, unsigned char *p, int l) 621 { 622 char str[17]; 623 int j; 624 625 str[16] = '\0'; 626 while (l) { 627 printf("%08lx:", (unsigned long) p); 628 for (j=0;j<16 && l;j++, l--, p++) { 629 printf(" %02x", (unsigned) *p); 630 str[j] = (*p < ' ' || *p > '~') ? '.' : *p; 631 } 632 while (j < 16) { printf(" "); str[j++] = ' '; } 633 printf(" %s\n", str); 634 } 635 } 636 #endif 637 638 void 639 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 640 { 641 struct ifnet * const ifp = &sc->sc_ec.ec_if; 642 struct gfe_rxqueue * const rxq = sc->sc_rxq[rxprio]; 643 struct mbuf *m = rxq->rxq_curpkt; 644 645 GE_FUNC_ENTER(sc, "gfe_rx_get"); 646 GE_DPRINTF(sc, ("(%d)", rxprio)); 647 648 while (rxq->rxq_active > 0) { 649 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 650 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 651 const struct ether_header *eh; 652 unsigned int cmdsts; 653 size_t buflen; 654 655 __asm __volatile("dcbi 0,%0" :: "r" (rxd)); 656 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 657 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 658 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 659 cmdsts = be32toh(rxd->ed_cmdsts); 660 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 661 rxq->rxq_cmdsts = cmdsts; 662 /* 663 * Sometimes the GE "forgets" to reset the ownership bit. 664 * But if the length has been rewritten, the packet is ours 665 * so pretend the O bit is set. 666 */ 667 buflen = be32toh(rxd->ed_lencnt) & 0xffff; 668 if ((cmdsts & RX_CMD_O) && buflen == 0) { 669 break; 670 } 671 672 /* 673 * If this is not a single buffer packet with no errors 674 * or for some reason it's bigger than our frame size, 675 * ignore it and go to the next packet. 676 */ 677 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 678 (RX_CMD_F|RX_CMD_L) || 679 buflen > sc->sc_max_frame_length) { 680 GE_DPRINTF(sc, ("!")); 681 --rxq->rxq_active; 682 ifp->if_ipackets++; 683 ifp->if_ierrors++; 684 goto give_it_back; 685 } 686 687 if (m == NULL) { 688 MGETHDR(m, M_DONTWAIT, MT_DATA); 689 if (m == NULL) { 690 GE_DPRINTF(sc, ("?")); 691 break; 692 } 693 m->m_data += 2; 694 } 695 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 696 MCLGET(m, M_DONTWAIT); 697 if ((m->m_flags & M_EXT) == 0) { 698 GE_DPRINTF(sc, ("?")); 699 break; 700 } 701 m->m_data += 2; 702 } 703 m->m_len = 0; 704 m->m_pkthdr.len = 0; 705 m->m_pkthdr.rcvif = &sc->sc_ec.ec_if; 706 rxq->rxq_cmdsts = cmdsts; 707 --rxq->rxq_active; 708 709 ifp->if_ibytes += buflen; 710 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 711 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTWRITE); 712 713 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 714 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 715 #if PKT_DUMP 716 printf("[%d]\n", buflen); 717 pkt_dump(sc,m->m_data+m->m_len,buflen); 718 #endif 719 m->m_len = buflen; 720 m->m_pkthdr.len = buflen; 721 722 ifp->if_ipackets++; 723 #ifdef M_HASFCS 724 m->m_flags |= M_HASFCS; 725 #else 726 m->m_len -= 4; 727 m->m_pkthdr.len -= 4; 728 #endif 729 #if NBPFILTER > 0 730 if (ifp->if_bpf != NULL) 731 bpf_mtap(ifp->if_bpf, m); 732 #endif 733 734 eh = (const struct ether_header *) m->m_data; 735 if ((ifp->if_flags & IFF_PROMISC) || 736 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 737 (rxq->rxq_cmdsts & RX_STS_HE) || 738 (eh->ether_dhost[0] & 1) != 0 || 739 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 740 ETHER_ADDR_LEN) == 0) { 741 (*ifp->if_input)(ifp, m); 742 m = NULL; 743 GE_DPRINTF(sc, (">")); 744 } else { 745 m->m_len = 0; 746 m->m_pkthdr.len = 0; 747 GE_DPRINTF(sc, ("+")); 748 } 749 rxq->rxq_cmdsts = 0; 750 751 give_it_back: 752 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 753 rxd->ed_cmdsts = htobe32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 754 __asm __volatile("dcbf 0,%0" :: "r" (rxd)); 755 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 756 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 757 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 758 rxq->rxq_fi = (rxd->ed_nxtptr - rxq->rxq_desc_busaddr) / 759 sizeof(*rxd); 760 #if 0 761 if (++rxq->rxq_fi == GE_RXDESC_MAX) 762 rxq->rxq_fi = 0; 763 #endif 764 rxq->rxq_active++; 765 } 766 rxq->rxq_curpkt = m; 767 GE_FUNC_EXIT(sc, ""); 768 } 769 770 uint32_t 771 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 772 { 773 struct gfe_rxqueue *rxq; 774 uint32_t rxbits; 775 #define RXPRIO_DECODER 0xffffaa50 776 GE_FUNC_ENTER(sc, "gfe_rx_process"); 777 778 rxbits = ETH_IR_RxBuffer_GET(cause); 779 while (rxbits) { 780 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 781 GE_DPRINTF(sc, ("%1x", rxbits)); 782 rxbits &= ~(1 << rxprio); 783 gfe_rx_get(sc, rxprio); 784 } 785 786 rxbits = ETH_IR_RxError_GET(cause); 787 while (rxbits) { 788 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 789 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 790 int idx; 791 rxbits &= ~(1 << rxprio); 792 rxq = sc->sc_rxq[rxprio]; 793 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 794 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 795 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 796 sc->sc_tickflags |= GE_TICK_RX_RESTART; 797 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 798 } 799 sc->sc_ec.ec_if.if_ierrors++; 800 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 801 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 802 memset(masks, 0, sizeof(masks)); 803 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 804 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 805 806 __asm __volatile("dcbi 0,%0" :: "r" (rxd)); 807 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 808 idx * sizeof(*rxd), sizeof(*rxd), 809 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 810 if (RX_CMD_O & be32toh(rxd->ed_cmdsts)) 811 masks[idx/32] |= 1 << (idx & 31); 812 } 813 #if defined(DEBUG) 814 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 815 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 816 rxq->rxq_cmdsts, masks[0], masks[1]); 817 #endif 818 } 819 if ((intrmask & ETH_IR_RxBits) == 0) 820 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 821 822 GE_FUNC_EXIT(sc, ""); 823 return intrmask; 824 } 825 826 int 827 gfe_rx_prime(struct gfe_softc *sc) 828 { 829 struct gfe_rxqueue *rxq; 830 int error; 831 832 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 833 834 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 835 if (error) 836 goto bail; 837 rxq = sc->sc_rxq[GE_RXPRIO_HI]; 838 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 839 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 840 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 841 } 842 sc->sc_intrmask |= rxq->rxq_intrbits; 843 844 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 845 if (error) 846 goto bail; 847 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 848 rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 849 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 850 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 851 sc->sc_intrmask |= rxq->rxq_intrbits; 852 } 853 854 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 855 if (error) 856 goto bail; 857 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 858 rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 859 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 860 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 861 sc->sc_intrmask |= rxq->rxq_intrbits; 862 } 863 864 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 865 if (error) 866 goto bail; 867 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 868 rxq = sc->sc_rxq[GE_RXPRIO_LO]; 869 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 870 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 871 sc->sc_intrmask |= rxq->rxq_intrbits; 872 } 873 874 bail: 875 GE_FUNC_EXIT(sc, ""); 876 return error; 877 } 878 879 void 880 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 881 { 882 struct gfe_rxqueue *rxq = sc->sc_rxq[rxprio]; 883 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 884 if (rxq == NULL) { 885 GE_FUNC_EXIT(sc, ""); 886 return; 887 } 888 889 if (rxq->rxq_curpkt) 890 m_freem(rxq->rxq_curpkt); 891 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 892 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 893 free(rxq, M_DEVBUF); 894 sc->sc_rxq[rxprio] = NULL; 895 GE_FUNC_EXIT(sc, ""); 896 } 897 898 void 899 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 900 { 901 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 902 sc->sc_flags &= ~GE_RXACTIVE; 903 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 904 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 905 GE_WRITE(sc, EIMR, sc->sc_intrmask); 906 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 907 do { 908 delay(10); 909 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 910 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 911 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 912 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 913 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 914 GE_FUNC_EXIT(sc, ""); 915 } 916 917 void 919 gfe_tick(void *arg) 920 { 921 struct gfe_softc * const sc = arg; 922 uint32_t intrmask; 923 unsigned int tickflags; 924 int s; 925 926 GE_FUNC_ENTER(sc, "gfe_tick"); 927 928 s = splnet(); 929 930 tickflags = sc->sc_tickflags; 931 sc->sc_tickflags = 0; 932 intrmask = sc->sc_intrmask; 933 if (tickflags & GE_TICK_TX_IFSTART) 934 gfe_ifstart(&sc->sc_ec.ec_if); 935 if (tickflags & GE_TICK_RX_RESTART) { 936 intrmask |= sc->sc_idlemask; 937 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 938 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_HI]; 939 rxq->rxq_fi = 0; 940 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 941 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 942 } 943 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 944 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 945 rxq->rxq_fi = 0; 946 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 947 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 948 } 949 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 950 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 951 rxq->rxq_fi = 0; 952 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 953 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 954 } 955 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 956 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_LO]; 957 rxq->rxq_fi = 0; 958 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 959 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 960 } 961 sc->sc_idlemask = 0; 962 } 963 if (intrmask != sc->sc_intrmask) { 964 sc->sc_intrmask = intrmask; 965 GE_WRITE(sc, EIMR, sc->sc_intrmask); 966 } 967 gfe_intr(sc); 968 splx(s); 969 970 GE_FUNC_EXIT(sc, ""); 971 } 972 973 int 974 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 975 { 976 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 977 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 978 uint32_t intrmask = sc->sc_intrmask; 979 struct mbuf *m; 980 981 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 982 983 /* 984 * Anything in the pending queue to enqueue? if not, punt. 985 * otherwise grab its dmamap. 986 */ 987 if ((m = txq->txq_pendq.ifq_head) == NULL) { 988 GE_FUNC_EXIT(sc, "-"); 989 return 0; 990 } 991 992 /* 993 * Have we [over]consumed our limit of descriptors? 994 * Do we have enough free descriptors? 995 */ 996 if (GE_TXDESC_MAX == txq->txq_nactive + 1) { 997 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 998 uint32_t cmdsts; 999 size_t pktlen; 1000 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1001 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1002 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1003 cmdsts = be32toh(txd2->ed_cmdsts); 1004 if (cmdsts & TX_CMD_O) { 1005 GE_FUNC_EXIT(sc, "@"); 1006 return 0; 1007 } 1008 if (++txq->txq_fi == GE_TXDESC_MAX) 1009 txq->txq_fi = 0; 1010 txq->txq_inptr = be32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1011 pktlen = (be32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1012 txq->txq_inptr += (pktlen + 7) & ~7; 1013 txq->txq_nactive--; 1014 1015 /* statistics */ 1016 sc->sc_ec.ec_if.if_opackets++; 1017 sc->sc_ec.ec_if.if_obytes += pktlen; 1018 if (cmdsts & TX_STS_ES) 1019 sc->sc_ec.ec_if.if_oerrors++; 1020 GE_DPRINTF(sc, ("%%")); 1021 } 1022 1023 /* 1024 * If this packet would wrap around the end of the buffer, reset back 1025 * to the beginning. 1026 */ 1027 if (txq->txq_outptr + m->m_pkthdr.len > GE_TXBUF_SIZE) { 1028 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1029 txq->txq_outptr = 0; 1030 } 1031 1032 /* 1033 * Make sure the output packet doesn't run over the beginning of 1034 * what we've already given the GT. 1035 */ 1036 if (txq->txq_outptr <= txq->txq_inptr && 1037 txq->txq_outptr + m->m_pkthdr.len > txq->txq_inptr) { 1038 intrmask |= txq->txq_intrbits & 1039 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1040 if (sc->sc_intrmask != intrmask) { 1041 sc->sc_intrmask = intrmask; 1042 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1043 } 1044 GE_FUNC_EXIT(sc, "#"); 1045 return 0; 1046 } 1047 1048 /* 1049 * The end-of-list descriptor we put on last time is the starting point 1050 * for this packet. The GT is supposed to terminate list processing on 1051 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1052 * must terminate the list. 1053 */ 1054 intrmask = sc->sc_intrmask; 1055 1056 m_copydata(m, 0, m->m_pkthdr.len, 1057 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1058 #if PKT_DUMP 1059 GE_DPRINTF(sc,("\n")); 1060 pkt_dump(sc, txq->txq_buf_mem.gdm_kva + txq->txq_outptr, m->m_pkthdr.len); 1061 #endif 1062 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1063 txq->txq_outptr, m->m_pkthdr.len, BUS_DMASYNC_PREREAD); 1064 txd->ed_bufptr = htobe32(txq->txq_buf_busaddr + txq->txq_outptr); 1065 txd->ed_lencnt = htobe32(m->m_pkthdr.len << 16); 1066 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1067 txq->txq_lo * sizeof(*txd), sizeof(*txd), 1068 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1069 GE_DPRINTF(sc, ("(p/l=%#lx/%d)", 1070 (unsigned long) txq->txq_buf_busaddr + txq->txq_outptr, 1071 m->m_pkthdr.len)); 1072 /* 1073 * Request a buffer interrupt every 2/3 of the way thru the transmit 1074 * buffer. 1075 */ 1076 txq->txq_ei_gapcount += m->m_pkthdr.len + 7; 1077 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1078 txd->ed_cmdsts = htobe32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1079 txq->txq_ei_gapcount = 0; 1080 } else { 1081 txd->ed_cmdsts = htobe32(TX_CMD_FIRST|TX_CMD_LAST); 1082 } 1083 1084 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1085 txq->txq_lo * sizeof(*txd), sizeof(*txd), 1086 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1087 1088 txq->txq_outptr += (m->m_pkthdr.len + 7) & ~7; 1089 /* 1090 * Tell the SDMA engine to "Fetch!" 1091 */ 1092 GE_WRITE(sc, ESDCMR, 1093 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1094 1095 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1096 1097 /* 1098 * Update the last out appropriately. 1099 */ 1100 if (++txq->txq_lo == GE_TXDESC_MAX) 1101 txq->txq_lo = 0; 1102 1103 /* 1104 * Move mbuf from the pending queue to the snd queue. 1105 */ 1106 IF_DEQUEUE(&txq->txq_pendq, m); 1107 #if NBPFILTER > 0 1108 if (sc->sc_ec.ec_if.if_bpf != NULL) 1109 bpf_mtap(sc->sc_ec.ec_if.if_bpf, m); 1110 #endif 1111 m_freem(m); 1112 sc->sc_ec.ec_if.if_flags &= ~IFF_OACTIVE; 1113 1114 /* 1115 * Since we have put an item into the packet queue, we now want 1116 * an interrupt when the transmit queue finishes processing the 1117 * list. But only update the mask if needs changing. 1118 */ 1119 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1120 if (sc->sc_intrmask != intrmask) { 1121 sc->sc_intrmask = intrmask; 1122 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1123 } 1124 if (sc->sc_ec.ec_if.if_timer == 0) 1125 sc->sc_ec.ec_if.if_timer = 5; 1126 GE_FUNC_EXIT(sc, "*"); 1127 return 1; 1128 } 1129 1130 uint32_t 1131 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1132 { 1133 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1134 1135 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1136 1137 if (txq == NULL) { 1138 GE_FUNC_EXIT(sc, ""); 1139 return intrmask; 1140 } 1141 1142 while (txq->txq_nactive > 0) { 1143 volatile struct gt_eth_desc *ed = &txq->txq_descs[txq->txq_fi]; 1144 uint32_t cmdsts; 1145 size_t pktlen; 1146 1147 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1148 txq->txq_fi * sizeof(*ed), sizeof(*ed), 1149 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1150 if ((cmdsts = be32toh(ed->ed_cmdsts)) & TX_CMD_O) { 1151 /* 1152 * If the GT owns this descriptor and according 1153 * to the status register, the transmit engine 1154 * is not running, restart it. 1155 */ 1156 #if 0 1157 if ((GE_READ(sc, EPSR) & txq->txq_epsrbits & 1158 (ETH_EPSR_TxHigh|ETH_EPSR_TxLow)) == 0) { 1159 /* 1160 * If the current transmit descriptor isn't 1161 * pointing at this descriptor, then we've 1162 * lost synch, reset it to this one before 1163 * restarting. 1164 */ 1165 unsigned int curtxdnum = ( 1166 gt_read(sc->sc_dev.dv_parent, 1167 txq->txq_ectdp) - 1168 txq->txq_desc_busaddr) / 16; 1169 if (curtxdnum != txq->txq_fi) { 1170 gt_write(sc->sc_dev.dv_parent, 1171 txq->txq_ectdp, 1172 txq->txq_desc_busaddr + 1173 sizeof(*ed) * txq->txq_fi); 1174 GE_DPRINTF(sc, 1175 ("(oldcur=%d,newcur=fi(%d))", 1176 curtxdnum, txq->txq_fi)); 1177 printf("%s: transmitter synchronization" 1178 " lost at %d; repositioning" 1179 " to %d\n", 1180 sc->sc_dev.dv_xname, 1181 curtxdnum, txq->txq_fi); 1182 } 1183 /* 1184 * [Re-] Kick the transmit engine. 1185 */ 1186 GE_WRITE(sc, ESDCMR, 1187 txq->txq_esdcmrbits & 1188 (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1189 GE_DPRINTF(sc, ("*")); 1190 } 1191 #endif 1192 GE_FUNC_EXIT(sc, ""); 1193 return intrmask; 1194 } 1195 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1196 if (++txq->txq_fi == GE_TXDESC_MAX) 1197 txq->txq_fi = 0; 1198 txq->txq_inptr = be32toh(ed->ed_bufptr) - txq->txq_buf_busaddr; 1199 pktlen = (be32toh(ed->ed_lencnt) >> 16) & 0xffff; 1200 txq->txq_inptr += (pktlen + 7) & ~7; 1201 1202 /* statistics */ 1203 sc->sc_ec.ec_if.if_opackets++; 1204 sc->sc_ec.ec_if.if_obytes += pktlen; 1205 if (cmdsts & TX_STS_ES) 1206 sc->sc_ec.ec_if.if_oerrors++; 1207 1208 ed->ed_bufptr = 0; 1209 1210 sc->sc_ec.ec_if.if_timer = 5; 1211 --txq->txq_nactive; 1212 } 1213 if (txq->txq_nactive != 0) 1214 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1215 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1216 sc->sc_ec.ec_if.if_timer = 0; 1217 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1218 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1219 GE_FUNC_EXIT(sc, ""); 1220 return intrmask; 1221 } 1222 1223 int 1224 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1225 { 1226 struct gfe_txqueue *txq; 1227 volatile struct gt_eth_desc *txd; 1228 unsigned int i; 1229 bus_addr_t addr; 1230 1231 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1232 1233 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1234 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1235 1236 if ((txq = sc->sc_txq[txprio]) == NULL) { 1237 int error; 1238 txq = (struct gfe_txqueue *) malloc(sizeof(*txq), 1239 M_DEVBUF, M_NOWAIT); 1240 if (txq == NULL) { 1241 GE_FUNC_EXIT(sc, ""); 1242 return ENOMEM; 1243 } 1244 memset(txq, 0, sizeof(*txq)); 1245 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1246 GE_TXMEM_SIZE); 1247 if (error) { 1248 free(txq, M_DEVBUF); 1249 GE_FUNC_EXIT(sc, ""); 1250 return error; 1251 } 1252 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, 1253 GE_TXBUF_SIZE); 1254 if (error) { 1255 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1256 free(txq, M_DEVBUF); 1257 GE_FUNC_EXIT(sc, ""); 1258 return error; 1259 } 1260 sc->sc_txq[txprio] = txq; 1261 } 1262 1263 txq->txq_descs = 1264 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1265 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1266 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1267 GE_DPRINTF(sc, ("(kva %#08lx, desc_bus %#08lx)", (unsigned long) txq->txq_descs, 1268 (unsigned long) txq->txq_desc_busaddr)); 1269 1270 txq->txq_pendq.ifq_maxlen = 10; 1271 txq->txq_ei_gapcount = 0; 1272 txq->txq_nactive = 0; 1273 txq->txq_fi = 0; 1274 txq->txq_lo = 0; 1275 txq->txq_inptr = GE_TXBUF_SIZE; 1276 txq->txq_outptr = 0; 1277 for (i = 0, txd = txq->txq_descs, 1278 addr = txq->txq_desc_busaddr + sizeof(*txd); 1279 i < GE_TXDESC_MAX - 1; 1280 i++, txd++, addr += sizeof(*txd)) { 1281 /* 1282 * update the nxtptr to point to the next txd. 1283 */ 1284 txd->ed_cmdsts = 0; 1285 txd->ed_nxtptr = htobe32(addr); 1286 } 1287 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1288 htobe32(txq->txq_desc_busaddr); 1289 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1290 GE_TXMEM_SIZE, BUS_DMASYNC_PREREAD); 1291 1292 switch (txprio) { 1293 case GE_TXPRIO_HI: 1294 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1295 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1296 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1297 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1298 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1299 break; 1300 1301 case GE_TXPRIO_LO: 1302 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1303 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1304 txq->txq_epsrbits = ETH_EPSR_TxLow; 1305 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1306 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1307 break; 1308 1309 case GE_TXPRIO_NONE: 1310 break; 1311 } 1312 #if 0 1313 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1314 gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); 1315 GE_DPRINTF(sc, (")")); 1316 #endif 1317 1318 /* 1319 * If we are restarting, there may be packets in the pending queue 1320 * waiting to be enqueued. Try enqueuing packets from both priority 1321 * queues until the pending queue is empty or there no room for them 1322 * on the device. 1323 */ 1324 while (gfe_tx_enqueue(sc, txprio)) 1325 continue; 1326 1327 GE_FUNC_EXIT(sc, ""); 1328 return 0; 1329 } 1330 1331 void 1332 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1333 { 1334 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1335 1336 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1337 if (txq == NULL) { 1338 GE_FUNC_EXIT(sc, ""); 1339 return; 1340 } 1341 1342 if (!flush) { 1343 GE_FUNC_EXIT(sc, ""); 1344 return; 1345 } 1346 1347 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1348 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1349 free(txq, M_DEVBUF); 1350 sc->sc_txq[txprio] = NULL; 1351 GE_FUNC_EXIT(sc, "-F"); 1352 } 1353 1354 void 1355 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1356 { 1357 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1358 1359 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1360 1361 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1362 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1363 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1364 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1365 1366 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1367 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1368 1369 sc->sc_ec.ec_if.if_timer = 0; 1370 GE_FUNC_EXIT(sc, ""); 1371 } 1372 1373 int 1375 gfe_intr(void *arg) 1376 { 1377 struct gfe_softc * const sc = arg; 1378 uint32_t cause; 1379 uint32_t intrmask = sc->sc_intrmask; 1380 int claim = 0; 1381 int cnt; 1382 1383 GE_FUNC_ENTER(sc, "gfe_intr"); 1384 1385 for (cnt = 0; cnt < 4; cnt++) { 1386 if (sc->sc_intrmask != intrmask) { 1387 sc->sc_intrmask = intrmask; 1388 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1389 } 1390 cause = GE_READ(sc, EICR); 1391 cause &= sc->sc_intrmask; 1392 GE_DPRINTF(sc, (".%#x", cause)); 1393 if (cause == 0) 1394 break; 1395 1396 claim = 1; 1397 1398 GE_WRITE(sc, EICR, ~cause); 1399 #ifndef GE_NORX 1400 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1401 intrmask = gfe_rx_process(sc, cause, intrmask); 1402 #endif 1403 1404 #ifndef GE_NOTX 1405 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1406 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1407 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1408 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1409 #endif 1410 if (cause & ETH_IR_MIIPhySTC) { 1411 sc->sc_flags |= GE_PHYSTSCHG; 1412 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1413 } 1414 } 1415 1416 GE_FUNC_EXIT(sc, ""); 1417 return claim; 1418 } 1419 1420 int 1422 gfe_mii_mediachange (struct ifnet *ifp) 1423 { 1424 struct gfe_softc *sc = ifp->if_softc; 1425 1426 if (ifp->if_flags & IFF_UP) 1427 mii_mediachg(&sc->sc_mii); 1428 1429 return (0); 1430 } 1431 void 1432 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1433 { 1434 struct gfe_softc *sc = ifp->if_softc; 1435 1436 if (sc->sc_flags & GE_PHYSTSCHG) { 1437 sc->sc_flags &= ~GE_PHYSTSCHG; 1438 mii_pollstat(&sc->sc_mii); 1439 } 1440 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1441 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1442 } 1443 1444 int 1445 gfe_mii_read (struct device *self, int phy, int reg) 1446 { 1447 return gt_mii_read(self, self->dv_parent, phy, reg); 1448 } 1449 1450 void 1451 gfe_mii_write (struct device *self, int phy, int reg, int value) 1452 { 1453 gt_mii_write(self, self->dv_parent, phy, reg, value); 1454 } 1455 1456 void 1457 gfe_mii_statchg (struct device *self) 1458 { 1459 /* struct gfe_softc *sc = (struct gfe_softc *) self; */ 1460 /* do nothing? */ 1461 } 1462 1463 int 1465 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1466 { 1467 int error = 0; 1468 GE_FUNC_ENTER(sc, "gfe_whack"); 1469 1470 switch (op) { 1471 case GE_WHACK_RESTART: 1472 #ifndef GE_NOTX 1473 gfe_tx_stop(sc, op); 1474 #endif 1475 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1476 /* FALLTHROUGH */ 1477 case GE_WHACK_START: 1478 #ifndef GE_NOHASH 1479 if (error == 0 && sc->sc_hashtable == NULL) { 1480 error = gfe_hash_alloc(sc); 1481 if (error) 1482 break; 1483 } 1484 if (op != GE_WHACK_RESTART) 1485 gfe_hash_fill(sc); 1486 #endif 1487 #ifndef GE_NORX 1488 if (op != GE_WHACK_RESTART) { 1489 error = gfe_rx_prime(sc); 1490 if (error) 1491 break; 1492 } 1493 #endif 1494 #ifndef GE_NOTX 1495 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1496 if (error) 1497 break; 1498 #endif 1499 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1500 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1501 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1502 GE_WRITE(sc, EICR, 0); 1503 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1504 #ifndef GE_NOHASH 1505 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1506 #endif 1507 #ifndef GE_NORX 1508 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1509 sc->sc_flags |= GE_RXACTIVE; 1510 #endif 1511 /* FALLTHROUGH */ 1512 case GE_WHACK_CHANGE: 1513 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1514 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1515 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1516 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1517 gfe_ifstart(&sc->sc_ec.ec_if); 1518 return error; 1519 case GE_WHACK_STOP: 1520 break; 1521 } 1522 1523 #ifdef GE_DEBUG 1524 if (error) 1525 GE_DPRINTF(sc, (" failed: %d\n", error)); 1526 #endif 1527 GE_WRITE(sc, EPCR, sc->sc_pcr); 1528 GE_WRITE(sc, EIMR, 0); 1529 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1530 #ifndef GE_NOTX 1531 gfe_tx_stop(sc, GE_WHACK_STOP); 1532 #endif 1533 #ifndef GE_NORX 1534 gfe_rx_stop(sc, GE_WHACK_STOP); 1535 #endif 1536 #ifndef GE_NOHASH 1537 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1538 sc->sc_hashtable = NULL; 1539 #endif 1540 1541 GE_FUNC_EXIT(sc, ""); 1542 return error; 1543 } 1544 1545 int 1547 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1548 { 1549 uint32_t w0, add0, add1; 1550 uint32_t result; 1551 1552 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1553 add0 = ((uint32_t) eaddr[5] << 0) | 1554 ((uint32_t) eaddr[4] << 8) | 1555 ((uint32_t) eaddr[3] << 16); 1556 1557 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1558 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1559 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1560 1561 add1 = ((uint32_t) eaddr[2] << 0) | 1562 ((uint32_t) eaddr[1] << 8) | 1563 ((uint32_t) eaddr[0] << 16); 1564 1565 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1566 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1567 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1568 1569 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1570 /* 1571 * hashResult is the 15 bits Hash entry address. 1572 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1573 * MAC address, by nibble swapping in every byte (i.e MAC address 1574 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1575 */ 1576 1577 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1578 /* 1579 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1580 * 1581 * hashFunc0 calculates the hashResult in the following manner: 1582 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1583 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1584 */ 1585 result = (add0 & 3) | ((add0 >> 6) & ~3); 1586 result ^= (add0 >> 15) ^ (add1 >> 0); 1587 result &= 0x1ff; 1588 /* 1589 * hashResult[14:9] = ethernetADD[7:2] 1590 */ 1591 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1592 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1593 } else { 1594 #define TRIBITFLIP 073516240 /* yes its in octal */ 1595 /* 1596 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1597 * 1598 * hashFunc1 calculates the hashResult in the following manner: 1599 * hashResult[08:00] = ethernetADD[06:14] 1600 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1601 */ 1602 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1603 /* 1604 * Now bitswap those 9 bits 1605 */ 1606 result = 0; 1607 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1608 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1609 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1610 1611 /* 1612 * hashResult[14:09] = ethernetADD[00:05] 1613 */ 1614 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1615 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1616 GE_DPRINTF(sc, ("1(%#x)", result)); 1617 } 1618 GE_FUNC_EXIT(sc, ""); 1619 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1620 } 1621 1622 int 1623 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1624 enum gfe_rxprio prio, const u_int8_t eaddr[ETHER_ADDR_LEN]) 1625 { 1626 uint64_t he; 1627 uint64_t *maybe_he_p = NULL; 1628 int limit; 1629 int hash; 1630 int maybe_hash = 0; 1631 1632 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1633 1634 hash = gfe_hash_compute(sc, eaddr); 1635 1636 if (sc->sc_hashtable == NULL) { 1637 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1638 __LINE__); 1639 } 1640 1641 /* 1642 * Assume we are going to insert so create the hash entry we 1643 * are going to insert. We also use it to match entries we 1644 * will be removing. 1645 */ 1646 he = ((uint64_t) eaddr[5] << 43) | 1647 ((uint64_t) eaddr[4] << 35) | 1648 ((uint64_t) eaddr[3] << 27) | 1649 ((uint64_t) eaddr[2] << 19) | 1650 ((uint64_t) eaddr[1] << 11) | 1651 ((uint64_t) eaddr[0] << 3) | 1652 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1653 1654 /* 1655 * The GT will search upto 12 entries for a hit, so we must mimic that. 1656 */ 1657 hash &= sc->sc_hashmask / sizeof(he); 1658 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1659 /* 1660 * Does the GT wrap at the end, stop at the, or overrun the 1661 * end? Assume it wraps for now. Stash a copy of the 1662 * current hash entry. 1663 */ 1664 uint64_t *he_p = &sc->sc_hashtable[hash]; 1665 uint64_t thishe = *he_p; 1666 1667 /* 1668 * If the hash entry isn't valid, that break the chain. And 1669 * this entry a good candidate for reuse. 1670 */ 1671 if ((thishe & HSH_V) == 0) { 1672 maybe_he_p = he_p; 1673 break; 1674 } 1675 1676 /* 1677 * If the hash entry has the same address we are looking for 1678 * then ... if we are removing and the skip bit is set, its 1679 * already been removed. if are adding and the skip bit is 1680 * clear, then its already added. In either return EBUSY 1681 * indicating the op has already been done. Otherwise flip 1682 * the skip bit and return 0. 1683 */ 1684 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1685 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1686 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1687 return EBUSY; 1688 *he_p = thishe ^ HSH_S; 1689 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1690 hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREREAD); 1691 GE_FUNC_EXIT(sc, "^"); 1692 return 0; 1693 } 1694 1695 /* 1696 * If we haven't found a slot for the entry and this entry 1697 * is currently being skipped, return this entry. 1698 */ 1699 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1700 maybe_he_p = he_p; 1701 maybe_hash = hash; 1702 } 1703 1704 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1705 } 1706 1707 /* 1708 * If we got here, then there was no entry to remove. 1709 */ 1710 if (op == GE_HASH_REMOVE) { 1711 GE_FUNC_EXIT(sc, "?"); 1712 return ENOENT; 1713 } 1714 1715 /* 1716 * If we couldn't find a slot, return an error. 1717 */ 1718 if (maybe_he_p == NULL) { 1719 GE_FUNC_EXIT(sc, "!"); 1720 return ENOSPC; 1721 } 1722 1723 /* Update the entry. 1724 */ 1725 *maybe_he_p = he; 1726 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1727 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREREAD); 1728 GE_FUNC_EXIT(sc, "+"); 1729 return 0; 1730 } 1731 1732 int 1733 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1734 { 1735 struct gfe_softc * const sc = ec->ec_if.if_softc; 1736 int error; 1737 enum gfe_hash_op op; 1738 enum gfe_rxprio prio; 1739 1740 GE_FUNC_ENTER(sc, "hash_multichg"); 1741 /* 1742 * Is this a wildcard entry? If so and its being removed, recompute. 1743 */ 1744 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1745 if (cmd == SIOCDELMULTI) { 1746 GE_FUNC_EXIT(sc, ""); 1747 return ENETRESET; 1748 } 1749 1750 /* 1751 * Switch in 1752 */ 1753 sc->sc_flags |= GE_ALLMULTI; 1754 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1755 sc->sc_pcr |= ETH_EPCR_PM; 1756 GE_WRITE(sc, EPCR, sc->sc_pcr); 1757 GE_FUNC_EXIT(sc, ""); 1758 return 0; 1759 } 1760 GE_FUNC_EXIT(sc, ""); 1761 return ENETRESET; 1762 } 1763 1764 prio = GE_RXPRIO_MEDLO; 1765 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1766 1767 if (sc->sc_hashtable == NULL) { 1768 GE_FUNC_EXIT(sc, ""); 1769 return 0; 1770 } 1771 1772 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1773 if (error == EBUSY) { 1774 printf("%s: multichg: tried to %s %s again\n", 1775 sc->sc_dev.dv_xname, 1776 cmd == SIOCDELMULTI ? "remove" : "add", 1777 ether_sprintf(enm->enm_addrlo)); 1778 GE_FUNC_EXIT(sc, ""); 1779 return 0; 1780 } 1781 1782 if (error == ENOENT) { 1783 printf("%s: multichg: failed to remove %s: not in table\n", 1784 sc->sc_dev.dv_xname, 1785 ether_sprintf(enm->enm_addrlo)); 1786 GE_FUNC_EXIT(sc, ""); 1787 return 0; 1788 } 1789 1790 if (error == ENOSPC) { 1791 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1792 sc->sc_dev.dv_xname, 1793 ether_sprintf(enm->enm_addrlo)); 1794 GE_FUNC_EXIT(sc, ""); 1795 return ENETRESET; 1796 } 1797 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1798 sc->sc_dev.dv_xname, 1799 cmd == SIOCDELMULTI ? "remove" : "add", 1800 ether_sprintf(enm->enm_addrlo))); 1801 GE_FUNC_EXIT(sc, ""); 1802 return 0; 1803 } 1804 1805 int 1806 gfe_hash_fill(struct gfe_softc *sc) 1807 { 1808 struct ether_multistep step; 1809 struct ether_multi *enm; 1810 int error; 1811 1812 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1813 1814 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1815 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1816 if (error) 1817 GE_FUNC_EXIT(sc, "!"); 1818 return error; 1819 1820 sc->sc_flags &= ~GE_ALLMULTI; 1821 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1822 sc->sc_pcr &= ~ETH_EPCR_PM; 1823 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1824 while (enm != NULL) { 1825 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1826 sc->sc_flags |= GE_ALLMULTI; 1827 sc->sc_pcr |= ETH_EPCR_PM; 1828 } else { 1829 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1830 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1831 if (error == ENOSPC) 1832 break; 1833 } 1834 ETHER_NEXT_MULTI(step, enm); 1835 } 1836 1837 GE_FUNC_EXIT(sc, ""); 1838 return error; 1839 } 1840 1841 int 1842 gfe_hash_alloc(struct gfe_softc *sc) 1843 { 1844 int error; 1845 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1846 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1847 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1); 1848 if (error) { 1849 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1850 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1851 GE_FUNC_EXIT(sc, ""); 1852 return error; 1853 } 1854 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1855 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1856 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1857 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREREAD); 1858 GE_FUNC_EXIT(sc, ""); 1859 return 0; 1860 } 1861
Indexes created Tue Sep 30 11:09:46 GMT 2025