if_gfe.c revision 1.12
1 /* $NetBSD: if_gfe.c,v 1.12 2003/07/14 15:47:17 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.12 2003/07/14 15:47:17 lukem Exp $"); 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/inttypes.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <sys/callout.h> 58 #include <sys/device.h> 59 #include <sys/errno.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/socket.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/marvell/gtintrreg.h> 82 #include <dev/marvell/gtethreg.h> 83 84 #include <dev/marvell/gtvar.h> 85 #include <dev/marvell/if_gfevar.h> 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) do \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 while (0) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 STATIC int gfe_match (struct device *, struct cfdata *, void *); 148 STATIC void gfe_attach (struct device *, struct device *, void *); 149 150 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 151 size_t, int); 152 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 153 154 STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); 155 STATIC void gfe_ifstart (struct ifnet *); 156 STATIC void gfe_ifwatchdog (struct ifnet *); 157 158 STATIC int gfe_mii_mediachange (struct ifnet *); 159 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 160 STATIC int gfe_mii_read (struct device *, int, int); 161 STATIC void gfe_mii_write (struct device *, int, int, int); 162 STATIC void gfe_mii_statchg (struct device *); 163 164 STATIC void gfe_tick(void *arg); 165 166 STATIC void gfe_tx_restart(void *); 167 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 168 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 169 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 170 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 171 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 172 173 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 174 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 175 STATIC int gfe_rx_prime(struct gfe_softc *); 176 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 177 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 178 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 179 180 STATIC int gfe_intr(void *); 181 182 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 183 184 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 185 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 186 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 187 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 188 u_long); 189 STATIC int gfe_hash_fill(struct gfe_softc *); 190 STATIC int gfe_hash_alloc(struct gfe_softc *); 191 192 /* Linkup to the rest of the kernel */ 193 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 194 gfe_match, gfe_attach, NULL, NULL); 195 196 extern struct cfdriver gfe_cd; 197 198 int 199 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 200 { 201 struct gt_softc *gt = (struct gt_softc *) parent; 202 struct gt_attach_args *ga = aux; 203 uint8_t enaddr[6]; 204 205 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 206 return 0; 207 208 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 209 return 0; 210 211 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 212 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 213 return 0; 214 215 return 1; 216 } 217 218 /* 219 * Attach this instance, and then all the sub-devices 220 */ 221 void 222 gfe_attach(struct device *parent, struct device *self, void *aux) 223 { 224 struct gt_attach_args * const ga = aux; 225 struct gt_softc * const gt = (struct gt_softc *) parent; 226 struct gfe_softc * const sc = (struct gfe_softc *) self; 227 struct ifnet * const ifp = &sc->sc_ec.ec_if; 228 uint32_t data; 229 uint8_t enaddr[6]; 230 int phyaddr; 231 uint32_t sdcr; 232 233 GT_ETHERFOUND(gt, ga); 234 235 sc->sc_gt_memt = ga->ga_memt; 236 sc->sc_gt_memh = ga->ga_memh; 237 sc->sc_dmat = ga->ga_dmat; 238 sc->sc_macno = ga->ga_unit; 239 240 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 241 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 242 aprint_error(": failed to map registers\n"); 243 } 244 245 callout_init(&sc->sc_co); 246 247 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 248 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 249 250 gtget_macaddr(gt, sc->sc_macno, enaddr); 251 252 sc->sc_pcr = GE_READ(sc, EPCR); 253 sc->sc_pcxr = GE_READ(sc, EPCXR); 254 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 255 256 aprint_normal(": address %s", ether_sprintf(enaddr)); 257 258 #if defined(DEBUG) 259 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 260 #endif 261 262 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 263 if (sc->sc_dev.dv_cfdata->cf_flags & 1) { 264 aprint_normal(", phy %d (rmii)", phyaddr); 265 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 266 } else { 267 aprint_normal(", phy %d (mii)", phyaddr); 268 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 269 } 270 sc->sc_pcxr &= ~(3 << 14); 271 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 272 273 if (sc->sc_pcr & ETH_EPCR_EN) { 274 int tries = 1000; 275 /* 276 * Abort transmitter and receiver and wait for them to quiese 277 */ 278 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 279 do { 280 delay(100); 281 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 282 } 283 284 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 285 286 #if defined(DEBUG) 287 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 288 #endif 289 290 /* 291 * Now turn off the GT. If it didn't quiese, too ***ing bad. 292 */ 293 GE_WRITE(sc, EPCR, sc->sc_pcr); 294 GE_WRITE(sc, EIMR, sc->sc_intrmask); 295 sdcr = GE_READ(sc, ESDCR); 296 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 297 sdcr |= ETH_ESDCR_RIFB; 298 GE_WRITE(sc, ESDCR, sdcr); 299 sc->sc_max_frame_length = 1536; 300 301 aprint_normal("\n"); 302 sc->sc_mii.mii_ifp = ifp; 303 sc->sc_mii.mii_readreg = gfe_mii_read; 304 sc->sc_mii.mii_writereg = gfe_mii_write; 305 sc->sc_mii.mii_statchg = gfe_mii_statchg; 306 307 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 308 gfe_mii_mediastatus); 309 310 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 311 MII_OFFSET_ANY, MIIF_NOISOLATE); 312 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 313 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 314 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 315 } else { 316 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 317 } 318 319 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 320 ifp->if_softc = sc; 321 /* ifp->if_mowner = &sc->sc_mowner; */ 322 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 323 #if 0 324 ifp->if_flags |= IFF_DEBUG; 325 #endif 326 ifp->if_ioctl = gfe_ifioctl; 327 ifp->if_start = gfe_ifstart; 328 ifp->if_watchdog = gfe_ifwatchdog; 329 330 if_attach(ifp); 331 ether_ifattach(ifp, enaddr); 332 #if NBPFILTER > 0 333 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 334 #endif 335 #if NRND > 0 336 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 337 #endif 338 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 339 gfe_intr, sc); 340 } 341 342 int 343 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 344 size_t size, int flags) 345 { 346 int error = 0; 347 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 348 gdm->gdm_size = size; 349 gdm->gdm_maxsegs = maxsegs; 350 351 flags |= BUS_DMA_COHERENT; 352 353 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 354 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 355 BUS_DMA_NOWAIT); 356 if (error) 357 goto fail; 358 359 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 360 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 361 if (error) 362 goto fail; 363 364 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 365 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 366 if (error) 367 goto fail; 368 369 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 370 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 371 if (error) 372 goto fail; 373 374 /* invalidate from cache */ 375 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 376 BUS_DMASYNC_PREREAD); 377 fail: 378 if (error) { 379 gfe_dmamem_free(sc, gdm); 380 GE_DPRINTF(sc, (":err=%d", error)); 381 } 382 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 383 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 384 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 385 GE_FUNC_EXIT(sc, ""); 386 return error; 387 } 388 389 void 390 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 391 { 392 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 393 if (gdm->gdm_map) 394 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 395 if (gdm->gdm_kva) 396 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 397 if (gdm->gdm_nsegs > 0) 398 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 399 gdm->gdm_map = NULL; 400 gdm->gdm_kva = NULL; 401 gdm->gdm_nsegs = 0; 402 GE_FUNC_EXIT(sc, ""); 403 } 404 405 int 406 gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 407 { 408 struct gfe_softc * const sc = ifp->if_softc; 409 struct ifreq *ifr = (struct ifreq *) data; 410 struct ifaddr *ifa = (struct ifaddr *) data; 411 int s, error = 0; 412 413 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 414 s = splnet(); 415 416 switch (cmd) { 417 case SIOCSIFADDR: 418 ifp->if_flags |= IFF_UP; 419 switch (ifa->ifa_addr->sa_family) { 420 #ifdef INET 421 case AF_INET: 422 error = gfe_whack(sc, GE_WHACK_START); 423 if (error == 0) 424 arp_ifinit(ifp, ifa); 425 break; 426 #endif 427 default: 428 error = gfe_whack(sc, GE_WHACK_START); 429 break; 430 } 431 break; 432 433 case SIOCSIFFLAGS: 434 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 435 case IFF_UP|IFF_RUNNING:/* active->active, update */ 436 error = gfe_whack(sc, GE_WHACK_CHANGE); 437 break; 438 case IFF_RUNNING: /* not up, so we stop */ 439 error = gfe_whack(sc, GE_WHACK_STOP); 440 break; 441 case IFF_UP: /* not running, so we start */ 442 error = gfe_whack(sc, GE_WHACK_START); 443 break; 444 case 0: /* idle->idle: do nothing */ 445 break; 446 } 447 break; 448 449 case SIOCADDMULTI: 450 case SIOCDELMULTI: 451 error = (cmd == SIOCADDMULTI) 452 ? ether_addmulti(ifr, &sc->sc_ec) 453 : ether_delmulti(ifr, &sc->sc_ec); 454 if (error == ENETRESET) { 455 if (ifp->if_flags & IFF_RUNNING) 456 error = gfe_whack(sc, GE_WHACK_CHANGE); 457 else 458 error = 0; 459 } 460 break; 461 462 case SIOCSIFMTU: 463 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 464 error = EINVAL; 465 break; 466 } 467 ifp->if_mtu = ifr->ifr_mtu; 468 break; 469 470 case SIOCSIFMEDIA: 471 case SIOCGIFMEDIA: 472 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 473 break; 474 475 default: 476 error = EINVAL; 477 break; 478 } 479 splx(s); 480 GE_FUNC_EXIT(sc, ""); 481 return error; 482 } 483 484 void 485 gfe_ifstart(struct ifnet *ifp) 486 { 487 struct gfe_softc * const sc = ifp->if_softc; 488 struct mbuf *m; 489 490 GE_FUNC_ENTER(sc, "gfe_ifstart"); 491 492 if ((ifp->if_flags & IFF_RUNNING) == 0) { 493 GE_FUNC_EXIT(sc, "$"); 494 return; 495 } 496 497 if (sc->sc_txq[GE_TXPRIO_HI] == NULL) { 498 ifp->if_flags |= IFF_OACTIVE; 499 #if defined(DEBUG) || defined(DIAGNOSTIC) 500 printf("%s: ifstart: txq not yet created\n", ifp->if_xname); 501 #endif 502 GE_FUNC_EXIT(sc, ""); 503 return; 504 } 505 506 for (;;) { 507 IF_DEQUEUE(&ifp->if_snd, m); 508 if (m == NULL) { 509 ifp->if_flags &= ~IFF_OACTIVE; 510 GE_FUNC_EXIT(sc, ""); 511 return; 512 } 513 514 /* 515 * No space in the pending queue? try later. 516 */ 517 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq)) 518 break; 519 520 /* 521 * Try to enqueue a mbuf to the device. If that fails, we 522 * can always try to map the next mbuf. 523 */ 524 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq, m); 525 GE_DPRINTF(sc, (">")); 526 #ifndef GE_NOTX 527 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 528 #endif 529 } 530 531 /* 532 * Attempt to queue the mbuf for send failed. 533 */ 534 IF_PREPEND(&ifp->if_snd, m); 535 ifp->if_flags |= IFF_OACTIVE; 536 GE_FUNC_EXIT(sc, "%%"); 537 } 538 539 void 540 gfe_ifwatchdog(struct ifnet *ifp) 541 { 542 struct gfe_softc * const sc = ifp->if_softc; 543 struct gfe_txqueue *txq; 544 545 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 546 printf("%s: device timeout", sc->sc_dev.dv_xname); 547 if ((txq = sc->sc_txq[GE_TXPRIO_HI]) != NULL) { 548 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 549 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 550 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 551 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 552 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 553 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 554 GE_READ(sc, EICR)); 555 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 556 GE_TXDPRESYNC(sc, txq, curtxdnum); 557 } 558 printf("\n"); 559 ifp->if_oerrors++; 560 (void) gfe_whack(sc, GE_WHACK_RESTART); 561 GE_FUNC_EXIT(sc, ""); 562 } 563 564 int 566 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 567 { 568 struct gfe_rxqueue *rxq; 569 volatile struct gt_eth_desc *rxd; 570 const bus_dma_segment_t *ds; 571 int error; 572 int idx; 573 bus_addr_t nxtaddr; 574 bus_size_t boff; 575 576 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 577 GE_DPRINTF(sc, ("(%d)", rxprio)); 578 if (sc->sc_rxq[rxprio] != NULL) { 579 GE_FUNC_EXIT(sc, ""); 580 return 0; 581 } 582 583 rxq = (struct gfe_rxqueue *) malloc(sizeof(*rxq), M_DEVBUF, M_NOWAIT); 584 if (rxq == NULL) { 585 GE_FUNC_EXIT(sc, "!"); 586 return ENOMEM; 587 } 588 589 memset(rxq, 0, sizeof(*rxq)); 590 591 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 592 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 593 if (error) { 594 free(rxq, M_DEVBUF); 595 GE_FUNC_EXIT(sc, "!!"); 596 return error; 597 } 598 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 599 GE_RXBUF_MEMSIZE, 0); 600 if (error) { 601 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 602 free(rxq, M_DEVBUF); 603 GE_FUNC_EXIT(sc, "!!!"); 604 return error; 605 } 606 607 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_TXMEM_SIZE); 608 609 sc->sc_rxq[rxprio] = rxq; 610 rxq->rxq_descs = 611 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 612 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 613 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 614 rxq->rxq_fi = 0; 615 rxq->rxq_active = GE_RXDESC_MAX; 616 for (idx = 0, rxd = rxq->rxq_descs, 617 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 618 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 619 idx < GE_RXDESC_MAX; 620 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 621 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 622 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 623 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 624 /* 625 * update the nxtptr to point to the next txd. 626 */ 627 if (idx == GE_RXDESC_MAX - 1) 628 nxtaddr = rxq->rxq_desc_busaddr; 629 rxd->ed_nxtptr = htogt32(nxtaddr); 630 boff += GE_RXBUF_SIZE; 631 if (boff == ds->ds_len) { 632 ds++; 633 boff = 0; 634 } 635 } 636 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 637 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 638 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 639 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 640 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 641 BUS_DMASYNC_PREREAD); 642 643 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 644 switch (rxprio) { 645 case GE_RXPRIO_HI: 646 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 647 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 648 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 649 break; 650 case GE_RXPRIO_MEDHI: 651 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 652 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 653 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 654 break; 655 case GE_RXPRIO_MEDLO: 656 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 657 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 658 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 659 break; 660 case GE_RXPRIO_LO: 661 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 662 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 663 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 664 break; 665 } 666 GE_FUNC_EXIT(sc, ""); 667 return error; 668 } 669 670 void 671 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 672 { 673 struct ifnet * const ifp = &sc->sc_ec.ec_if; 674 struct gfe_rxqueue * const rxq = sc->sc_rxq[rxprio]; 675 struct mbuf *m = rxq->rxq_curpkt; 676 677 GE_FUNC_ENTER(sc, "gfe_rx_get"); 678 GE_DPRINTF(sc, ("(%d)", rxprio)); 679 680 while (rxq->rxq_active > 0) { 681 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 682 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 683 const struct ether_header *eh; 684 unsigned int cmdsts; 685 size_t buflen; 686 687 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 688 cmdsts = gt32toh(rxd->ed_cmdsts); 689 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 690 rxq->rxq_cmdsts = cmdsts; 691 /* 692 * Sometimes the GE "forgets" to reset the ownership bit. 693 * But if the length has been rewritten, the packet is ours 694 * so pretend the O bit is set. 695 */ 696 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 697 if ((cmdsts & RX_CMD_O) && buflen == 0) { 698 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 699 break; 700 } 701 702 /* 703 * If this is not a single buffer packet with no errors 704 * or for some reason it's bigger than our frame size, 705 * ignore it and go to the next packet. 706 */ 707 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 708 (RX_CMD_F|RX_CMD_L) || 709 buflen > sc->sc_max_frame_length) { 710 GE_DPRINTF(sc, ("!")); 711 --rxq->rxq_active; 712 ifp->if_ipackets++; 713 ifp->if_ierrors++; 714 goto give_it_back; 715 } 716 717 if (m == NULL) { 718 MGETHDR(m, M_DONTWAIT, MT_DATA); 719 if (m == NULL) { 720 GE_DPRINTF(sc, ("?")); 721 break; 722 } 723 } 724 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 725 MCLGET(m, M_DONTWAIT); 726 if ((m->m_flags & M_EXT) == 0) { 727 GE_DPRINTF(sc, ("?")); 728 break; 729 } 730 } 731 m->m_data += 2; 732 m->m_len = 0; 733 m->m_pkthdr.len = 0; 734 m->m_pkthdr.rcvif = ifp; 735 rxq->rxq_cmdsts = cmdsts; 736 --rxq->rxq_active; 737 738 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 739 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 740 741 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 742 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 743 m->m_len = buflen; 744 m->m_pkthdr.len = buflen; 745 m->m_flags |= M_HASFCS; 746 747 ifp->if_ipackets++; 748 #if NBPFILTER > 0 749 if (ifp->if_bpf != NULL) 750 bpf_mtap(ifp->if_bpf, m); 751 #endif 752 753 eh = (const struct ether_header *) m->m_data; 754 if ((ifp->if_flags & IFF_PROMISC) || 755 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 756 (rxq->rxq_cmdsts & RX_STS_HE) || 757 (eh->ether_dhost[0] & 1) != 0 || 758 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 759 ETHER_ADDR_LEN) == 0) { 760 (*ifp->if_input)(ifp, m); 761 m = NULL; 762 GE_DPRINTF(sc, (">")); 763 } else { 764 m->m_len = 0; 765 m->m_pkthdr.len = 0; 766 GE_DPRINTF(sc, ("+")); 767 } 768 rxq->rxq_cmdsts = 0; 769 770 give_it_back: 771 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 772 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 773 #if 0 774 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 775 rxq->rxq_fi, 776 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 777 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 778 #endif 779 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 780 if (++rxq->rxq_fi == GE_RXDESC_MAX) 781 rxq->rxq_fi = 0; 782 rxq->rxq_active++; 783 } 784 rxq->rxq_curpkt = m; 785 GE_FUNC_EXIT(sc, ""); 786 } 787 788 uint32_t 789 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 790 { 791 struct ifnet * const ifp = &sc->sc_ec.ec_if; 792 struct gfe_rxqueue *rxq; 793 uint32_t rxbits; 794 #define RXPRIO_DECODER 0xffffaa50 795 GE_FUNC_ENTER(sc, "gfe_rx_process"); 796 797 rxbits = ETH_IR_RxBuffer_GET(cause); 798 while (rxbits) { 799 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 800 GE_DPRINTF(sc, ("%1x", rxbits)); 801 rxbits &= ~(1 << rxprio); 802 gfe_rx_get(sc, rxprio); 803 } 804 805 rxbits = ETH_IR_RxError_GET(cause); 806 while (rxbits) { 807 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 808 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 809 int idx; 810 rxbits &= ~(1 << rxprio); 811 rxq = sc->sc_rxq[rxprio]; 812 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 813 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 814 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 815 sc->sc_tickflags |= GE_TICK_RX_RESTART; 816 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 817 } 818 ifp->if_ierrors++; 819 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 820 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 821 memset(masks, 0, sizeof(masks)); 822 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 823 0, rxq->rxq_desc_mem.gdm_size, 824 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 825 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 826 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 827 828 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 829 masks[idx/32] |= 1 << (idx & 31); 830 } 831 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 832 0, rxq->rxq_desc_mem.gdm_size, 833 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 834 #if defined(DEBUG) 835 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 836 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 837 rxq->rxq_cmdsts, masks[0], masks[1]); 838 #endif 839 } 840 if ((intrmask & ETH_IR_RxBits) == 0) 841 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 842 843 GE_FUNC_EXIT(sc, ""); 844 return intrmask; 845 } 846 847 int 848 gfe_rx_prime(struct gfe_softc *sc) 849 { 850 struct gfe_rxqueue *rxq; 851 int error; 852 853 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 854 855 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 856 if (error) 857 goto bail; 858 rxq = sc->sc_rxq[GE_RXPRIO_HI]; 859 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 860 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 861 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 862 } 863 sc->sc_intrmask |= rxq->rxq_intrbits; 864 865 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 866 if (error) 867 goto bail; 868 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 869 rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 870 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 871 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 872 sc->sc_intrmask |= rxq->rxq_intrbits; 873 } 874 875 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 876 if (error) 877 goto bail; 878 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 879 rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 880 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 881 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 882 sc->sc_intrmask |= rxq->rxq_intrbits; 883 } 884 885 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 886 if (error) 887 goto bail; 888 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 889 rxq = sc->sc_rxq[GE_RXPRIO_LO]; 890 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 891 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 892 sc->sc_intrmask |= rxq->rxq_intrbits; 893 } 894 895 bail: 896 GE_FUNC_EXIT(sc, ""); 897 return error; 898 } 899 900 void 901 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 902 { 903 struct gfe_rxqueue *rxq = sc->sc_rxq[rxprio]; 904 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 905 if (rxq == NULL) { 906 GE_FUNC_EXIT(sc, ""); 907 return; 908 } 909 910 if (rxq->rxq_curpkt) 911 m_freem(rxq->rxq_curpkt); 912 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 913 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 914 free(rxq, M_DEVBUF); 915 sc->sc_rxq[rxprio] = NULL; 916 GE_FUNC_EXIT(sc, ""); 917 } 918 919 void 920 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 921 { 922 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 923 sc->sc_flags &= ~GE_RXACTIVE; 924 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 925 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 926 GE_WRITE(sc, EIMR, sc->sc_intrmask); 927 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 928 do { 929 delay(10); 930 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 931 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 932 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 933 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 934 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 935 GE_FUNC_EXIT(sc, ""); 936 } 937 938 void 940 gfe_tick(void *arg) 941 { 942 struct gfe_softc * const sc = arg; 943 uint32_t intrmask; 944 unsigned int tickflags; 945 int s; 946 947 GE_FUNC_ENTER(sc, "gfe_tick"); 948 949 s = splnet(); 950 951 tickflags = sc->sc_tickflags; 952 sc->sc_tickflags = 0; 953 intrmask = sc->sc_intrmask; 954 if (tickflags & GE_TICK_TX_IFSTART) 955 gfe_ifstart(&sc->sc_ec.ec_if); 956 if (tickflags & GE_TICK_RX_RESTART) { 957 intrmask |= sc->sc_idlemask; 958 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 959 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_HI]; 960 rxq->rxq_fi = 0; 961 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 962 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 963 } 964 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 965 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 966 rxq->rxq_fi = 0; 967 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 968 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 969 } 970 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 971 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 972 rxq->rxq_fi = 0; 973 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 974 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 975 } 976 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 977 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_LO]; 978 rxq->rxq_fi = 0; 979 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 980 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 981 } 982 sc->sc_idlemask = 0; 983 } 984 if (intrmask != sc->sc_intrmask) { 985 sc->sc_intrmask = intrmask; 986 GE_WRITE(sc, EIMR, sc->sc_intrmask); 987 } 988 gfe_intr(sc); 989 splx(s); 990 991 GE_FUNC_EXIT(sc, ""); 992 } 993 994 int 995 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 996 { 997 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 998 struct ifnet * const ifp = &sc->sc_ec.ec_if; 999 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1000 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1001 uint32_t intrmask = sc->sc_intrmask; 1002 size_t buflen; 1003 struct mbuf *m; 1004 1005 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1006 1007 /* 1008 * Anything in the pending queue to enqueue? if not, punt. 1009 * otherwise grab its dmamap. 1010 */ 1011 if ((m = txq->txq_pendq.ifq_head) == NULL) { 1012 GE_FUNC_EXIT(sc, "-"); 1013 return 0; 1014 } 1015 1016 /* 1017 * Have we [over]consumed our limit of descriptors? 1018 * Do we have enough free descriptors? 1019 */ 1020 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1021 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1022 uint32_t cmdsts; 1023 size_t pktlen; 1024 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1025 cmdsts = gt32toh(txd2->ed_cmdsts); 1026 if (cmdsts & TX_CMD_O) { 1027 int nextin; 1028 /* 1029 * Sometime the Discovery forgets to update the 1030 * last descriptor. See if we own the descriptor 1031 * after it (since we know we've turned that to 1032 * the discovery and if we owned it, the Discovery 1033 * gave it back). If we do, we know the Discovery 1034 * gave back this one but forgot to mark it as ours. 1035 */ 1036 nextin = txq->txq_fi + 1; 1037 if (nextin == GE_TXDESC_MAX) 1038 nextin = 0; 1039 GE_TXDPOSTSYNC(sc, txq, nextin); 1040 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1041 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1042 GE_TXDPRESYNC(sc, txq, nextin); 1043 GE_FUNC_EXIT(sc, "@"); 1044 return 0; 1045 } 1046 #ifdef DEBUG 1047 printf("%s: txenqueue: transmitter resynced at %d\n", 1048 sc->sc_dev.dv_xname, txq->txq_fi); 1049 #endif 1050 } 1051 if (++txq->txq_fi == GE_TXDESC_MAX) 1052 txq->txq_fi = 0; 1053 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1054 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1055 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1056 txq->txq_nactive--; 1057 1058 /* statistics */ 1059 ifp->if_opackets++; 1060 if (cmdsts & TX_STS_ES) 1061 ifp->if_oerrors++; 1062 GE_DPRINTF(sc, ("%%")); 1063 } 1064 1065 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1066 1067 /* 1068 * If this packet would wrap around the end of the buffer, reset back 1069 * to the beginning. 1070 */ 1071 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1072 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1073 txq->txq_outptr = 0; 1074 } 1075 1076 /* 1077 * Make sure the output packet doesn't run over the beginning of 1078 * what we've already given the GT. 1079 */ 1080 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1081 txq->txq_outptr + buflen > txq->txq_inptr) { 1082 intrmask |= txq->txq_intrbits & 1083 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1084 if (sc->sc_intrmask != intrmask) { 1085 sc->sc_intrmask = intrmask; 1086 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1087 } 1088 GE_FUNC_EXIT(sc, "#"); 1089 return 0; 1090 } 1091 1092 /* 1093 * The end-of-list descriptor we put on last time is the starting point 1094 * for this packet. The GT is supposed to terminate list processing on 1095 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1096 * must terminate the list. 1097 */ 1098 intrmask = sc->sc_intrmask; 1099 1100 m_copydata(m, 0, m->m_pkthdr.len, 1101 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1102 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1103 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1104 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1105 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1106 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1107 1108 /* 1109 * Request a buffer interrupt every 2/3 of the way thru the transmit 1110 * buffer. 1111 */ 1112 txq->txq_ei_gapcount += buflen; 1113 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1114 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1115 txq->txq_ei_gapcount = 0; 1116 } else { 1117 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1118 } 1119 #if 0 1120 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1121 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1122 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1123 #endif 1124 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1125 1126 txq->txq_outptr += buflen; 1127 /* 1128 * Tell the SDMA engine to "Fetch!" 1129 */ 1130 GE_WRITE(sc, ESDCMR, 1131 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1132 1133 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1134 1135 /* 1136 * Update the last out appropriately. 1137 */ 1138 txq->txq_nactive++; 1139 if (++txq->txq_lo == GE_TXDESC_MAX) 1140 txq->txq_lo = 0; 1141 1142 /* 1143 * Move mbuf from the pending queue to the snd queue. 1144 */ 1145 IF_DEQUEUE(&txq->txq_pendq, m); 1146 #if NBPFILTER > 0 1147 if (ifp->if_bpf != NULL) 1148 bpf_mtap(ifp->if_bpf, m); 1149 #endif 1150 m_freem(m); 1151 ifp->if_flags &= ~IFF_OACTIVE; 1152 1153 /* 1154 * Since we have put an item into the packet queue, we now want 1155 * an interrupt when the transmit queue finishes processing the 1156 * list. But only update the mask if needs changing. 1157 */ 1158 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1159 if (sc->sc_intrmask != intrmask) { 1160 sc->sc_intrmask = intrmask; 1161 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1162 } 1163 if (ifp->if_timer == 0) 1164 ifp->if_timer = 5; 1165 GE_FUNC_EXIT(sc, "*"); 1166 return 1; 1167 } 1168 1169 uint32_t 1170 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1171 { 1172 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1173 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1174 1175 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1176 1177 if (txq == NULL) { 1178 GE_FUNC_EXIT(sc, ""); 1179 return intrmask; 1180 } 1181 1182 while (txq->txq_nactive > 0) { 1183 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1184 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1185 uint32_t cmdsts; 1186 size_t pktlen; 1187 1188 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1189 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1190 int nextin; 1191 1192 if (txq->txq_nactive == 1) { 1193 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1194 GE_FUNC_EXIT(sc, ""); 1195 return intrmask; 1196 } 1197 /* 1198 * Sometimes the Discovery forgets to update the 1199 * ownership bit in the descriptor. See if we own the 1200 * descriptor after it (since we know we've turned 1201 * that to the Discovery and if we own it now then the 1202 * Discovery gave it back). If we do, we know the 1203 * Discovery gave back this one but forgot to mark it 1204 * as ours. 1205 */ 1206 nextin = txq->txq_fi + 1; 1207 if (nextin == GE_TXDESC_MAX) 1208 nextin = 0; 1209 GE_TXDPOSTSYNC(sc, txq, nextin); 1210 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1211 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1212 GE_TXDPRESYNC(sc, txq, nextin); 1213 GE_FUNC_EXIT(sc, ""); 1214 return intrmask; 1215 } 1216 #ifdef DEBUG 1217 printf("%s: txdone: transmitter resynced at %d\n", 1218 sc->sc_dev.dv_xname, txq->txq_fi); 1219 #endif 1220 } 1221 #if 0 1222 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1223 txq->txq_lo, 1224 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1225 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1226 #endif 1227 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1228 if (++txq->txq_fi == GE_TXDESC_MAX) 1229 txq->txq_fi = 0; 1230 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1231 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1232 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1233 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1234 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1235 1236 /* statistics */ 1237 ifp->if_opackets++; 1238 if (cmdsts & TX_STS_ES) 1239 ifp->if_oerrors++; 1240 1241 /* txd->ed_bufptr = 0; */ 1242 1243 ifp->if_timer = 5; 1244 --txq->txq_nactive; 1245 } 1246 if (txq->txq_nactive != 0) 1247 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1248 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1249 ifp->if_timer = 0; 1250 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1251 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1252 GE_FUNC_EXIT(sc, ""); 1253 return intrmask; 1254 } 1255 1256 int 1257 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1258 { 1259 struct gfe_txqueue *txq; 1260 volatile struct gt_eth_desc *txd; 1261 unsigned int i; 1262 bus_addr_t addr; 1263 1264 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1265 1266 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1267 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1268 1269 if ((txq = sc->sc_txq[txprio]) == NULL) { 1270 int error; 1271 txq = (struct gfe_txqueue *) malloc(sizeof(*txq), 1272 M_DEVBUF, M_NOWAIT); 1273 if (txq == NULL) { 1274 GE_FUNC_EXIT(sc, ""); 1275 return ENOMEM; 1276 } 1277 memset(txq, 0, sizeof(*txq)); 1278 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1279 GE_TXMEM_SIZE, BUS_DMA_NOCACHE); 1280 if (error) { 1281 free(txq, M_DEVBUF); 1282 GE_FUNC_EXIT(sc, ""); 1283 return error; 1284 } 1285 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, 1286 GE_TXBUF_SIZE, 0); 1287 if (error) { 1288 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1289 free(txq, M_DEVBUF); 1290 GE_FUNC_EXIT(sc, ""); 1291 return error; 1292 } 1293 sc->sc_txq[txprio] = txq; 1294 } 1295 1296 txq->txq_descs = 1297 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1298 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1299 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1300 1301 txq->txq_pendq.ifq_maxlen = 10; 1302 txq->txq_ei_gapcount = 0; 1303 txq->txq_nactive = 0; 1304 txq->txq_fi = 0; 1305 txq->txq_lo = 0; 1306 txq->txq_inptr = GE_TXBUF_SIZE; 1307 txq->txq_outptr = 0; 1308 for (i = 0, txd = txq->txq_descs, 1309 addr = txq->txq_desc_busaddr + sizeof(*txd); 1310 i < GE_TXDESC_MAX - 1; 1311 i++, txd++, addr += sizeof(*txd)) { 1312 /* 1313 * update the nxtptr to point to the next txd. 1314 */ 1315 txd->ed_cmdsts = 0; 1316 txd->ed_nxtptr = htogt32(addr); 1317 } 1318 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1319 htogt32(txq->txq_desc_busaddr); 1320 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1321 GE_TXMEM_SIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1322 1323 switch (txprio) { 1324 case GE_TXPRIO_HI: 1325 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1326 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1327 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1328 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1329 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1330 break; 1331 1332 case GE_TXPRIO_LO: 1333 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1334 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1335 txq->txq_epsrbits = ETH_EPSR_TxLow; 1336 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1337 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1338 break; 1339 1340 case GE_TXPRIO_NONE: 1341 break; 1342 } 1343 #if 0 1344 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1345 gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); 1346 GE_DPRINTF(sc, (")")); 1347 #endif 1348 1349 /* 1350 * If we are restarting, there may be packets in the pending queue 1351 * waiting to be enqueued. Try enqueuing packets from both priority 1352 * queues until the pending queue is empty or there no room for them 1353 * on the device. 1354 */ 1355 while (gfe_tx_enqueue(sc, txprio)) 1356 continue; 1357 1358 GE_FUNC_EXIT(sc, ""); 1359 return 0; 1360 } 1361 1362 void 1363 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1364 { 1365 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1366 1367 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1368 if (txq == NULL) { 1369 GE_FUNC_EXIT(sc, ""); 1370 return; 1371 } 1372 1373 if (!flush) { 1374 GE_FUNC_EXIT(sc, ""); 1375 return; 1376 } 1377 1378 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1379 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1380 free(txq, M_DEVBUF); 1381 sc->sc_txq[txprio] = NULL; 1382 GE_FUNC_EXIT(sc, "-F"); 1383 } 1384 1385 void 1386 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1387 { 1388 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1389 1390 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1391 1392 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1393 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1394 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1395 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1396 1397 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1398 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1399 1400 sc->sc_ec.ec_if.if_timer = 0; 1401 GE_FUNC_EXIT(sc, ""); 1402 } 1403 1404 int 1406 gfe_intr(void *arg) 1407 { 1408 struct gfe_softc * const sc = arg; 1409 uint32_t cause; 1410 uint32_t intrmask = sc->sc_intrmask; 1411 int claim = 0; 1412 int cnt; 1413 1414 GE_FUNC_ENTER(sc, "gfe_intr"); 1415 1416 for (cnt = 0; cnt < 4; cnt++) { 1417 if (sc->sc_intrmask != intrmask) { 1418 sc->sc_intrmask = intrmask; 1419 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1420 } 1421 cause = GE_READ(sc, EICR); 1422 cause &= sc->sc_intrmask; 1423 GE_DPRINTF(sc, (".%#x", cause)); 1424 if (cause == 0) 1425 break; 1426 1427 claim = 1; 1428 1429 GE_WRITE(sc, EICR, ~cause); 1430 #ifndef GE_NORX 1431 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1432 intrmask = gfe_rx_process(sc, cause, intrmask); 1433 #endif 1434 1435 #ifndef GE_NOTX 1436 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1437 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1438 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1439 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1440 #endif 1441 if (cause & ETH_IR_MIIPhySTC) { 1442 sc->sc_flags |= GE_PHYSTSCHG; 1443 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1444 } 1445 } 1446 1447 GE_FUNC_EXIT(sc, ""); 1448 return claim; 1449 } 1450 1451 int 1453 gfe_mii_mediachange (struct ifnet *ifp) 1454 { 1455 struct gfe_softc *sc = ifp->if_softc; 1456 1457 if (ifp->if_flags & IFF_UP) 1458 mii_mediachg(&sc->sc_mii); 1459 1460 return (0); 1461 } 1462 void 1463 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1464 { 1465 struct gfe_softc *sc = ifp->if_softc; 1466 1467 if (sc->sc_flags & GE_PHYSTSCHG) { 1468 sc->sc_flags &= ~GE_PHYSTSCHG; 1469 mii_pollstat(&sc->sc_mii); 1470 } 1471 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1472 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1473 } 1474 1475 int 1476 gfe_mii_read (struct device *self, int phy, int reg) 1477 { 1478 return gt_mii_read(self, self->dv_parent, phy, reg); 1479 } 1480 1481 void 1482 gfe_mii_write (struct device *self, int phy, int reg, int value) 1483 { 1484 gt_mii_write(self, self->dv_parent, phy, reg, value); 1485 } 1486 1487 void 1488 gfe_mii_statchg (struct device *self) 1489 { 1490 /* struct gfe_softc *sc = (struct gfe_softc *) self; */ 1491 /* do nothing? */ 1492 } 1493 1494 int 1496 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1497 { 1498 int error = 0; 1499 GE_FUNC_ENTER(sc, "gfe_whack"); 1500 1501 switch (op) { 1502 case GE_WHACK_RESTART: 1503 #ifndef GE_NOTX 1504 gfe_tx_stop(sc, op); 1505 #endif 1506 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1507 /* FALLTHROUGH */ 1508 case GE_WHACK_START: 1509 #ifndef GE_NOHASH 1510 if (error == 0 && sc->sc_hashtable == NULL) { 1511 error = gfe_hash_alloc(sc); 1512 if (error) 1513 break; 1514 } 1515 if (op != GE_WHACK_RESTART) 1516 gfe_hash_fill(sc); 1517 #endif 1518 #ifndef GE_NORX 1519 if (op != GE_WHACK_RESTART) { 1520 error = gfe_rx_prime(sc); 1521 if (error) 1522 break; 1523 } 1524 #endif 1525 #ifndef GE_NOTX 1526 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1527 if (error) 1528 break; 1529 #endif 1530 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1531 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1532 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1533 GE_WRITE(sc, EICR, 0); 1534 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1535 #ifndef GE_NOHASH 1536 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1537 #endif 1538 #ifndef GE_NORX 1539 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1540 sc->sc_flags |= GE_RXACTIVE; 1541 #endif 1542 /* FALLTHROUGH */ 1543 case GE_WHACK_CHANGE: 1544 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1545 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1546 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1547 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1548 gfe_ifstart(&sc->sc_ec.ec_if); 1549 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1550 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1551 GE_FUNC_EXIT(sc, ""); 1552 return error; 1553 case GE_WHACK_STOP: 1554 break; 1555 } 1556 1557 #ifdef GE_DEBUG 1558 if (error) 1559 GE_DPRINTF(sc, (" failed: %d\n", error)); 1560 #endif 1561 GE_WRITE(sc, EPCR, sc->sc_pcr); 1562 GE_WRITE(sc, EIMR, 0); 1563 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1564 #ifndef GE_NOTX 1565 gfe_tx_stop(sc, GE_WHACK_STOP); 1566 #endif 1567 #ifndef GE_NORX 1568 gfe_rx_stop(sc, GE_WHACK_STOP); 1569 #endif 1570 #ifndef GE_NOHASH 1571 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1572 sc->sc_hashtable = NULL; 1573 #endif 1574 1575 GE_FUNC_EXIT(sc, ""); 1576 return error; 1577 } 1578 1579 int 1581 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1582 { 1583 uint32_t w0, add0, add1; 1584 uint32_t result; 1585 1586 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1587 add0 = ((uint32_t) eaddr[5] << 0) | 1588 ((uint32_t) eaddr[4] << 8) | 1589 ((uint32_t) eaddr[3] << 16); 1590 1591 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1592 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1593 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1594 1595 add1 = ((uint32_t) eaddr[2] << 0) | 1596 ((uint32_t) eaddr[1] << 8) | 1597 ((uint32_t) eaddr[0] << 16); 1598 1599 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1600 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1601 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1602 1603 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1604 /* 1605 * hashResult is the 15 bits Hash entry address. 1606 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1607 * MAC address, by nibble swapping in every byte (i.e MAC address 1608 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1609 */ 1610 1611 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1612 /* 1613 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1614 * 1615 * hashFunc0 calculates the hashResult in the following manner: 1616 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1617 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1618 */ 1619 result = (add0 & 3) | ((add0 >> 6) & ~3); 1620 result ^= (add0 >> 15) ^ (add1 >> 0); 1621 result &= 0x1ff; 1622 /* 1623 * hashResult[14:9] = ethernetADD[7:2] 1624 */ 1625 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1626 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1627 } else { 1628 #define TRIBITFLIP 073516240 /* yes its in octal */ 1629 /* 1630 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1631 * 1632 * hashFunc1 calculates the hashResult in the following manner: 1633 * hashResult[08:00] = ethernetADD[06:14] 1634 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1635 */ 1636 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1637 /* 1638 * Now bitswap those 9 bits 1639 */ 1640 result = 0; 1641 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1642 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1643 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1644 1645 /* 1646 * hashResult[14:09] = ethernetADD[00:05] 1647 */ 1648 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1649 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1650 GE_DPRINTF(sc, ("1(%#x)", result)); 1651 } 1652 GE_FUNC_EXIT(sc, ""); 1653 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1654 } 1655 1656 int 1657 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1658 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1659 { 1660 uint64_t he; 1661 uint64_t *maybe_he_p = NULL; 1662 int limit; 1663 int hash; 1664 int maybe_hash = 0; 1665 1666 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1667 1668 hash = gfe_hash_compute(sc, eaddr); 1669 1670 if (sc->sc_hashtable == NULL) { 1671 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1672 __LINE__); 1673 } 1674 1675 /* 1676 * Assume we are going to insert so create the hash entry we 1677 * are going to insert. We also use it to match entries we 1678 * will be removing. 1679 */ 1680 he = ((uint64_t) eaddr[5] << 43) | 1681 ((uint64_t) eaddr[4] << 35) | 1682 ((uint64_t) eaddr[3] << 27) | 1683 ((uint64_t) eaddr[2] << 19) | 1684 ((uint64_t) eaddr[1] << 11) | 1685 ((uint64_t) eaddr[0] << 3) | 1686 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1687 1688 /* 1689 * The GT will search upto 12 entries for a hit, so we must mimic that. 1690 */ 1691 hash &= sc->sc_hashmask / sizeof(he); 1692 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1693 /* 1694 * Does the GT wrap at the end, stop at the, or overrun the 1695 * end? Assume it wraps for now. Stash a copy of the 1696 * current hash entry. 1697 */ 1698 uint64_t *he_p = &sc->sc_hashtable[hash]; 1699 uint64_t thishe = *he_p; 1700 1701 /* 1702 * If the hash entry isn't valid, that break the chain. And 1703 * this entry a good candidate for reuse. 1704 */ 1705 if ((thishe & HSH_V) == 0) { 1706 maybe_he_p = he_p; 1707 break; 1708 } 1709 1710 /* 1711 * If the hash entry has the same address we are looking for 1712 * then ... if we are removing and the skip bit is set, its 1713 * already been removed. if are adding and the skip bit is 1714 * clear, then its already added. In either return EBUSY 1715 * indicating the op has already been done. Otherwise flip 1716 * the skip bit and return 0. 1717 */ 1718 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1719 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1720 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1721 return EBUSY; 1722 *he_p = thishe ^ HSH_S; 1723 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1724 hash * sizeof(he), sizeof(he), 1725 BUS_DMASYNC_PREWRITE); 1726 GE_FUNC_EXIT(sc, "^"); 1727 return 0; 1728 } 1729 1730 /* 1731 * If we haven't found a slot for the entry and this entry 1732 * is currently being skipped, return this entry. 1733 */ 1734 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1735 maybe_he_p = he_p; 1736 maybe_hash = hash; 1737 } 1738 1739 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1740 } 1741 1742 /* 1743 * If we got here, then there was no entry to remove. 1744 */ 1745 if (op == GE_HASH_REMOVE) { 1746 GE_FUNC_EXIT(sc, "?"); 1747 return ENOENT; 1748 } 1749 1750 /* 1751 * If we couldn't find a slot, return an error. 1752 */ 1753 if (maybe_he_p == NULL) { 1754 GE_FUNC_EXIT(sc, "!"); 1755 return ENOSPC; 1756 } 1757 1758 /* Update the entry. 1759 */ 1760 *maybe_he_p = he; 1761 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1762 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1763 GE_FUNC_EXIT(sc, "+"); 1764 return 0; 1765 } 1766 1767 int 1768 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1769 { 1770 struct gfe_softc * const sc = ec->ec_if.if_softc; 1771 int error; 1772 enum gfe_hash_op op; 1773 enum gfe_rxprio prio; 1774 1775 GE_FUNC_ENTER(sc, "hash_multichg"); 1776 /* 1777 * Is this a wildcard entry? If so and its being removed, recompute. 1778 */ 1779 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1780 if (cmd == SIOCDELMULTI) { 1781 GE_FUNC_EXIT(sc, ""); 1782 return ENETRESET; 1783 } 1784 1785 /* 1786 * Switch in 1787 */ 1788 sc->sc_flags |= GE_ALLMULTI; 1789 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1790 sc->sc_pcr |= ETH_EPCR_PM; 1791 GE_WRITE(sc, EPCR, sc->sc_pcr); 1792 GE_FUNC_EXIT(sc, ""); 1793 return 0; 1794 } 1795 GE_FUNC_EXIT(sc, ""); 1796 return ENETRESET; 1797 } 1798 1799 prio = GE_RXPRIO_MEDLO; 1800 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1801 1802 if (sc->sc_hashtable == NULL) { 1803 GE_FUNC_EXIT(sc, ""); 1804 return 0; 1805 } 1806 1807 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1808 if (error == EBUSY) { 1809 printf("%s: multichg: tried to %s %s again\n", 1810 sc->sc_dev.dv_xname, 1811 cmd == SIOCDELMULTI ? "remove" : "add", 1812 ether_sprintf(enm->enm_addrlo)); 1813 GE_FUNC_EXIT(sc, ""); 1814 return 0; 1815 } 1816 1817 if (error == ENOENT) { 1818 printf("%s: multichg: failed to remove %s: not in table\n", 1819 sc->sc_dev.dv_xname, 1820 ether_sprintf(enm->enm_addrlo)); 1821 GE_FUNC_EXIT(sc, ""); 1822 return 0; 1823 } 1824 1825 if (error == ENOSPC) { 1826 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1827 sc->sc_dev.dv_xname, 1828 ether_sprintf(enm->enm_addrlo)); 1829 GE_FUNC_EXIT(sc, ""); 1830 return ENETRESET; 1831 } 1832 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1833 sc->sc_dev.dv_xname, 1834 cmd == SIOCDELMULTI ? "remove" : "add", 1835 ether_sprintf(enm->enm_addrlo))); 1836 GE_FUNC_EXIT(sc, ""); 1837 return 0; 1838 } 1839 1840 int 1841 gfe_hash_fill(struct gfe_softc *sc) 1842 { 1843 struct ether_multistep step; 1844 struct ether_multi *enm; 1845 int error; 1846 1847 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1848 1849 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1850 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1851 if (error) 1852 GE_FUNC_EXIT(sc, "!"); 1853 return error; 1854 1855 sc->sc_flags &= ~GE_ALLMULTI; 1856 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1857 sc->sc_pcr &= ~ETH_EPCR_PM; 1858 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1859 while (enm != NULL) { 1860 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1861 sc->sc_flags |= GE_ALLMULTI; 1862 sc->sc_pcr |= ETH_EPCR_PM; 1863 } else { 1864 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1865 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1866 if (error == ENOSPC) 1867 break; 1868 } 1869 ETHER_NEXT_MULTI(step, enm); 1870 } 1871 1872 GE_FUNC_EXIT(sc, ""); 1873 return error; 1874 } 1875 1876 int 1877 gfe_hash_alloc(struct gfe_softc *sc) 1878 { 1879 int error; 1880 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1881 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1882 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1883 BUS_DMA_NOCACHE); 1884 if (error) { 1885 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1886 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1887 GE_FUNC_EXIT(sc, ""); 1888 return error; 1889 } 1890 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1891 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1892 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1893 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1894 GE_FUNC_EXIT(sc, ""); 1895 return 0; 1896 } 1897
Indexes created Tue Sep 30 11:09:46 GMT 2025