if_gfe.c revision 1.14
1 /* $NetBSD: if_gfe.c,v 1.14 2005/01/30 19:19:24 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.14 2005/01/30 19:19:24 thorpej Exp $"); 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/inttypes.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <sys/callout.h> 58 #include <sys/device.h> 59 #include <sys/errno.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/socket.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/marvell/gtintrreg.h> 82 #include <dev/marvell/gtethreg.h> 83 84 #include <dev/marvell/gtvar.h> 85 #include <dev/marvell/if_gfevar.h> 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) do \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 while (0) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 STATIC int gfe_match (struct device *, struct cfdata *, void *); 148 STATIC void gfe_attach (struct device *, struct device *, void *); 149 150 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 151 size_t, int); 152 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 153 154 STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); 155 STATIC void gfe_ifstart (struct ifnet *); 156 STATIC void gfe_ifwatchdog (struct ifnet *); 157 158 STATIC int gfe_mii_mediachange (struct ifnet *); 159 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 160 STATIC int gfe_mii_read (struct device *, int, int); 161 STATIC void gfe_mii_write (struct device *, int, int, int); 162 STATIC void gfe_mii_statchg (struct device *); 163 164 STATIC void gfe_tick(void *arg); 165 166 STATIC void gfe_tx_restart(void *); 167 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 168 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 169 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 170 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 171 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 172 173 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 174 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 175 STATIC int gfe_rx_prime(struct gfe_softc *); 176 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 177 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 178 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 179 180 STATIC int gfe_intr(void *); 181 182 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 183 184 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 185 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 186 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 187 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 188 u_long); 189 STATIC int gfe_hash_fill(struct gfe_softc *); 190 STATIC int gfe_hash_alloc(struct gfe_softc *); 191 192 /* Linkup to the rest of the kernel */ 193 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 194 gfe_match, gfe_attach, NULL, NULL); 195 196 extern struct cfdriver gfe_cd; 197 198 int 199 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 200 { 201 struct gt_softc *gt = (struct gt_softc *) parent; 202 struct gt_attach_args *ga = aux; 203 uint8_t enaddr[6]; 204 205 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 206 return 0; 207 208 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 209 return 0; 210 211 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 212 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 213 return 0; 214 215 return 1; 216 } 217 218 /* 219 * Attach this instance, and then all the sub-devices 220 */ 221 void 222 gfe_attach(struct device *parent, struct device *self, void *aux) 223 { 224 struct gt_attach_args * const ga = aux; 225 struct gt_softc * const gt = (struct gt_softc *) parent; 226 struct gfe_softc * const sc = (struct gfe_softc *) self; 227 struct ifnet * const ifp = &sc->sc_ec.ec_if; 228 uint32_t data; 229 uint8_t enaddr[6]; 230 int phyaddr; 231 uint32_t sdcr; 232 233 GT_ETHERFOUND(gt, ga); 234 235 sc->sc_gt_memt = ga->ga_memt; 236 sc->sc_gt_memh = ga->ga_memh; 237 sc->sc_dmat = ga->ga_dmat; 238 sc->sc_macno = ga->ga_unit; 239 240 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 241 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 242 aprint_error(": failed to map registers\n"); 243 } 244 245 callout_init(&sc->sc_co); 246 247 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 248 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 249 250 gtget_macaddr(gt, sc->sc_macno, enaddr); 251 252 sc->sc_pcr = GE_READ(sc, EPCR); 253 sc->sc_pcxr = GE_READ(sc, EPCXR); 254 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 255 256 aprint_normal(": address %s", ether_sprintf(enaddr)); 257 258 #if defined(DEBUG) 259 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 260 #endif 261 262 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 263 if (sc->sc_dev.dv_cfdata->cf_flags & 1) { 264 aprint_normal(", phy %d (rmii)", phyaddr); 265 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 266 } else { 267 aprint_normal(", phy %d (mii)", phyaddr); 268 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 269 } 270 sc->sc_pcxr &= ~(3 << 14); 271 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 272 273 if (sc->sc_pcr & ETH_EPCR_EN) { 274 int tries = 1000; 275 /* 276 * Abort transmitter and receiver and wait for them to quiese 277 */ 278 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 279 do { 280 delay(100); 281 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 282 } 283 284 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 285 286 #if defined(DEBUG) 287 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 288 #endif 289 290 /* 291 * Now turn off the GT. If it didn't quiese, too ***ing bad. 292 */ 293 GE_WRITE(sc, EPCR, sc->sc_pcr); 294 GE_WRITE(sc, EIMR, sc->sc_intrmask); 295 sdcr = GE_READ(sc, ESDCR); 296 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 297 sdcr |= ETH_ESDCR_RIFB; 298 GE_WRITE(sc, ESDCR, sdcr); 299 sc->sc_max_frame_length = 1536; 300 301 aprint_normal("\n"); 302 sc->sc_mii.mii_ifp = ifp; 303 sc->sc_mii.mii_readreg = gfe_mii_read; 304 sc->sc_mii.mii_writereg = gfe_mii_write; 305 sc->sc_mii.mii_statchg = gfe_mii_statchg; 306 307 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 308 gfe_mii_mediastatus); 309 310 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 311 MII_OFFSET_ANY, MIIF_NOISOLATE); 312 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 313 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 314 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 315 } else { 316 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 317 } 318 319 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 320 ifp->if_softc = sc; 321 /* ifp->if_mowner = &sc->sc_mowner; */ 322 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 323 #if 0 324 ifp->if_flags |= IFF_DEBUG; 325 #endif 326 ifp->if_ioctl = gfe_ifioctl; 327 ifp->if_start = gfe_ifstart; 328 ifp->if_watchdog = gfe_ifwatchdog; 329 330 if_attach(ifp); 331 ether_ifattach(ifp, enaddr); 332 #if NBPFILTER > 0 333 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 334 #endif 335 #if NRND > 0 336 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 337 #endif 338 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 339 gfe_intr, sc); 340 } 341 342 int 343 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 344 size_t size, int flags) 345 { 346 int error = 0; 347 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 348 gdm->gdm_size = size; 349 gdm->gdm_maxsegs = maxsegs; 350 351 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 352 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 353 BUS_DMA_NOWAIT); 354 if (error) 355 goto fail; 356 357 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 358 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 359 if (error) 360 goto fail; 361 362 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 363 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 364 if (error) 365 goto fail; 366 367 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 368 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 369 if (error) 370 goto fail; 371 372 /* invalidate from cache */ 373 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 374 BUS_DMASYNC_PREREAD); 375 fail: 376 if (error) { 377 gfe_dmamem_free(sc, gdm); 378 GE_DPRINTF(sc, (":err=%d", error)); 379 } 380 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 381 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 382 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 383 GE_FUNC_EXIT(sc, ""); 384 return error; 385 } 386 387 void 388 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 389 { 390 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 391 if (gdm->gdm_map) 392 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 393 if (gdm->gdm_kva) 394 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 395 if (gdm->gdm_nsegs > 0) 396 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 397 gdm->gdm_map = NULL; 398 gdm->gdm_kva = NULL; 399 gdm->gdm_nsegs = 0; 400 GE_FUNC_EXIT(sc, ""); 401 } 402 403 int 404 gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 405 { 406 struct gfe_softc * const sc = ifp->if_softc; 407 struct ifreq *ifr = (struct ifreq *) data; 408 struct ifaddr *ifa = (struct ifaddr *) data; 409 int s, error = 0; 410 411 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 412 s = splnet(); 413 414 switch (cmd) { 415 case SIOCSIFADDR: 416 ifp->if_flags |= IFF_UP; 417 switch (ifa->ifa_addr->sa_family) { 418 #ifdef INET 419 case AF_INET: 420 error = gfe_whack(sc, GE_WHACK_START); 421 if (error == 0) 422 arp_ifinit(ifp, ifa); 423 break; 424 #endif 425 default: 426 error = gfe_whack(sc, GE_WHACK_START); 427 break; 428 } 429 break; 430 431 case SIOCSIFFLAGS: 432 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 433 case IFF_UP|IFF_RUNNING:/* active->active, update */ 434 error = gfe_whack(sc, GE_WHACK_CHANGE); 435 break; 436 case IFF_RUNNING: /* not up, so we stop */ 437 error = gfe_whack(sc, GE_WHACK_STOP); 438 break; 439 case IFF_UP: /* not running, so we start */ 440 error = gfe_whack(sc, GE_WHACK_START); 441 break; 442 case 0: /* idle->idle: do nothing */ 443 break; 444 } 445 break; 446 447 case SIOCADDMULTI: 448 case SIOCDELMULTI: 449 error = (cmd == SIOCADDMULTI) 450 ? ether_addmulti(ifr, &sc->sc_ec) 451 : ether_delmulti(ifr, &sc->sc_ec); 452 if (error == ENETRESET) { 453 if (ifp->if_flags & IFF_RUNNING) 454 error = gfe_whack(sc, GE_WHACK_CHANGE); 455 else 456 error = 0; 457 } 458 break; 459 460 case SIOCSIFMTU: 461 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 462 error = EINVAL; 463 break; 464 } 465 ifp->if_mtu = ifr->ifr_mtu; 466 break; 467 468 case SIOCSIFMEDIA: 469 case SIOCGIFMEDIA: 470 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 471 break; 472 473 default: 474 error = EINVAL; 475 break; 476 } 477 splx(s); 478 GE_FUNC_EXIT(sc, ""); 479 return error; 480 } 481 482 void 483 gfe_ifstart(struct ifnet *ifp) 484 { 485 struct gfe_softc * const sc = ifp->if_softc; 486 struct mbuf *m; 487 488 GE_FUNC_ENTER(sc, "gfe_ifstart"); 489 490 if ((ifp->if_flags & IFF_RUNNING) == 0) { 491 GE_FUNC_EXIT(sc, "$"); 492 return; 493 } 494 495 if (sc->sc_txq[GE_TXPRIO_HI] == NULL) { 496 ifp->if_flags |= IFF_OACTIVE; 497 #if defined(DEBUG) || defined(DIAGNOSTIC) 498 printf("%s: ifstart: txq not yet created\n", ifp->if_xname); 499 #endif 500 GE_FUNC_EXIT(sc, ""); 501 return; 502 } 503 504 for (;;) { 505 IF_DEQUEUE(&ifp->if_snd, m); 506 if (m == NULL) { 507 ifp->if_flags &= ~IFF_OACTIVE; 508 GE_FUNC_EXIT(sc, ""); 509 return; 510 } 511 512 /* 513 * No space in the pending queue? try later. 514 */ 515 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq)) 516 break; 517 518 /* 519 * Try to enqueue a mbuf to the device. If that fails, we 520 * can always try to map the next mbuf. 521 */ 522 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq, m); 523 GE_DPRINTF(sc, (">")); 524 #ifndef GE_NOTX 525 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 526 #endif 527 } 528 529 /* 530 * Attempt to queue the mbuf for send failed. 531 */ 532 IF_PREPEND(&ifp->if_snd, m); 533 ifp->if_flags |= IFF_OACTIVE; 534 GE_FUNC_EXIT(sc, "%%"); 535 } 536 537 void 538 gfe_ifwatchdog(struct ifnet *ifp) 539 { 540 struct gfe_softc * const sc = ifp->if_softc; 541 struct gfe_txqueue *txq; 542 543 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 544 printf("%s: device timeout", sc->sc_dev.dv_xname); 545 if ((txq = sc->sc_txq[GE_TXPRIO_HI]) != NULL) { 546 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 547 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 548 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 549 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 550 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 551 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 552 GE_READ(sc, EICR)); 553 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 554 GE_TXDPRESYNC(sc, txq, curtxdnum); 555 } 556 printf("\n"); 557 ifp->if_oerrors++; 558 (void) gfe_whack(sc, GE_WHACK_RESTART); 559 GE_FUNC_EXIT(sc, ""); 560 } 561 562 int 564 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 565 { 566 struct gfe_rxqueue *rxq; 567 volatile struct gt_eth_desc *rxd; 568 const bus_dma_segment_t *ds; 569 int error; 570 int idx; 571 bus_addr_t nxtaddr; 572 bus_size_t boff; 573 574 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 575 GE_DPRINTF(sc, ("(%d)", rxprio)); 576 if (sc->sc_rxq[rxprio] != NULL) { 577 GE_FUNC_EXIT(sc, ""); 578 return 0; 579 } 580 581 rxq = (struct gfe_rxqueue *) malloc(sizeof(*rxq), M_DEVBUF, M_NOWAIT); 582 if (rxq == NULL) { 583 GE_FUNC_EXIT(sc, "!"); 584 return ENOMEM; 585 } 586 587 memset(rxq, 0, sizeof(*rxq)); 588 589 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 590 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 591 if (error) { 592 free(rxq, M_DEVBUF); 593 GE_FUNC_EXIT(sc, "!!"); 594 return error; 595 } 596 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 597 GE_RXBUF_MEMSIZE, 0); 598 if (error) { 599 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 600 free(rxq, M_DEVBUF); 601 GE_FUNC_EXIT(sc, "!!!"); 602 return error; 603 } 604 605 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_TXMEM_SIZE); 606 607 sc->sc_rxq[rxprio] = rxq; 608 rxq->rxq_descs = 609 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 610 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 611 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 612 rxq->rxq_fi = 0; 613 rxq->rxq_active = GE_RXDESC_MAX; 614 for (idx = 0, rxd = rxq->rxq_descs, 615 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 616 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 617 idx < GE_RXDESC_MAX; 618 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 619 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 620 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 621 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 622 /* 623 * update the nxtptr to point to the next txd. 624 */ 625 if (idx == GE_RXDESC_MAX - 1) 626 nxtaddr = rxq->rxq_desc_busaddr; 627 rxd->ed_nxtptr = htogt32(nxtaddr); 628 boff += GE_RXBUF_SIZE; 629 if (boff == ds->ds_len) { 630 ds++; 631 boff = 0; 632 } 633 } 634 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 635 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 636 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 637 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 638 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 639 BUS_DMASYNC_PREREAD); 640 641 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 642 switch (rxprio) { 643 case GE_RXPRIO_HI: 644 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 645 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 646 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 647 break; 648 case GE_RXPRIO_MEDHI: 649 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 650 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 651 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 652 break; 653 case GE_RXPRIO_MEDLO: 654 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 655 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 656 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 657 break; 658 case GE_RXPRIO_LO: 659 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 660 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 661 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 662 break; 663 } 664 GE_FUNC_EXIT(sc, ""); 665 return error; 666 } 667 668 void 669 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 670 { 671 struct ifnet * const ifp = &sc->sc_ec.ec_if; 672 struct gfe_rxqueue * const rxq = sc->sc_rxq[rxprio]; 673 struct mbuf *m = rxq->rxq_curpkt; 674 675 GE_FUNC_ENTER(sc, "gfe_rx_get"); 676 GE_DPRINTF(sc, ("(%d)", rxprio)); 677 678 while (rxq->rxq_active > 0) { 679 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 680 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 681 const struct ether_header *eh; 682 unsigned int cmdsts; 683 size_t buflen; 684 685 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 686 cmdsts = gt32toh(rxd->ed_cmdsts); 687 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 688 rxq->rxq_cmdsts = cmdsts; 689 /* 690 * Sometimes the GE "forgets" to reset the ownership bit. 691 * But if the length has been rewritten, the packet is ours 692 * so pretend the O bit is set. 693 */ 694 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 695 if ((cmdsts & RX_CMD_O) && buflen == 0) { 696 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 697 break; 698 } 699 700 /* 701 * If this is not a single buffer packet with no errors 702 * or for some reason it's bigger than our frame size, 703 * ignore it and go to the next packet. 704 */ 705 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 706 (RX_CMD_F|RX_CMD_L) || 707 buflen > sc->sc_max_frame_length) { 708 GE_DPRINTF(sc, ("!")); 709 --rxq->rxq_active; 710 ifp->if_ipackets++; 711 ifp->if_ierrors++; 712 goto give_it_back; 713 } 714 715 /* CRC is included with the packet; trim it off. */ 716 buflen -= ETHER_CRC_LEN; 717 718 if (m == NULL) { 719 MGETHDR(m, M_DONTWAIT, MT_DATA); 720 if (m == NULL) { 721 GE_DPRINTF(sc, ("?")); 722 break; 723 } 724 } 725 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 726 MCLGET(m, M_DONTWAIT); 727 if ((m->m_flags & M_EXT) == 0) { 728 GE_DPRINTF(sc, ("?")); 729 break; 730 } 731 } 732 m->m_data += 2; 733 m->m_len = 0; 734 m->m_pkthdr.len = 0; 735 m->m_pkthdr.rcvif = ifp; 736 rxq->rxq_cmdsts = cmdsts; 737 --rxq->rxq_active; 738 739 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 740 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 741 742 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 743 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 744 m->m_len = buflen; 745 m->m_pkthdr.len = buflen; 746 747 ifp->if_ipackets++; 748 #if NBPFILTER > 0 749 if (ifp->if_bpf != NULL) 750 bpf_mtap(ifp->if_bpf, m); 751 #endif 752 753 eh = (const struct ether_header *) m->m_data; 754 if ((ifp->if_flags & IFF_PROMISC) || 755 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 756 (rxq->rxq_cmdsts & RX_STS_HE) || 757 (eh->ether_dhost[0] & 1) != 0 || 758 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 759 ETHER_ADDR_LEN) == 0) { 760 (*ifp->if_input)(ifp, m); 761 m = NULL; 762 GE_DPRINTF(sc, (">")); 763 } else { 764 m->m_len = 0; 765 m->m_pkthdr.len = 0; 766 GE_DPRINTF(sc, ("+")); 767 } 768 rxq->rxq_cmdsts = 0; 769 770 give_it_back: 771 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 772 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 773 #if 0 774 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 775 rxq->rxq_fi, 776 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 777 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 778 #endif 779 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 780 if (++rxq->rxq_fi == GE_RXDESC_MAX) 781 rxq->rxq_fi = 0; 782 rxq->rxq_active++; 783 } 784 rxq->rxq_curpkt = m; 785 GE_FUNC_EXIT(sc, ""); 786 } 787 788 uint32_t 789 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 790 { 791 struct ifnet * const ifp = &sc->sc_ec.ec_if; 792 struct gfe_rxqueue *rxq; 793 uint32_t rxbits; 794 #define RXPRIO_DECODER 0xffffaa50 795 GE_FUNC_ENTER(sc, "gfe_rx_process"); 796 797 rxbits = ETH_IR_RxBuffer_GET(cause); 798 while (rxbits) { 799 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 800 GE_DPRINTF(sc, ("%1x", rxbits)); 801 rxbits &= ~(1 << rxprio); 802 gfe_rx_get(sc, rxprio); 803 } 804 805 rxbits = ETH_IR_RxError_GET(cause); 806 while (rxbits) { 807 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 808 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 809 int idx; 810 rxbits &= ~(1 << rxprio); 811 rxq = sc->sc_rxq[rxprio]; 812 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 813 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 814 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 815 sc->sc_tickflags |= GE_TICK_RX_RESTART; 816 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 817 } 818 ifp->if_ierrors++; 819 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 820 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 821 memset(masks, 0, sizeof(masks)); 822 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 823 0, rxq->rxq_desc_mem.gdm_size, 824 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 825 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 826 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 827 828 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 829 masks[idx/32] |= 1 << (idx & 31); 830 } 831 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 832 0, rxq->rxq_desc_mem.gdm_size, 833 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 834 #if defined(DEBUG) 835 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 836 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 837 rxq->rxq_cmdsts, masks[0], masks[1]); 838 #endif 839 } 840 if ((intrmask & ETH_IR_RxBits) == 0) 841 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 842 843 GE_FUNC_EXIT(sc, ""); 844 return intrmask; 845 } 846 847 int 848 gfe_rx_prime(struct gfe_softc *sc) 849 { 850 struct gfe_rxqueue *rxq; 851 int error; 852 853 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 854 855 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 856 if (error) 857 goto bail; 858 rxq = sc->sc_rxq[GE_RXPRIO_HI]; 859 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 860 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 861 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 862 } 863 sc->sc_intrmask |= rxq->rxq_intrbits; 864 865 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 866 if (error) 867 goto bail; 868 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 869 rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 870 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 871 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 872 sc->sc_intrmask |= rxq->rxq_intrbits; 873 } 874 875 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 876 if (error) 877 goto bail; 878 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 879 rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 880 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 881 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 882 sc->sc_intrmask |= rxq->rxq_intrbits; 883 } 884 885 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 886 if (error) 887 goto bail; 888 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 889 rxq = sc->sc_rxq[GE_RXPRIO_LO]; 890 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 891 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 892 sc->sc_intrmask |= rxq->rxq_intrbits; 893 } 894 895 bail: 896 GE_FUNC_EXIT(sc, ""); 897 return error; 898 } 899 900 void 901 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 902 { 903 struct gfe_rxqueue *rxq = sc->sc_rxq[rxprio]; 904 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 905 if (rxq == NULL) { 906 GE_FUNC_EXIT(sc, ""); 907 return; 908 } 909 910 if (rxq->rxq_curpkt) 911 m_freem(rxq->rxq_curpkt); 912 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 913 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 914 free(rxq, M_DEVBUF); 915 sc->sc_rxq[rxprio] = NULL; 916 GE_FUNC_EXIT(sc, ""); 917 } 918 919 void 920 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 921 { 922 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 923 sc->sc_flags &= ~GE_RXACTIVE; 924 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 925 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 926 GE_WRITE(sc, EIMR, sc->sc_intrmask); 927 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 928 do { 929 delay(10); 930 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 931 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 932 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 933 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 934 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 935 GE_FUNC_EXIT(sc, ""); 936 } 937 938 void 940 gfe_tick(void *arg) 941 { 942 struct gfe_softc * const sc = arg; 943 uint32_t intrmask; 944 unsigned int tickflags; 945 int s; 946 947 GE_FUNC_ENTER(sc, "gfe_tick"); 948 949 s = splnet(); 950 951 tickflags = sc->sc_tickflags; 952 sc->sc_tickflags = 0; 953 intrmask = sc->sc_intrmask; 954 if (tickflags & GE_TICK_TX_IFSTART) 955 gfe_ifstart(&sc->sc_ec.ec_if); 956 if (tickflags & GE_TICK_RX_RESTART) { 957 intrmask |= sc->sc_idlemask; 958 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 959 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_HI]; 960 rxq->rxq_fi = 0; 961 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 962 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 963 } 964 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 965 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 966 rxq->rxq_fi = 0; 967 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 968 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 969 } 970 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 971 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 972 rxq->rxq_fi = 0; 973 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 974 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 975 } 976 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 977 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_LO]; 978 rxq->rxq_fi = 0; 979 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 980 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 981 } 982 sc->sc_idlemask = 0; 983 } 984 if (intrmask != sc->sc_intrmask) { 985 sc->sc_intrmask = intrmask; 986 GE_WRITE(sc, EIMR, sc->sc_intrmask); 987 } 988 gfe_intr(sc); 989 splx(s); 990 991 GE_FUNC_EXIT(sc, ""); 992 } 993 994 int 995 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 996 { 997 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 998 struct ifnet * const ifp = &sc->sc_ec.ec_if; 999 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1000 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1001 uint32_t intrmask = sc->sc_intrmask; 1002 size_t buflen; 1003 struct mbuf *m; 1004 1005 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1006 1007 /* 1008 * Anything in the pending queue to enqueue? if not, punt. Likewise 1009 * if the txq is not yet created. 1010 * otherwise grab its dmamap. 1011 */ 1012 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1013 GE_FUNC_EXIT(sc, "-"); 1014 return 0; 1015 } 1016 1017 /* 1018 * Have we [over]consumed our limit of descriptors? 1019 * Do we have enough free descriptors? 1020 */ 1021 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1022 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1023 uint32_t cmdsts; 1024 size_t pktlen; 1025 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1026 cmdsts = gt32toh(txd2->ed_cmdsts); 1027 if (cmdsts & TX_CMD_O) { 1028 int nextin; 1029 /* 1030 * Sometime the Discovery forgets to update the 1031 * last descriptor. See if we own the descriptor 1032 * after it (since we know we've turned that to 1033 * the discovery and if we owned it, the Discovery 1034 * gave it back). If we do, we know the Discovery 1035 * gave back this one but forgot to mark it as ours. 1036 */ 1037 nextin = txq->txq_fi + 1; 1038 if (nextin == GE_TXDESC_MAX) 1039 nextin = 0; 1040 GE_TXDPOSTSYNC(sc, txq, nextin); 1041 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1042 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1043 GE_TXDPRESYNC(sc, txq, nextin); 1044 GE_FUNC_EXIT(sc, "@"); 1045 return 0; 1046 } 1047 #ifdef DEBUG 1048 printf("%s: txenqueue: transmitter resynced at %d\n", 1049 sc->sc_dev.dv_xname, txq->txq_fi); 1050 #endif 1051 } 1052 if (++txq->txq_fi == GE_TXDESC_MAX) 1053 txq->txq_fi = 0; 1054 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1055 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1056 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1057 txq->txq_nactive--; 1058 1059 /* statistics */ 1060 ifp->if_opackets++; 1061 if (cmdsts & TX_STS_ES) 1062 ifp->if_oerrors++; 1063 GE_DPRINTF(sc, ("%%")); 1064 } 1065 1066 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1067 1068 /* 1069 * If this packet would wrap around the end of the buffer, reset back 1070 * to the beginning. 1071 */ 1072 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1073 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1074 txq->txq_outptr = 0; 1075 } 1076 1077 /* 1078 * Make sure the output packet doesn't run over the beginning of 1079 * what we've already given the GT. 1080 */ 1081 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1082 txq->txq_outptr + buflen > txq->txq_inptr) { 1083 intrmask |= txq->txq_intrbits & 1084 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1085 if (sc->sc_intrmask != intrmask) { 1086 sc->sc_intrmask = intrmask; 1087 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1088 } 1089 GE_FUNC_EXIT(sc, "#"); 1090 return 0; 1091 } 1092 1093 /* 1094 * The end-of-list descriptor we put on last time is the starting point 1095 * for this packet. The GT is supposed to terminate list processing on 1096 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1097 * must terminate the list. 1098 */ 1099 intrmask = sc->sc_intrmask; 1100 1101 m_copydata(m, 0, m->m_pkthdr.len, 1102 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1103 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1104 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1105 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1106 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1107 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1108 1109 /* 1110 * Request a buffer interrupt every 2/3 of the way thru the transmit 1111 * buffer. 1112 */ 1113 txq->txq_ei_gapcount += buflen; 1114 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1115 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1116 txq->txq_ei_gapcount = 0; 1117 } else { 1118 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1119 } 1120 #if 0 1121 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1122 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1123 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1124 #endif 1125 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1126 1127 txq->txq_outptr += buflen; 1128 /* 1129 * Tell the SDMA engine to "Fetch!" 1130 */ 1131 GE_WRITE(sc, ESDCMR, 1132 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1133 1134 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1135 1136 /* 1137 * Update the last out appropriately. 1138 */ 1139 txq->txq_nactive++; 1140 if (++txq->txq_lo == GE_TXDESC_MAX) 1141 txq->txq_lo = 0; 1142 1143 /* 1144 * Move mbuf from the pending queue to the snd queue. 1145 */ 1146 IF_DEQUEUE(&txq->txq_pendq, m); 1147 #if NBPFILTER > 0 1148 if (ifp->if_bpf != NULL) 1149 bpf_mtap(ifp->if_bpf, m); 1150 #endif 1151 m_freem(m); 1152 ifp->if_flags &= ~IFF_OACTIVE; 1153 1154 /* 1155 * Since we have put an item into the packet queue, we now want 1156 * an interrupt when the transmit queue finishes processing the 1157 * list. But only update the mask if needs changing. 1158 */ 1159 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1160 if (sc->sc_intrmask != intrmask) { 1161 sc->sc_intrmask = intrmask; 1162 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1163 } 1164 if (ifp->if_timer == 0) 1165 ifp->if_timer = 5; 1166 GE_FUNC_EXIT(sc, "*"); 1167 return 1; 1168 } 1169 1170 uint32_t 1171 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1172 { 1173 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1174 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1175 1176 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1177 1178 if (txq == NULL) { 1179 GE_FUNC_EXIT(sc, ""); 1180 return intrmask; 1181 } 1182 1183 while (txq->txq_nactive > 0) { 1184 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1185 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1186 uint32_t cmdsts; 1187 size_t pktlen; 1188 1189 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1190 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1191 int nextin; 1192 1193 if (txq->txq_nactive == 1) { 1194 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1195 GE_FUNC_EXIT(sc, ""); 1196 return intrmask; 1197 } 1198 /* 1199 * Sometimes the Discovery forgets to update the 1200 * ownership bit in the descriptor. See if we own the 1201 * descriptor after it (since we know we've turned 1202 * that to the Discovery and if we own it now then the 1203 * Discovery gave it back). If we do, we know the 1204 * Discovery gave back this one but forgot to mark it 1205 * as ours. 1206 */ 1207 nextin = txq->txq_fi + 1; 1208 if (nextin == GE_TXDESC_MAX) 1209 nextin = 0; 1210 GE_TXDPOSTSYNC(sc, txq, nextin); 1211 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1212 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1213 GE_TXDPRESYNC(sc, txq, nextin); 1214 GE_FUNC_EXIT(sc, ""); 1215 return intrmask; 1216 } 1217 #ifdef DEBUG 1218 printf("%s: txdone: transmitter resynced at %d\n", 1219 sc->sc_dev.dv_xname, txq->txq_fi); 1220 #endif 1221 } 1222 #if 0 1223 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1224 txq->txq_lo, 1225 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1226 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1227 #endif 1228 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1229 if (++txq->txq_fi == GE_TXDESC_MAX) 1230 txq->txq_fi = 0; 1231 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1232 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1233 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1234 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1235 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1236 1237 /* statistics */ 1238 ifp->if_opackets++; 1239 if (cmdsts & TX_STS_ES) 1240 ifp->if_oerrors++; 1241 1242 /* txd->ed_bufptr = 0; */ 1243 1244 ifp->if_timer = 5; 1245 --txq->txq_nactive; 1246 } 1247 if (txq->txq_nactive != 0) 1248 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1249 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1250 ifp->if_timer = 0; 1251 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1252 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1253 GE_FUNC_EXIT(sc, ""); 1254 return intrmask; 1255 } 1256 1257 int 1258 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1259 { 1260 struct gfe_txqueue *txq; 1261 volatile struct gt_eth_desc *txd; 1262 unsigned int i; 1263 bus_addr_t addr; 1264 1265 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1266 1267 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1268 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1269 1270 if ((txq = sc->sc_txq[txprio]) == NULL) { 1271 int error; 1272 txq = (struct gfe_txqueue *) malloc(sizeof(*txq), 1273 M_DEVBUF, M_NOWAIT); 1274 if (txq == NULL) { 1275 GE_FUNC_EXIT(sc, ""); 1276 return ENOMEM; 1277 } 1278 memset(txq, 0, sizeof(*txq)); 1279 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1280 GE_TXMEM_SIZE, BUS_DMA_NOCACHE); 1281 if (error) { 1282 free(txq, M_DEVBUF); 1283 GE_FUNC_EXIT(sc, ""); 1284 return error; 1285 } 1286 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, 1287 GE_TXBUF_SIZE, 0); 1288 if (error) { 1289 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1290 free(txq, M_DEVBUF); 1291 GE_FUNC_EXIT(sc, ""); 1292 return error; 1293 } 1294 sc->sc_txq[txprio] = txq; 1295 } 1296 1297 txq->txq_descs = 1298 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1299 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1300 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1301 1302 txq->txq_pendq.ifq_maxlen = 10; 1303 txq->txq_ei_gapcount = 0; 1304 txq->txq_nactive = 0; 1305 txq->txq_fi = 0; 1306 txq->txq_lo = 0; 1307 txq->txq_inptr = GE_TXBUF_SIZE; 1308 txq->txq_outptr = 0; 1309 for (i = 0, txd = txq->txq_descs, 1310 addr = txq->txq_desc_busaddr + sizeof(*txd); 1311 i < GE_TXDESC_MAX - 1; 1312 i++, txd++, addr += sizeof(*txd)) { 1313 /* 1314 * update the nxtptr to point to the next txd. 1315 */ 1316 txd->ed_cmdsts = 0; 1317 txd->ed_nxtptr = htogt32(addr); 1318 } 1319 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1320 htogt32(txq->txq_desc_busaddr); 1321 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1322 GE_TXMEM_SIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1323 1324 switch (txprio) { 1325 case GE_TXPRIO_HI: 1326 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1327 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1328 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1329 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1330 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1331 break; 1332 1333 case GE_TXPRIO_LO: 1334 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1335 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1336 txq->txq_epsrbits = ETH_EPSR_TxLow; 1337 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1338 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1339 break; 1340 1341 case GE_TXPRIO_NONE: 1342 break; 1343 } 1344 #if 0 1345 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1346 gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); 1347 GE_DPRINTF(sc, (")")); 1348 #endif 1349 1350 /* 1351 * If we are restarting, there may be packets in the pending queue 1352 * waiting to be enqueued. Try enqueuing packets from both priority 1353 * queues until the pending queue is empty or there no room for them 1354 * on the device. 1355 */ 1356 while (gfe_tx_enqueue(sc, txprio)) 1357 continue; 1358 1359 GE_FUNC_EXIT(sc, ""); 1360 return 0; 1361 } 1362 1363 void 1364 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1365 { 1366 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1367 1368 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1369 if (txq == NULL) { 1370 GE_FUNC_EXIT(sc, ""); 1371 return; 1372 } 1373 1374 if (!flush) { 1375 GE_FUNC_EXIT(sc, ""); 1376 return; 1377 } 1378 1379 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1380 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1381 free(txq, M_DEVBUF); 1382 sc->sc_txq[txprio] = NULL; 1383 GE_FUNC_EXIT(sc, "-F"); 1384 } 1385 1386 void 1387 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1388 { 1389 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1390 1391 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1392 1393 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1394 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1395 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1396 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1397 1398 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1399 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1400 1401 sc->sc_ec.ec_if.if_timer = 0; 1402 GE_FUNC_EXIT(sc, ""); 1403 } 1404 1405 int 1407 gfe_intr(void *arg) 1408 { 1409 struct gfe_softc * const sc = arg; 1410 uint32_t cause; 1411 uint32_t intrmask = sc->sc_intrmask; 1412 int claim = 0; 1413 int cnt; 1414 1415 GE_FUNC_ENTER(sc, "gfe_intr"); 1416 1417 for (cnt = 0; cnt < 4; cnt++) { 1418 if (sc->sc_intrmask != intrmask) { 1419 sc->sc_intrmask = intrmask; 1420 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1421 } 1422 cause = GE_READ(sc, EICR); 1423 cause &= sc->sc_intrmask; 1424 GE_DPRINTF(sc, (".%#x", cause)); 1425 if (cause == 0) 1426 break; 1427 1428 claim = 1; 1429 1430 GE_WRITE(sc, EICR, ~cause); 1431 #ifndef GE_NORX 1432 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1433 intrmask = gfe_rx_process(sc, cause, intrmask); 1434 #endif 1435 1436 #ifndef GE_NOTX 1437 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1438 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1439 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1440 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1441 #endif 1442 if (cause & ETH_IR_MIIPhySTC) { 1443 sc->sc_flags |= GE_PHYSTSCHG; 1444 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1445 } 1446 } 1447 1448 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1449 continue; 1450 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1451 continue; 1452 1453 GE_FUNC_EXIT(sc, ""); 1454 return claim; 1455 } 1456 1457 int 1459 gfe_mii_mediachange (struct ifnet *ifp) 1460 { 1461 struct gfe_softc *sc = ifp->if_softc; 1462 1463 if (ifp->if_flags & IFF_UP) 1464 mii_mediachg(&sc->sc_mii); 1465 1466 return (0); 1467 } 1468 void 1469 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1470 { 1471 struct gfe_softc *sc = ifp->if_softc; 1472 1473 if (sc->sc_flags & GE_PHYSTSCHG) { 1474 sc->sc_flags &= ~GE_PHYSTSCHG; 1475 mii_pollstat(&sc->sc_mii); 1476 } 1477 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1478 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1479 } 1480 1481 int 1482 gfe_mii_read (struct device *self, int phy, int reg) 1483 { 1484 return gt_mii_read(self, self->dv_parent, phy, reg); 1485 } 1486 1487 void 1488 gfe_mii_write (struct device *self, int phy, int reg, int value) 1489 { 1490 gt_mii_write(self, self->dv_parent, phy, reg, value); 1491 } 1492 1493 void 1494 gfe_mii_statchg (struct device *self) 1495 { 1496 /* struct gfe_softc *sc = (struct gfe_softc *) self; */ 1497 /* do nothing? */ 1498 } 1499 1500 int 1502 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1503 { 1504 int error = 0; 1505 GE_FUNC_ENTER(sc, "gfe_whack"); 1506 1507 switch (op) { 1508 case GE_WHACK_RESTART: 1509 #ifndef GE_NOTX 1510 gfe_tx_stop(sc, op); 1511 #endif 1512 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1513 /* FALLTHROUGH */ 1514 case GE_WHACK_START: 1515 #ifndef GE_NOHASH 1516 if (error == 0 && sc->sc_hashtable == NULL) { 1517 error = gfe_hash_alloc(sc); 1518 if (error) 1519 break; 1520 } 1521 if (op != GE_WHACK_RESTART) 1522 gfe_hash_fill(sc); 1523 #endif 1524 #ifndef GE_NORX 1525 if (op != GE_WHACK_RESTART) { 1526 error = gfe_rx_prime(sc); 1527 if (error) 1528 break; 1529 } 1530 #endif 1531 #ifndef GE_NOTX 1532 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1533 if (error) 1534 break; 1535 #endif 1536 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1537 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1538 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1539 GE_WRITE(sc, EICR, 0); 1540 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1541 #ifndef GE_NOHASH 1542 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1543 #endif 1544 #ifndef GE_NORX 1545 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1546 sc->sc_flags |= GE_RXACTIVE; 1547 #endif 1548 /* FALLTHROUGH */ 1549 case GE_WHACK_CHANGE: 1550 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1551 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1552 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1553 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1554 gfe_ifstart(&sc->sc_ec.ec_if); 1555 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1556 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1557 GE_FUNC_EXIT(sc, ""); 1558 return error; 1559 case GE_WHACK_STOP: 1560 break; 1561 } 1562 1563 #ifdef GE_DEBUG 1564 if (error) 1565 GE_DPRINTF(sc, (" failed: %d\n", error)); 1566 #endif 1567 GE_WRITE(sc, EPCR, sc->sc_pcr); 1568 GE_WRITE(sc, EIMR, 0); 1569 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1570 #ifndef GE_NOTX 1571 gfe_tx_stop(sc, GE_WHACK_STOP); 1572 #endif 1573 #ifndef GE_NORX 1574 gfe_rx_stop(sc, GE_WHACK_STOP); 1575 #endif 1576 #ifndef GE_NOHASH 1577 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1578 sc->sc_hashtable = NULL; 1579 #endif 1580 1581 GE_FUNC_EXIT(sc, ""); 1582 return error; 1583 } 1584 1585 int 1587 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1588 { 1589 uint32_t w0, add0, add1; 1590 uint32_t result; 1591 1592 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1593 add0 = ((uint32_t) eaddr[5] << 0) | 1594 ((uint32_t) eaddr[4] << 8) | 1595 ((uint32_t) eaddr[3] << 16); 1596 1597 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1598 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1599 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1600 1601 add1 = ((uint32_t) eaddr[2] << 0) | 1602 ((uint32_t) eaddr[1] << 8) | 1603 ((uint32_t) eaddr[0] << 16); 1604 1605 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1606 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1607 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1608 1609 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1610 /* 1611 * hashResult is the 15 bits Hash entry address. 1612 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1613 * MAC address, by nibble swapping in every byte (i.e MAC address 1614 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1615 */ 1616 1617 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1618 /* 1619 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1620 * 1621 * hashFunc0 calculates the hashResult in the following manner: 1622 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1623 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1624 */ 1625 result = (add0 & 3) | ((add0 >> 6) & ~3); 1626 result ^= (add0 >> 15) ^ (add1 >> 0); 1627 result &= 0x1ff; 1628 /* 1629 * hashResult[14:9] = ethernetADD[7:2] 1630 */ 1631 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1632 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1633 } else { 1634 #define TRIBITFLIP 073516240 /* yes its in octal */ 1635 /* 1636 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1637 * 1638 * hashFunc1 calculates the hashResult in the following manner: 1639 * hashResult[08:00] = ethernetADD[06:14] 1640 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1641 */ 1642 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1643 /* 1644 * Now bitswap those 9 bits 1645 */ 1646 result = 0; 1647 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1648 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1649 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1650 1651 /* 1652 * hashResult[14:09] = ethernetADD[00:05] 1653 */ 1654 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1655 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1656 GE_DPRINTF(sc, ("1(%#x)", result)); 1657 } 1658 GE_FUNC_EXIT(sc, ""); 1659 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1660 } 1661 1662 int 1663 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1664 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1665 { 1666 uint64_t he; 1667 uint64_t *maybe_he_p = NULL; 1668 int limit; 1669 int hash; 1670 int maybe_hash = 0; 1671 1672 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1673 1674 hash = gfe_hash_compute(sc, eaddr); 1675 1676 if (sc->sc_hashtable == NULL) { 1677 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1678 __LINE__); 1679 } 1680 1681 /* 1682 * Assume we are going to insert so create the hash entry we 1683 * are going to insert. We also use it to match entries we 1684 * will be removing. 1685 */ 1686 he = ((uint64_t) eaddr[5] << 43) | 1687 ((uint64_t) eaddr[4] << 35) | 1688 ((uint64_t) eaddr[3] << 27) | 1689 ((uint64_t) eaddr[2] << 19) | 1690 ((uint64_t) eaddr[1] << 11) | 1691 ((uint64_t) eaddr[0] << 3) | 1692 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1693 1694 /* 1695 * The GT will search upto 12 entries for a hit, so we must mimic that. 1696 */ 1697 hash &= sc->sc_hashmask / sizeof(he); 1698 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1699 /* 1700 * Does the GT wrap at the end, stop at the, or overrun the 1701 * end? Assume it wraps for now. Stash a copy of the 1702 * current hash entry. 1703 */ 1704 uint64_t *he_p = &sc->sc_hashtable[hash]; 1705 uint64_t thishe = *he_p; 1706 1707 /* 1708 * If the hash entry isn't valid, that break the chain. And 1709 * this entry a good candidate for reuse. 1710 */ 1711 if ((thishe & HSH_V) == 0) { 1712 maybe_he_p = he_p; 1713 break; 1714 } 1715 1716 /* 1717 * If the hash entry has the same address we are looking for 1718 * then ... if we are removing and the skip bit is set, its 1719 * already been removed. if are adding and the skip bit is 1720 * clear, then its already added. In either return EBUSY 1721 * indicating the op has already been done. Otherwise flip 1722 * the skip bit and return 0. 1723 */ 1724 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1725 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1726 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1727 return EBUSY; 1728 *he_p = thishe ^ HSH_S; 1729 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1730 hash * sizeof(he), sizeof(he), 1731 BUS_DMASYNC_PREWRITE); 1732 GE_FUNC_EXIT(sc, "^"); 1733 return 0; 1734 } 1735 1736 /* 1737 * If we haven't found a slot for the entry and this entry 1738 * is currently being skipped, return this entry. 1739 */ 1740 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1741 maybe_he_p = he_p; 1742 maybe_hash = hash; 1743 } 1744 1745 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1746 } 1747 1748 /* 1749 * If we got here, then there was no entry to remove. 1750 */ 1751 if (op == GE_HASH_REMOVE) { 1752 GE_FUNC_EXIT(sc, "?"); 1753 return ENOENT; 1754 } 1755 1756 /* 1757 * If we couldn't find a slot, return an error. 1758 */ 1759 if (maybe_he_p == NULL) { 1760 GE_FUNC_EXIT(sc, "!"); 1761 return ENOSPC; 1762 } 1763 1764 /* Update the entry. 1765 */ 1766 *maybe_he_p = he; 1767 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1768 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1769 GE_FUNC_EXIT(sc, "+"); 1770 return 0; 1771 } 1772 1773 int 1774 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1775 { 1776 struct gfe_softc * const sc = ec->ec_if.if_softc; 1777 int error; 1778 enum gfe_hash_op op; 1779 enum gfe_rxprio prio; 1780 1781 GE_FUNC_ENTER(sc, "hash_multichg"); 1782 /* 1783 * Is this a wildcard entry? If so and its being removed, recompute. 1784 */ 1785 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1786 if (cmd == SIOCDELMULTI) { 1787 GE_FUNC_EXIT(sc, ""); 1788 return ENETRESET; 1789 } 1790 1791 /* 1792 * Switch in 1793 */ 1794 sc->sc_flags |= GE_ALLMULTI; 1795 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1796 sc->sc_pcr |= ETH_EPCR_PM; 1797 GE_WRITE(sc, EPCR, sc->sc_pcr); 1798 GE_FUNC_EXIT(sc, ""); 1799 return 0; 1800 } 1801 GE_FUNC_EXIT(sc, ""); 1802 return ENETRESET; 1803 } 1804 1805 prio = GE_RXPRIO_MEDLO; 1806 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1807 1808 if (sc->sc_hashtable == NULL) { 1809 GE_FUNC_EXIT(sc, ""); 1810 return 0; 1811 } 1812 1813 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1814 if (error == EBUSY) { 1815 printf("%s: multichg: tried to %s %s again\n", 1816 sc->sc_dev.dv_xname, 1817 cmd == SIOCDELMULTI ? "remove" : "add", 1818 ether_sprintf(enm->enm_addrlo)); 1819 GE_FUNC_EXIT(sc, ""); 1820 return 0; 1821 } 1822 1823 if (error == ENOENT) { 1824 printf("%s: multichg: failed to remove %s: not in table\n", 1825 sc->sc_dev.dv_xname, 1826 ether_sprintf(enm->enm_addrlo)); 1827 GE_FUNC_EXIT(sc, ""); 1828 return 0; 1829 } 1830 1831 if (error == ENOSPC) { 1832 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1833 sc->sc_dev.dv_xname, 1834 ether_sprintf(enm->enm_addrlo)); 1835 GE_FUNC_EXIT(sc, ""); 1836 return ENETRESET; 1837 } 1838 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1839 sc->sc_dev.dv_xname, 1840 cmd == SIOCDELMULTI ? "remove" : "add", 1841 ether_sprintf(enm->enm_addrlo))); 1842 GE_FUNC_EXIT(sc, ""); 1843 return 0; 1844 } 1845 1846 int 1847 gfe_hash_fill(struct gfe_softc *sc) 1848 { 1849 struct ether_multistep step; 1850 struct ether_multi *enm; 1851 int error; 1852 1853 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1854 1855 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1856 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1857 if (error) 1858 GE_FUNC_EXIT(sc, "!"); 1859 return error; 1860 1861 sc->sc_flags &= ~GE_ALLMULTI; 1862 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1863 sc->sc_pcr &= ~ETH_EPCR_PM; 1864 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1865 while (enm != NULL) { 1866 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1867 sc->sc_flags |= GE_ALLMULTI; 1868 sc->sc_pcr |= ETH_EPCR_PM; 1869 } else { 1870 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1871 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1872 if (error == ENOSPC) 1873 break; 1874 } 1875 ETHER_NEXT_MULTI(step, enm); 1876 } 1877 1878 GE_FUNC_EXIT(sc, ""); 1879 return error; 1880 } 1881 1882 int 1883 gfe_hash_alloc(struct gfe_softc *sc) 1884 { 1885 int error; 1886 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1887 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1888 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1889 BUS_DMA_NOCACHE); 1890 if (error) { 1891 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1892 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1893 GE_FUNC_EXIT(sc, ""); 1894 return error; 1895 } 1896 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1897 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1898 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1899 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1900 GE_FUNC_EXIT(sc, ""); 1901 return 0; 1902 } 1903
Indexes created Tue Sep 30 11:09:46 GMT 2025