if_gfe.c revision 1.2
1 /* $NetBSD: if_gfe.c,v 1.2 2003/03/16 07:05:34 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #define PKT_DUMP 0 45 46 #include "opt_inet.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/types.h> 51 #include <sys/inttypes.h> 52 #include <sys/queue.h> 53 54 #include <sys/callout.h> 55 #include <sys/device.h> 56 #include <sys/errno.h> 57 #include <sys/ioctl.h> 58 #include <sys/mbuf.h> 59 #include <sys/socket.h> 60 61 #include <machine/bus.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <dev/mii/miivar.h> 77 78 #include <dev/marvell/gtintrreg.h> 79 #include <dev/marvell/gtethreg.h> 80 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/if_gfevar.h> 83 84 #define GE_READ(sc, reg) \ 85 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_gt_memh, \ 86 ETH_ ## reg ((sc)->sc_macno)) 87 #define GE_WRITE(sc, reg, v) \ 88 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_gt_memh, \ 89 ETH_ ## reg ((sc)->sc_macno), (v)) 90 91 #define GE_DEBUG 92 #if 0 93 #define GE_NOHASH 94 #define GE_NORX 95 #endif 96 97 #ifdef GE_DEBUG 98 #define GE_DPRINTF(sc, a) do \ 99 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 100 printf a; \ 101 while (0) 102 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 103 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 104 #else 105 #define GE_DPRINTF(sc, a) do { } while (0) 106 #define GE_FUNC_ENTER(sc, func) do { } while (0) 107 #define GE_FUNC_EXIT(sc, str) do { } while (0) 108 #endif 109 enum gfe_whack_op { 110 GE_WHACK_START, GE_WHACK_RESTART, 111 GE_WHACK_CHANGE, GE_WHACK_STOP 112 }; 113 114 enum gfe_hash_op { 115 GE_HASH_ADD, GE_HASH_REMOVE, 116 }; 117 118 #if 1 119 #define htogt32(a) htobe32(a) 120 #define gt32toh(a) be32toh(a) 121 #else 122 #define htogt32(a) htole32(a) 123 #define gt32toh(a) le32toh(a) 124 #endif 125 126 #define STATIC 127 128 STATIC int gfe_match (struct device *, struct cfdata *, void *); 129 STATIC void gfe_attach (struct device *, struct device *, void *); 130 131 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 132 size_t, int); 133 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 134 135 STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); 136 STATIC void gfe_ifstart (struct ifnet *); 137 STATIC void gfe_ifwatchdog (struct ifnet *); 138 139 STATIC int gfe_mii_mediachange (struct ifnet *); 140 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 141 STATIC int gfe_mii_read (struct device *, int, int); 142 STATIC void gfe_mii_write (struct device *, int, int, int); 143 STATIC void gfe_mii_statchg (struct device *); 144 145 STATIC void gfe_tick(void *arg); 146 147 STATIC void gfe_tx_restart(void *); 148 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 149 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 150 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 151 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 152 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 153 154 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 155 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 156 STATIC int gfe_rx_prime(struct gfe_softc *); 157 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 158 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 159 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 160 161 STATIC int gfe_intr(void *); 162 163 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 164 165 STATIC int gfe_hash_compute(struct gfe_softc *, const u_int8_t [ETHER_ADDR_LEN]); 166 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 167 enum gfe_rxprio, const u_int8_t [ETHER_ADDR_LEN]); 168 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 169 u_long); 170 STATIC int gfe_hash_fill(struct gfe_softc *); 171 STATIC int gfe_hash_alloc(struct gfe_softc *); 172 173 /* Linkup to the rest of the kernel */ 174 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 175 gfe_match, gfe_attach, NULL, NULL); 176 177 extern struct cfdriver gfe_cd; 178 179 int 180 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 181 { 182 struct gt_softc *gt = (struct gt_softc *) parent; 183 struct gt_attach_args *ga = aux; 184 uint8_t enaddr[6]; 185 186 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 187 return 0; 188 189 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 190 return 0; 191 192 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 193 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 194 return 0; 195 196 return 1; 197 } 198 199 /* 200 * Attach this instance, and then all the sub-devices 201 */ 202 void 203 gfe_attach(struct device *parent, struct device *self, void *aux) 204 { 205 struct gt_attach_args *ga = aux; 206 struct gt_softc *gt = (struct gt_softc *) parent; 207 struct gfe_softc *sc = (struct gfe_softc *) self; 208 struct ifnet *ifp; 209 uint32_t data; 210 uint8_t enaddr[6]; 211 int phyaddr; 212 uint32_t sdcr; 213 214 GT_ETHERFOUND(gt, ga); 215 216 sc->sc_gt_memt = ga->ga_memt; 217 sc->sc_gt_memh = ga->ga_memh; 218 sc->sc_dmat = ga->ga_dmat; 219 sc->sc_macno = ga->ga_unit; 220 221 callout_init(&sc->sc_co); 222 223 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 224 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 225 226 gtget_macaddr(gt, sc->sc_macno, enaddr); 227 228 sc->sc_pcr = GE_READ(sc, EPCR); 229 sc->sc_pcxr = GE_READ(sc, EPCXR); 230 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 231 232 aprint_normal(": address %s", ether_sprintf(enaddr)); 233 234 #if defined(DEBUG) 235 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 236 #endif 237 238 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 239 if (sc->sc_dev.dv_cfdata->cf_flags & 1) { 240 aprint_normal(", phy %d (rmii)", phyaddr); 241 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 242 } else { 243 aprint_normal(", phy %d (mii)", phyaddr); 244 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 245 } 246 sc->sc_pcxr &= ~(3 << 14); 247 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 248 249 if (sc->sc_pcr & ETH_EPCR_EN) { 250 int tries = 1000; 251 /* 252 * Abort transmitter and receiver and wait for them to quiese 253 */ 254 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 255 do { 256 delay(100); 257 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 258 } 259 260 sc->sc_pcr &= ~ETH_EPCR_EN; 261 262 #if defined(DEBUG) 263 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 264 #endif 265 266 /* 267 * Now turn off the GT. If it didn't quiese, too ***ing bad. 268 */ 269 GE_WRITE(sc, EPCR, sc->sc_pcr); 270 GE_WRITE(sc, EIMR, sc->sc_intrmask); 271 sdcr = GE_READ(sc, ESDCR); 272 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 273 sdcr |= ETH_ESDCR_RIFB; 274 GE_WRITE(sc, ESDCR, sdcr); 275 sc->sc_max_frame_length = 1536; 276 277 aprint_normal("\n"); 278 sc->sc_mii.mii_ifp = &sc->sc_ec.ec_if; 279 sc->sc_mii.mii_readreg = gfe_mii_read; 280 sc->sc_mii.mii_writereg = gfe_mii_write; 281 sc->sc_mii.mii_statchg = gfe_mii_statchg; 282 283 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 284 gfe_mii_mediastatus); 285 286 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 287 MII_OFFSET_ANY, MIIF_NOISOLATE); 288 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 289 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 290 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 291 } else { 292 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 293 } 294 295 ifp = &sc->sc_ec.ec_if; 296 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 297 ifp->if_softc = sc; 298 /* ifp->if_mowner = &sc->sc_mowner; */ 299 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 300 #if 0 301 ifp->if_flags |= IFF_DEBUG; 302 #endif 303 ifp->if_ioctl = gfe_ifioctl; 304 ifp->if_start = gfe_ifstart; 305 ifp->if_watchdog = gfe_ifwatchdog; 306 307 if_attach(ifp); 308 ether_ifattach(ifp, enaddr); 309 #if NBPFILTER > 0 310 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 311 #endif 312 #if NRND > 0 313 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 314 #endif 315 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 316 gfe_intr, sc); 317 } 318 319 int 320 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 321 size_t size, int flags) 322 { 323 int error = 0; 324 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 325 gdm->gdm_size = size; 326 gdm->gdm_maxsegs = maxsegs; 327 328 #if 1 329 flags |= BUS_DMA_NOCACHE; 330 #endif 331 332 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, NBPG, 333 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 334 BUS_DMA_NOWAIT); 335 if (error) 336 goto fail; 337 338 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 339 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 340 if (error) 341 goto fail; 342 343 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 344 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 345 if (error) 346 goto fail; 347 348 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 349 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 350 if (error) 351 goto fail; 352 353 /* invalidate from cache */ 354 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 355 BUS_DMASYNC_PREREAD); 356 fail: 357 if (error) { 358 gfe_dmamem_free(sc, gdm); 359 GE_DPRINTF(sc, (":err=%d", error)); 360 } 361 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 362 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 363 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 364 GE_FUNC_EXIT(sc, ""); 365 return error; 366 } 367 368 void 369 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 370 { 371 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 372 if (gdm->gdm_map) 373 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 374 if (gdm->gdm_kva) 375 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 376 if (gdm->gdm_nsegs > 0) 377 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 378 gdm->gdm_map = NULL; 379 gdm->gdm_kva = NULL; 380 gdm->gdm_nsegs = 0; 381 GE_FUNC_EXIT(sc, ""); 382 } 383 384 int 385 gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 386 { 387 struct gfe_softc * const sc = ifp->if_softc; 388 struct ifreq *ifr = (struct ifreq *) data; 389 struct ifaddr *ifa = (struct ifaddr *) data; 390 int s, error = 0; 391 392 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 393 s = splnet(); 394 395 switch (cmd) { 396 case SIOCSIFADDR: 397 ifp->if_flags |= IFF_UP; 398 switch (ifa->ifa_addr->sa_family) { 399 #ifdef INET 400 case AF_INET: 401 error = gfe_whack(sc, GE_WHACK_START); 402 if (error == 0) 403 arp_ifinit(ifp, ifa); 404 break; 405 #endif 406 default: 407 error = gfe_whack(sc, GE_WHACK_START); 408 break; 409 } 410 break; 411 412 case SIOCSIFFLAGS: 413 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 414 case IFF_UP|IFF_RUNNING:/* active->active, update */ 415 error = gfe_whack(sc, GE_WHACK_CHANGE); 416 break; 417 case IFF_RUNNING: /* not up, so we stop */ 418 error = gfe_whack(sc, GE_WHACK_STOP); 419 break; 420 case IFF_UP: /* not running, so we start */ 421 error = gfe_whack(sc, GE_WHACK_START); 422 break; 423 case 0: /* idle->idle: do nothing */ 424 break; 425 } 426 break; 427 428 case SIOCADDMULTI: 429 case SIOCDELMULTI: 430 error = (cmd == SIOCADDMULTI) 431 ? ether_addmulti(ifr, &sc->sc_ec) 432 : ether_delmulti(ifr, &sc->sc_ec); 433 if (error == ENETRESET) { 434 if (ifp->if_flags & IFF_RUNNING) 435 error = gfe_whack(sc, GE_WHACK_CHANGE); 436 else 437 error = 0; 438 } 439 break; 440 441 case SIOCSIFMTU: 442 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 443 error = EINVAL; 444 break; 445 } 446 ifp->if_mtu = ifr->ifr_mtu; 447 break; 448 449 case SIOCSIFMEDIA: 450 case SIOCGIFMEDIA: 451 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 452 break; 453 454 default: 455 error = EINVAL; 456 break; 457 } 458 splx(s); 459 GE_FUNC_EXIT(sc, ""); 460 return error; 461 } 462 463 void 464 gfe_ifstart(struct ifnet *ifp) 465 { 466 struct gfe_softc * const sc = ifp->if_softc; 467 struct mbuf *m; 468 469 GE_FUNC_ENTER(sc, "gfe_ifstart"); 470 471 if ((ifp->if_flags & IFF_RUNNING) == 0) { 472 GE_FUNC_EXIT(sc, "$"); 473 return; 474 } 475 476 if (sc->sc_txq[GE_TXPRIO_HI] == NULL) { 477 ifp->if_flags |= IFF_OACTIVE; 478 #if defined(DEBUG) || defined(DIAGNOSTIC) 479 printf("%s: ifstart: txq not yet created\n", ifp->if_xname); 480 #endif 481 GE_FUNC_EXIT(sc, ""); 482 return; 483 } 484 485 for (;;) { 486 IF_DEQUEUE(&ifp->if_snd, m); 487 if (m == NULL) { 488 ifp->if_flags &= ~IFF_OACTIVE; 489 GE_FUNC_EXIT(sc, ""); 490 return; 491 } 492 493 /* 494 * No space in the pending queue? try later. 495 */ 496 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq)) 497 break; 498 499 /* 500 * Try to enqueue a mbuf to the device. If that fails, we 501 * can always try to map the next mbuf. 502 */ 503 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq, m); 504 GE_DPRINTF(sc, (">")); 505 #ifndef GE_NOTX 506 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 507 #endif 508 } 509 510 /* 511 * Attempt to queue the mbuf for send failed. 512 */ 513 IF_PREPEND(&ifp->if_snd, m); 514 ifp->if_flags |= IFF_OACTIVE; 515 GE_FUNC_EXIT(sc, "%%"); 516 } 517 518 void 519 gfe_ifwatchdog(struct ifnet *ifp) 520 { 521 struct gfe_softc * const sc = ifp->if_softc; 522 struct gfe_txqueue *txq; 523 524 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 525 printf("%s: device timeout", 526 sc->sc_dev.dv_xname); 527 if ((txq = sc->sc_txq[GE_TXPRIO_HI]) != NULL) { 528 unsigned int curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / 16; 529 printf(" (fi=%d,lo=%d,cur=%d(%#x),icm=%#x) ", 530 txq->txq_fi, txq->txq_lo, curtxdnum, 531 txq->txq_descs[curtxdnum].ed_cmdsts, 532 GE_READ(sc, EICR)); 533 } 534 printf("\n"); 535 ifp->if_oerrors++; 536 (void) gfe_whack(sc, GE_WHACK_RESTART); 537 GE_FUNC_EXIT(sc, ""); 538 } 539 540 int 542 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 543 { 544 struct gfe_rxqueue *rxq; 545 volatile struct gt_eth_desc *rxd; 546 const bus_dma_segment_t *ds; 547 int error; 548 int idx; 549 bus_addr_t nxtaddr; 550 bus_size_t boff; 551 552 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 553 GE_DPRINTF(sc, ("(%d)", rxprio)); 554 if (sc->sc_rxq[rxprio] != NULL) { 555 GE_FUNC_EXIT(sc, ""); 556 return 0; 557 } 558 559 rxq = (struct gfe_rxqueue *) malloc(sizeof(*rxq), M_DEVBUF, M_NOWAIT); 560 if (rxq == NULL) { 561 GE_FUNC_EXIT(sc, "!"); 562 return ENOMEM; 563 } 564 565 memset(rxq, 0, sizeof(*rxq)); 566 567 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 568 GE_RXDESC_MEMSIZE, 0); 569 if (error) { 570 free(rxq, M_DEVBUF); 571 GE_FUNC_EXIT(sc, "!!"); 572 return error; 573 } 574 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 575 GE_RXBUF_MEMSIZE, 0); 576 if (error) { 577 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 578 free(rxq, M_DEVBUF); 579 GE_FUNC_EXIT(sc, "!!!"); 580 return error; 581 } 582 583 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_TXMEM_SIZE); 584 585 sc->sc_rxq[rxprio] = rxq; 586 rxq->rxq_descs = 587 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 588 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 589 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 590 rxq->rxq_fi = 0; 591 rxq->rxq_active = GE_RXDESC_MAX; 592 for (idx = 0, rxd = rxq->rxq_descs, 593 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 594 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 595 idx < GE_RXDESC_MAX; 596 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 597 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 598 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 599 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 600 /* 601 * update the nxtptr to point to the next txd. 602 */ 603 if (idx == GE_RXDESC_MAX - 1) 604 nxtaddr = rxq->rxq_desc_busaddr; 605 rxd->ed_nxtptr = htogt32(nxtaddr); 606 boff += GE_RXBUF_SIZE; 607 if (boff == ds->ds_len) { 608 ds++; 609 boff = 0; 610 } 611 } 612 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 613 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 614 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 615 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 616 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 617 BUS_DMASYNC_PREREAD); 618 619 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 620 switch (rxprio) { 621 case GE_RXPRIO_HI: 622 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 623 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 624 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 625 break; 626 case GE_RXPRIO_MEDHI: 627 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 628 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 629 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 630 break; 631 case GE_RXPRIO_MEDLO: 632 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 633 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 634 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 635 break; 636 case GE_RXPRIO_LO: 637 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 638 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 639 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 640 break; 641 } 642 GE_FUNC_EXIT(sc, ""); 643 return error; 644 } 645 646 #if PKT_DUMP 647 static void pkt_dump(struct gfe_softc *sc, unsigned char *p, int l); 648 static void 649 pkt_dump(struct gfe_softc *sc, unsigned char *p, int l) 650 { 651 char str[17]; 652 int j; 653 654 str[16] = '\0'; 655 while (l) { 656 printf("%08lx:", (unsigned long) p); 657 for (j=0;j<16 && l;j++, l--, p++) { 658 printf(" %02x", (unsigned) *p); 659 str[j] = (*p < ' ' || *p > '~') ? '.' : *p; 660 } 661 while (j < 16) { printf(" "); str[j++] = ' '; } 662 printf(" %s\n", str); 663 } 664 } 665 #endif 666 667 void 668 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 669 { 670 struct ifnet * const ifp = &sc->sc_ec.ec_if; 671 struct gfe_rxqueue * const rxq = sc->sc_rxq[rxprio]; 672 struct mbuf *m = rxq->rxq_curpkt; 673 674 GE_FUNC_ENTER(sc, "gfe_rx_get"); 675 GE_DPRINTF(sc, ("(%d)", rxprio)); 676 677 while (rxq->rxq_active > 0) { 678 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 679 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 680 const struct ether_header *eh; 681 unsigned int cmdsts; 682 size_t buflen; 683 684 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 685 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 686 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 687 cmdsts = gt32toh(rxd->ed_cmdsts); 688 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 689 rxq->rxq_cmdsts = cmdsts; 690 /* 691 * Sometimes the GE "forgets" to reset the ownership bit. 692 * But if the length has been rewritten, the packet is ours 693 * so pretend the O bit is set. 694 */ 695 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 696 if ((cmdsts & RX_CMD_O) && buflen == 0) { 697 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 698 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 699 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 700 break; 701 } 702 703 /* 704 * If this is not a single buffer packet with no errors 705 * or for some reason it's bigger than our frame size, 706 * ignore it and go to the next packet. 707 */ 708 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 709 (RX_CMD_F|RX_CMD_L) || 710 buflen > sc->sc_max_frame_length) { 711 GE_DPRINTF(sc, ("!")); 712 --rxq->rxq_active; 713 ifp->if_ipackets++; 714 ifp->if_ierrors++; 715 goto give_it_back; 716 } 717 718 if (m == NULL) { 719 MGETHDR(m, M_DONTWAIT, MT_DATA); 720 if (m == NULL) { 721 GE_DPRINTF(sc, ("?")); 722 break; 723 } 724 m->m_data += 2; 725 } 726 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 727 MCLGET(m, M_DONTWAIT); 728 if ((m->m_flags & M_EXT) == 0) { 729 GE_DPRINTF(sc, ("?")); 730 break; 731 } 732 m->m_data += 2; 733 } 734 m->m_len = 0; 735 m->m_pkthdr.len = 0; 736 m->m_pkthdr.rcvif = &sc->sc_ec.ec_if; 737 rxq->rxq_cmdsts = cmdsts; 738 --rxq->rxq_active; 739 740 ifp->if_ibytes += buflen; 741 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 742 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 743 744 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 745 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 746 #if PKT_DUMP 747 printf("[%d]\n", buflen); 748 pkt_dump(sc,m->m_data+m->m_len,buflen); 749 #endif 750 m->m_len = buflen; 751 m->m_pkthdr.len = buflen; 752 753 ifp->if_ipackets++; 754 #ifdef M_HASFCS 755 m->m_flags |= M_HASFCS; 756 #else 757 m->m_len -= 4; 758 m->m_pkthdr.len -= 4; 759 #endif 760 #if NBPFILTER > 0 761 if (ifp->if_bpf != NULL) 762 bpf_mtap(ifp->if_bpf, m); 763 #endif 764 765 eh = (const struct ether_header *) m->m_data; 766 if ((ifp->if_flags & IFF_PROMISC) || 767 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 768 (rxq->rxq_cmdsts & RX_STS_HE) || 769 (eh->ether_dhost[0] & 1) != 0 || 770 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 771 ETHER_ADDR_LEN) == 0) { 772 (*ifp->if_input)(ifp, m); 773 m = NULL; 774 GE_DPRINTF(sc, (">")); 775 } else { 776 m->m_len = 0; 777 m->m_pkthdr.len = 0; 778 GE_DPRINTF(sc, ("+")); 779 } 780 rxq->rxq_cmdsts = 0; 781 782 give_it_back: 783 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 784 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 785 #if 0 786 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 787 rxq->rxq_fi, 788 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 789 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 790 #endif 791 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 792 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 793 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 794 rxq->rxq_fi = (rxd->ed_nxtptr - rxq->rxq_desc_busaddr) / 795 sizeof(*rxd); 796 #if 0 797 if (++rxq->rxq_fi == GE_RXDESC_MAX) 798 rxq->rxq_fi = 0; 799 #endif 800 rxq->rxq_active++; 801 } 802 rxq->rxq_curpkt = m; 803 GE_FUNC_EXIT(sc, ""); 804 } 805 806 uint32_t 807 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 808 { 809 struct gfe_rxqueue *rxq; 810 uint32_t rxbits; 811 #define RXPRIO_DECODER 0xffffaa50 812 GE_FUNC_ENTER(sc, "gfe_rx_process"); 813 814 rxbits = ETH_IR_RxBuffer_GET(cause); 815 while (rxbits) { 816 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 817 GE_DPRINTF(sc, ("%1x", rxbits)); 818 rxbits &= ~(1 << rxprio); 819 gfe_rx_get(sc, rxprio); 820 } 821 822 rxbits = ETH_IR_RxError_GET(cause); 823 while (rxbits) { 824 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 825 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 826 int idx; 827 rxbits &= ~(1 << rxprio); 828 rxq = sc->sc_rxq[rxprio]; 829 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 830 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 831 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 832 sc->sc_tickflags |= GE_TICK_RX_RESTART; 833 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 834 } 835 sc->sc_ec.ec_if.if_ierrors++; 836 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 837 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 838 memset(masks, 0, sizeof(masks)); 839 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 840 0, rxq->rxq_desc_mem.gdm_size, 841 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 842 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 843 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 844 845 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 846 masks[idx/32] |= 1 << (idx & 31); 847 } 848 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 849 0, rxq->rxq_desc_mem.gdm_size, 850 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 851 #if defined(DEBUG) 852 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 853 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 854 rxq->rxq_cmdsts, masks[0], masks[1]); 855 #endif 856 } 857 if ((intrmask & ETH_IR_RxBits) == 0) 858 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 859 860 GE_FUNC_EXIT(sc, ""); 861 return intrmask; 862 } 863 864 int 865 gfe_rx_prime(struct gfe_softc *sc) 866 { 867 struct gfe_rxqueue *rxq; 868 int error; 869 870 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 871 872 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 873 if (error) 874 goto bail; 875 rxq = sc->sc_rxq[GE_RXPRIO_HI]; 876 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 877 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 878 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 879 } 880 sc->sc_intrmask |= rxq->rxq_intrbits; 881 882 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 883 if (error) 884 goto bail; 885 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 886 rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 887 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 888 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 889 sc->sc_intrmask |= rxq->rxq_intrbits; 890 } 891 892 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 893 if (error) 894 goto bail; 895 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 896 rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 897 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 898 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 899 sc->sc_intrmask |= rxq->rxq_intrbits; 900 } 901 902 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 903 if (error) 904 goto bail; 905 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 906 rxq = sc->sc_rxq[GE_RXPRIO_LO]; 907 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 908 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 909 sc->sc_intrmask |= rxq->rxq_intrbits; 910 } 911 912 bail: 913 GE_FUNC_EXIT(sc, ""); 914 return error; 915 } 916 917 void 918 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 919 { 920 struct gfe_rxqueue *rxq = sc->sc_rxq[rxprio]; 921 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 922 if (rxq == NULL) { 923 GE_FUNC_EXIT(sc, ""); 924 return; 925 } 926 927 if (rxq->rxq_curpkt) 928 m_freem(rxq->rxq_curpkt); 929 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 930 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 931 free(rxq, M_DEVBUF); 932 sc->sc_rxq[rxprio] = NULL; 933 GE_FUNC_EXIT(sc, ""); 934 } 935 936 void 937 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 938 { 939 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 940 sc->sc_flags &= ~GE_RXACTIVE; 941 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 942 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 943 GE_WRITE(sc, EIMR, sc->sc_intrmask); 944 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 945 do { 946 delay(10); 947 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 948 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 949 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 950 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 951 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 952 GE_FUNC_EXIT(sc, ""); 953 } 954 955 void 957 gfe_tick(void *arg) 958 { 959 struct gfe_softc * const sc = arg; 960 uint32_t intrmask; 961 unsigned int tickflags; 962 int s; 963 964 GE_FUNC_ENTER(sc, "gfe_tick"); 965 966 s = splnet(); 967 968 tickflags = sc->sc_tickflags; 969 sc->sc_tickflags = 0; 970 intrmask = sc->sc_intrmask; 971 if (tickflags & GE_TICK_TX_IFSTART) 972 gfe_ifstart(&sc->sc_ec.ec_if); 973 if (tickflags & GE_TICK_RX_RESTART) { 974 intrmask |= sc->sc_idlemask; 975 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 976 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_HI]; 977 rxq->rxq_fi = 0; 978 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 979 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 980 } 981 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 982 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 983 rxq->rxq_fi = 0; 984 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 985 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 986 } 987 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 988 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 989 rxq->rxq_fi = 0; 990 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 991 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 992 } 993 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 994 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_LO]; 995 rxq->rxq_fi = 0; 996 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 997 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 998 } 999 sc->sc_idlemask = 0; 1000 } 1001 if (intrmask != sc->sc_intrmask) { 1002 sc->sc_intrmask = intrmask; 1003 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1004 } 1005 gfe_intr(sc); 1006 splx(s); 1007 1008 GE_FUNC_EXIT(sc, ""); 1009 } 1010 1011 int 1012 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1013 { 1014 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1015 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1016 uint32_t intrmask = sc->sc_intrmask; 1017 struct mbuf *m; 1018 1019 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1020 1021 /* 1022 * Anything in the pending queue to enqueue? if not, punt. 1023 * otherwise grab its dmamap. 1024 */ 1025 if ((m = txq->txq_pendq.ifq_head) == NULL) { 1026 GE_FUNC_EXIT(sc, "-"); 1027 return 0; 1028 } 1029 1030 /* 1031 * Have we [over]consumed our limit of descriptors? 1032 * Do we have enough free descriptors? 1033 */ 1034 if (GE_TXDESC_MAX == txq->txq_nactive + 1) { 1035 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1036 uint32_t cmdsts; 1037 size_t pktlen; 1038 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1039 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1040 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1041 cmdsts = gt32toh(txd2->ed_cmdsts); 1042 if (cmdsts & TX_CMD_O) { 1043 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1044 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1045 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1046 GE_FUNC_EXIT(sc, "@"); 1047 return 0; 1048 } 1049 if (++txq->txq_fi == GE_TXDESC_MAX) 1050 txq->txq_fi = 0; 1051 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1052 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1053 txq->txq_inptr += (pktlen + 7) & ~7; 1054 txq->txq_nactive--; 1055 1056 /* statistics */ 1057 sc->sc_ec.ec_if.if_opackets++; 1058 sc->sc_ec.ec_if.if_obytes += pktlen; 1059 if (cmdsts & TX_STS_ES) 1060 sc->sc_ec.ec_if.if_oerrors++; 1061 GE_DPRINTF(sc, ("%%")); 1062 } 1063 1064 /* 1065 * If this packet would wrap around the end of the buffer, reset back 1066 * to the beginning. 1067 */ 1068 if (txq->txq_outptr + m->m_pkthdr.len > GE_TXBUF_SIZE) { 1069 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1070 txq->txq_outptr = 0; 1071 } 1072 1073 /* 1074 * Make sure the output packet doesn't run over the beginning of 1075 * what we've already given the GT. 1076 */ 1077 if (txq->txq_outptr <= txq->txq_inptr && 1078 txq->txq_outptr + m->m_pkthdr.len > txq->txq_inptr) { 1079 intrmask |= txq->txq_intrbits & 1080 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1081 if (sc->sc_intrmask != intrmask) { 1082 sc->sc_intrmask = intrmask; 1083 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1084 } 1085 GE_FUNC_EXIT(sc, "#"); 1086 return 0; 1087 } 1088 1089 /* 1090 * The end-of-list descriptor we put on last time is the starting point 1091 * for this packet. The GT is supposed to terminate list processing on 1092 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1093 * must terminate the list. 1094 */ 1095 intrmask = sc->sc_intrmask; 1096 1097 m_copydata(m, 0, m->m_pkthdr.len, 1098 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1099 #if PKT_DUMP 1100 GE_DPRINTF(sc,("\n")); 1101 pkt_dump(sc, txq->txq_buf_mem.gdm_kva + txq->txq_outptr, m->m_pkthdr.len); 1102 #endif 1103 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1104 txq->txq_outptr, m->m_pkthdr.len, BUS_DMASYNC_PREWRITE); 1105 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1106 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1107 #if 0 1108 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1109 txq->txq_lo * sizeof(*txd), sizeof(*txd), 1110 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1111 #endif 1112 1113 /* 1114 * Request a buffer interrupt every 2/3 of the way thru the transmit 1115 * buffer. 1116 */ 1117 txq->txq_ei_gapcount += m->m_pkthdr.len + 7; 1118 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1119 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1120 txq->txq_ei_gapcount = 0; 1121 } else { 1122 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1123 } 1124 #if 0 1125 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1126 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1127 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1128 #endif 1129 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1130 txq->txq_lo * sizeof(*txd), sizeof(*txd), 1131 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1132 1133 txq->txq_outptr += (m->m_pkthdr.len + 31) & ~31; 1134 /* 1135 * Tell the SDMA engine to "Fetch!" 1136 */ 1137 GE_WRITE(sc, ESDCMR, 1138 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1139 1140 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1141 1142 /* 1143 * Update the last out appropriately. 1144 */ 1145 if (++txq->txq_lo == GE_TXDESC_MAX) 1146 txq->txq_lo = 0; 1147 1148 /* 1149 * Move mbuf from the pending queue to the snd queue. 1150 */ 1151 IF_DEQUEUE(&txq->txq_pendq, m); 1152 #if NBPFILTER > 0 1153 if (sc->sc_ec.ec_if.if_bpf != NULL) 1154 bpf_mtap(sc->sc_ec.ec_if.if_bpf, m); 1155 #endif 1156 m_freem(m); 1157 sc->sc_ec.ec_if.if_flags &= ~IFF_OACTIVE; 1158 1159 /* 1160 * Since we have put an item into the packet queue, we now want 1161 * an interrupt when the transmit queue finishes processing the 1162 * list. But only update the mask if needs changing. 1163 */ 1164 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1165 if (sc->sc_intrmask != intrmask) { 1166 sc->sc_intrmask = intrmask; 1167 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1168 } 1169 if (sc->sc_ec.ec_if.if_timer == 0) 1170 sc->sc_ec.ec_if.if_timer = 5; 1171 GE_FUNC_EXIT(sc, "*"); 1172 return 1; 1173 } 1174 1175 uint32_t 1176 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1177 { 1178 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1179 1180 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1181 1182 if (txq == NULL) { 1183 GE_FUNC_EXIT(sc, ""); 1184 return intrmask; 1185 } 1186 1187 while (txq->txq_nactive > 0) { 1188 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1189 uint32_t cmdsts; 1190 size_t pktlen; 1191 1192 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1193 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1194 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1195 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1196 /* 1197 * If the GT owns this descriptor and according 1198 * to the status register, the transmit engine 1199 * is not running, restart it. 1200 */ 1201 #if 0 1202 if ((GE_READ(sc, EPSR) & txq->txq_epsrbits & 1203 (ETH_EPSR_TxHigh|ETH_EPSR_TxLow)) == 0) { 1204 /* 1205 * If the current transmit descriptor isn't 1206 * pointing at this descriptor, then we've 1207 * lost synch, reset it to this one before 1208 * restarting. 1209 */ 1210 unsigned int curtxdnum = ( 1211 gt_read(sc->sc_dev.dv_parent, 1212 txq->txq_ectdp) - 1213 txq->txq_desc_busaddr) / 16; 1214 if (curtxdnum != txq->txq_fi) { 1215 gt_write(sc->sc_dev.dv_parent, 1216 txq->txq_ectdp, 1217 txq->txq_desc_busaddr + 1218 sizeof(*ed) * txq->txq_fi); 1219 GE_DPRINTF(sc, 1220 ("(oldcur=%d,newcur=fi(%d))", 1221 curtxdnum, txq->txq_fi)); 1222 printf("%s: transmitter synchronization" 1223 " lost at %d; repositioning" 1224 " to %d\n", 1225 sc->sc_dev.dv_xname, 1226 curtxdnum, txq->txq_fi); 1227 } 1228 /* 1229 * [Re-] Kick the transmit engine. 1230 */ 1231 GE_WRITE(sc, ESDCMR, 1232 txq->txq_esdcmrbits & 1233 (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1234 GE_DPRINTF(sc, ("*")); 1235 } 1236 #endif 1237 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1238 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1239 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1240 GE_FUNC_EXIT(sc, ""); 1241 return intrmask; 1242 } 1243 #if 0 1244 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1245 txq->txq_lo, 1246 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1247 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1248 #endif 1249 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1250 if (++txq->txq_fi == GE_TXDESC_MAX) 1251 txq->txq_fi = 0; 1252 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1253 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1254 txq->txq_inptr += (pktlen + 31) & ~31; 1255 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1256 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1257 1258 /* statistics */ 1259 sc->sc_ec.ec_if.if_opackets++; 1260 sc->sc_ec.ec_if.if_obytes += pktlen; 1261 if (cmdsts & TX_STS_ES) 1262 sc->sc_ec.ec_if.if_oerrors++; 1263 1264 txd->ed_bufptr = 0; 1265 1266 sc->sc_ec.ec_if.if_timer = 5; 1267 --txq->txq_nactive; 1268 } 1269 if (txq->txq_nactive != 0) 1270 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1271 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1272 sc->sc_ec.ec_if.if_timer = 0; 1273 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1274 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1275 GE_FUNC_EXIT(sc, ""); 1276 return intrmask; 1277 } 1278 1279 int 1280 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1281 { 1282 struct gfe_txqueue *txq; 1283 volatile struct gt_eth_desc *txd; 1284 unsigned int i; 1285 bus_addr_t addr; 1286 1287 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1288 1289 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1290 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1291 1292 if ((txq = sc->sc_txq[txprio]) == NULL) { 1293 int error; 1294 txq = (struct gfe_txqueue *) malloc(sizeof(*txq), 1295 M_DEVBUF, M_NOWAIT); 1296 if (txq == NULL) { 1297 GE_FUNC_EXIT(sc, ""); 1298 return ENOMEM; 1299 } 1300 memset(txq, 0, sizeof(*txq)); 1301 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1302 GE_TXMEM_SIZE, 0); 1303 if (error) { 1304 free(txq, M_DEVBUF); 1305 GE_FUNC_EXIT(sc, ""); 1306 return error; 1307 } 1308 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, 1309 GE_TXBUF_SIZE, 0); 1310 if (error) { 1311 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1312 free(txq, M_DEVBUF); 1313 GE_FUNC_EXIT(sc, ""); 1314 return error; 1315 } 1316 sc->sc_txq[txprio] = txq; 1317 } 1318 1319 txq->txq_descs = 1320 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1321 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1322 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1323 1324 txq->txq_pendq.ifq_maxlen = 10; 1325 txq->txq_ei_gapcount = 0; 1326 txq->txq_nactive = 0; 1327 txq->txq_fi = 0; 1328 txq->txq_lo = 0; 1329 txq->txq_inptr = GE_TXBUF_SIZE; 1330 txq->txq_outptr = 0; 1331 for (i = 0, txd = txq->txq_descs, 1332 addr = txq->txq_desc_busaddr + sizeof(*txd); 1333 i < GE_TXDESC_MAX - 1; 1334 i++, txd++, addr += sizeof(*txd)) { 1335 /* 1336 * update the nxtptr to point to the next txd. 1337 */ 1338 txd->ed_cmdsts = 0; 1339 txd->ed_nxtptr = htogt32(addr); 1340 } 1341 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1342 htogt32(txq->txq_desc_busaddr); 1343 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1344 GE_TXMEM_SIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1345 1346 switch (txprio) { 1347 case GE_TXPRIO_HI: 1348 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1349 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1350 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1351 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1352 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1353 break; 1354 1355 case GE_TXPRIO_LO: 1356 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1357 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1358 txq->txq_epsrbits = ETH_EPSR_TxLow; 1359 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1360 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1361 break; 1362 1363 case GE_TXPRIO_NONE: 1364 break; 1365 } 1366 #if 0 1367 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1368 gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); 1369 GE_DPRINTF(sc, (")")); 1370 #endif 1371 1372 /* 1373 * If we are restarting, there may be packets in the pending queue 1374 * waiting to be enqueued. Try enqueuing packets from both priority 1375 * queues until the pending queue is empty or there no room for them 1376 * on the device. 1377 */ 1378 while (gfe_tx_enqueue(sc, txprio)) 1379 continue; 1380 1381 GE_FUNC_EXIT(sc, ""); 1382 return 0; 1383 } 1384 1385 void 1386 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1387 { 1388 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1389 1390 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1391 if (txq == NULL) { 1392 GE_FUNC_EXIT(sc, ""); 1393 return; 1394 } 1395 1396 if (!flush) { 1397 GE_FUNC_EXIT(sc, ""); 1398 return; 1399 } 1400 1401 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1402 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1403 free(txq, M_DEVBUF); 1404 sc->sc_txq[txprio] = NULL; 1405 GE_FUNC_EXIT(sc, "-F"); 1406 } 1407 1408 void 1409 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1410 { 1411 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1412 1413 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1414 1415 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1416 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1417 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1418 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1419 1420 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1421 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1422 1423 sc->sc_ec.ec_if.if_timer = 0; 1424 GE_FUNC_EXIT(sc, ""); 1425 } 1426 1427 int 1429 gfe_intr(void *arg) 1430 { 1431 struct gfe_softc * const sc = arg; 1432 uint32_t cause; 1433 uint32_t intrmask = sc->sc_intrmask; 1434 int claim = 0; 1435 int cnt; 1436 1437 GE_FUNC_ENTER(sc, "gfe_intr"); 1438 1439 for (cnt = 0; cnt < 4; cnt++) { 1440 if (sc->sc_intrmask != intrmask) { 1441 sc->sc_intrmask = intrmask; 1442 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1443 } 1444 cause = GE_READ(sc, EICR); 1445 cause &= sc->sc_intrmask; 1446 GE_DPRINTF(sc, (".%#x", cause)); 1447 if (cause == 0) 1448 break; 1449 1450 claim = 1; 1451 1452 GE_WRITE(sc, EICR, ~cause); 1453 #ifndef GE_NORX 1454 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1455 intrmask = gfe_rx_process(sc, cause, intrmask); 1456 #endif 1457 1458 #ifndef GE_NOTX 1459 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1460 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1461 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1462 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1463 #endif 1464 if (cause & ETH_IR_MIIPhySTC) { 1465 sc->sc_flags |= GE_PHYSTSCHG; 1466 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1467 } 1468 } 1469 1470 GE_FUNC_EXIT(sc, ""); 1471 return claim; 1472 } 1473 1474 int 1476 gfe_mii_mediachange (struct ifnet *ifp) 1477 { 1478 struct gfe_softc *sc = ifp->if_softc; 1479 1480 if (ifp->if_flags & IFF_UP) 1481 mii_mediachg(&sc->sc_mii); 1482 1483 return (0); 1484 } 1485 void 1486 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1487 { 1488 struct gfe_softc *sc = ifp->if_softc; 1489 1490 if (sc->sc_flags & GE_PHYSTSCHG) { 1491 sc->sc_flags &= ~GE_PHYSTSCHG; 1492 mii_pollstat(&sc->sc_mii); 1493 } 1494 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1495 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1496 } 1497 1498 int 1499 gfe_mii_read (struct device *self, int phy, int reg) 1500 { 1501 return gt_mii_read(self, self->dv_parent, phy, reg); 1502 } 1503 1504 void 1505 gfe_mii_write (struct device *self, int phy, int reg, int value) 1506 { 1507 gt_mii_write(self, self->dv_parent, phy, reg, value); 1508 } 1509 1510 void 1511 gfe_mii_statchg (struct device *self) 1512 { 1513 /* struct gfe_softc *sc = (struct gfe_softc *) self; */ 1514 /* do nothing? */ 1515 } 1516 1517 int 1519 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1520 { 1521 int error = 0; 1522 GE_FUNC_ENTER(sc, "gfe_whack"); 1523 1524 switch (op) { 1525 case GE_WHACK_RESTART: 1526 #ifndef GE_NOTX 1527 gfe_tx_stop(sc, op); 1528 #endif 1529 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1530 /* FALLTHROUGH */ 1531 case GE_WHACK_START: 1532 #ifndef GE_NOHASH 1533 if (error == 0 && sc->sc_hashtable == NULL) { 1534 error = gfe_hash_alloc(sc); 1535 if (error) 1536 break; 1537 } 1538 if (op != GE_WHACK_RESTART) 1539 gfe_hash_fill(sc); 1540 #endif 1541 #ifndef GE_NORX 1542 if (op != GE_WHACK_RESTART) { 1543 error = gfe_rx_prime(sc); 1544 if (error) 1545 break; 1546 } 1547 #endif 1548 #ifndef GE_NOTX 1549 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1550 if (error) 1551 break; 1552 #endif 1553 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1554 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1555 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1556 GE_WRITE(sc, EICR, 0); 1557 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1558 #ifndef GE_NOHASH 1559 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1560 #endif 1561 #ifndef GE_NORX 1562 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1563 sc->sc_flags |= GE_RXACTIVE; 1564 #endif 1565 /* FALLTHROUGH */ 1566 case GE_WHACK_CHANGE: 1567 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1568 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1569 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1570 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1571 gfe_ifstart(&sc->sc_ec.ec_if); 1572 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1573 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1574 GE_FUNC_EXIT(sc, ""); 1575 return error; 1576 case GE_WHACK_STOP: 1577 break; 1578 } 1579 1580 #ifdef GE_DEBUG 1581 if (error) 1582 GE_DPRINTF(sc, (" failed: %d\n", error)); 1583 #endif 1584 GE_WRITE(sc, EPCR, sc->sc_pcr); 1585 GE_WRITE(sc, EIMR, 0); 1586 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1587 #ifndef GE_NOTX 1588 gfe_tx_stop(sc, GE_WHACK_STOP); 1589 #endif 1590 #ifndef GE_NORX 1591 gfe_rx_stop(sc, GE_WHACK_STOP); 1592 #endif 1593 #ifndef GE_NOHASH 1594 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1595 sc->sc_hashtable = NULL; 1596 #endif 1597 1598 GE_FUNC_EXIT(sc, ""); 1599 return error; 1600 } 1601 1602 int 1604 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1605 { 1606 uint32_t w0, add0, add1; 1607 uint32_t result; 1608 1609 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1610 add0 = ((uint32_t) eaddr[5] << 0) | 1611 ((uint32_t) eaddr[4] << 8) | 1612 ((uint32_t) eaddr[3] << 16); 1613 1614 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1615 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1616 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1617 1618 add1 = ((uint32_t) eaddr[2] << 0) | 1619 ((uint32_t) eaddr[1] << 8) | 1620 ((uint32_t) eaddr[0] << 16); 1621 1622 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1623 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1624 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1625 1626 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1627 /* 1628 * hashResult is the 15 bits Hash entry address. 1629 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1630 * MAC address, by nibble swapping in every byte (i.e MAC address 1631 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1632 */ 1633 1634 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1635 /* 1636 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1637 * 1638 * hashFunc0 calculates the hashResult in the following manner: 1639 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1640 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1641 */ 1642 result = (add0 & 3) | ((add0 >> 6) & ~3); 1643 result ^= (add0 >> 15) ^ (add1 >> 0); 1644 result &= 0x1ff; 1645 /* 1646 * hashResult[14:9] = ethernetADD[7:2] 1647 */ 1648 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1649 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1650 } else { 1651 #define TRIBITFLIP 073516240 /* yes its in octal */ 1652 /* 1653 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1654 * 1655 * hashFunc1 calculates the hashResult in the following manner: 1656 * hashResult[08:00] = ethernetADD[06:14] 1657 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1658 */ 1659 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1660 /* 1661 * Now bitswap those 9 bits 1662 */ 1663 result = 0; 1664 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1665 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1666 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1667 1668 /* 1669 * hashResult[14:09] = ethernetADD[00:05] 1670 */ 1671 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1672 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1673 GE_DPRINTF(sc, ("1(%#x)", result)); 1674 } 1675 GE_FUNC_EXIT(sc, ""); 1676 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1677 } 1678 1679 int 1680 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1681 enum gfe_rxprio prio, const u_int8_t eaddr[ETHER_ADDR_LEN]) 1682 { 1683 uint64_t he; 1684 uint64_t *maybe_he_p = NULL; 1685 int limit; 1686 int hash; 1687 int maybe_hash = 0; 1688 1689 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1690 1691 hash = gfe_hash_compute(sc, eaddr); 1692 1693 if (sc->sc_hashtable == NULL) { 1694 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1695 __LINE__); 1696 } 1697 1698 /* 1699 * Assume we are going to insert so create the hash entry we 1700 * are going to insert. We also use it to match entries we 1701 * will be removing. 1702 */ 1703 he = ((uint64_t) eaddr[5] << 43) | 1704 ((uint64_t) eaddr[4] << 35) | 1705 ((uint64_t) eaddr[3] << 27) | 1706 ((uint64_t) eaddr[2] << 19) | 1707 ((uint64_t) eaddr[1] << 11) | 1708 ((uint64_t) eaddr[0] << 3) | 1709 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1710 1711 /* 1712 * The GT will search upto 12 entries for a hit, so we must mimic that. 1713 */ 1714 hash &= sc->sc_hashmask / sizeof(he); 1715 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1716 /* 1717 * Does the GT wrap at the end, stop at the, or overrun the 1718 * end? Assume it wraps for now. Stash a copy of the 1719 * current hash entry. 1720 */ 1721 uint64_t *he_p = &sc->sc_hashtable[hash]; 1722 uint64_t thishe = *he_p; 1723 1724 /* 1725 * If the hash entry isn't valid, that break the chain. And 1726 * this entry a good candidate for reuse. 1727 */ 1728 if ((thishe & HSH_V) == 0) { 1729 maybe_he_p = he_p; 1730 break; 1731 } 1732 1733 /* 1734 * If the hash entry has the same address we are looking for 1735 * then ... if we are removing and the skip bit is set, its 1736 * already been removed. if are adding and the skip bit is 1737 * clear, then its already added. In either return EBUSY 1738 * indicating the op has already been done. Otherwise flip 1739 * the skip bit and return 0. 1740 */ 1741 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1742 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1743 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1744 return EBUSY; 1745 *he_p = thishe ^ HSH_S; 1746 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1747 hash * sizeof(he), sizeof(he), 1748 BUS_DMASYNC_PREWRITE); 1749 GE_FUNC_EXIT(sc, "^"); 1750 return 0; 1751 } 1752 1753 /* 1754 * If we haven't found a slot for the entry and this entry 1755 * is currently being skipped, return this entry. 1756 */ 1757 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1758 maybe_he_p = he_p; 1759 maybe_hash = hash; 1760 } 1761 1762 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1763 } 1764 1765 /* 1766 * If we got here, then there was no entry to remove. 1767 */ 1768 if (op == GE_HASH_REMOVE) { 1769 GE_FUNC_EXIT(sc, "?"); 1770 return ENOENT; 1771 } 1772 1773 /* 1774 * If we couldn't find a slot, return an error. 1775 */ 1776 if (maybe_he_p == NULL) { 1777 GE_FUNC_EXIT(sc, "!"); 1778 return ENOSPC; 1779 } 1780 1781 /* Update the entry. 1782 */ 1783 *maybe_he_p = he; 1784 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1785 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1786 GE_FUNC_EXIT(sc, "+"); 1787 return 0; 1788 } 1789 1790 int 1791 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1792 { 1793 struct gfe_softc * const sc = ec->ec_if.if_softc; 1794 int error; 1795 enum gfe_hash_op op; 1796 enum gfe_rxprio prio; 1797 1798 GE_FUNC_ENTER(sc, "hash_multichg"); 1799 /* 1800 * Is this a wildcard entry? If so and its being removed, recompute. 1801 */ 1802 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1803 if (cmd == SIOCDELMULTI) { 1804 GE_FUNC_EXIT(sc, ""); 1805 return ENETRESET; 1806 } 1807 1808 /* 1809 * Switch in 1810 */ 1811 sc->sc_flags |= GE_ALLMULTI; 1812 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1813 sc->sc_pcr |= ETH_EPCR_PM; 1814 GE_WRITE(sc, EPCR, sc->sc_pcr); 1815 GE_FUNC_EXIT(sc, ""); 1816 return 0; 1817 } 1818 GE_FUNC_EXIT(sc, ""); 1819 return ENETRESET; 1820 } 1821 1822 prio = GE_RXPRIO_MEDLO; 1823 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1824 1825 if (sc->sc_hashtable == NULL) { 1826 GE_FUNC_EXIT(sc, ""); 1827 return 0; 1828 } 1829 1830 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1831 if (error == EBUSY) { 1832 printf("%s: multichg: tried to %s %s again\n", 1833 sc->sc_dev.dv_xname, 1834 cmd == SIOCDELMULTI ? "remove" : "add", 1835 ether_sprintf(enm->enm_addrlo)); 1836 GE_FUNC_EXIT(sc, ""); 1837 return 0; 1838 } 1839 1840 if (error == ENOENT) { 1841 printf("%s: multichg: failed to remove %s: not in table\n", 1842 sc->sc_dev.dv_xname, 1843 ether_sprintf(enm->enm_addrlo)); 1844 GE_FUNC_EXIT(sc, ""); 1845 return 0; 1846 } 1847 1848 if (error == ENOSPC) { 1849 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1850 sc->sc_dev.dv_xname, 1851 ether_sprintf(enm->enm_addrlo)); 1852 GE_FUNC_EXIT(sc, ""); 1853 return ENETRESET; 1854 } 1855 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1856 sc->sc_dev.dv_xname, 1857 cmd == SIOCDELMULTI ? "remove" : "add", 1858 ether_sprintf(enm->enm_addrlo))); 1859 GE_FUNC_EXIT(sc, ""); 1860 return 0; 1861 } 1862 1863 int 1864 gfe_hash_fill(struct gfe_softc *sc) 1865 { 1866 struct ether_multistep step; 1867 struct ether_multi *enm; 1868 int error; 1869 1870 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1871 1872 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1873 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1874 if (error) 1875 GE_FUNC_EXIT(sc, "!"); 1876 return error; 1877 1878 sc->sc_flags &= ~GE_ALLMULTI; 1879 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1880 sc->sc_pcr &= ~ETH_EPCR_PM; 1881 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1882 while (enm != NULL) { 1883 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1884 sc->sc_flags |= GE_ALLMULTI; 1885 sc->sc_pcr |= ETH_EPCR_PM; 1886 } else { 1887 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1888 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1889 if (error == ENOSPC) 1890 break; 1891 } 1892 ETHER_NEXT_MULTI(step, enm); 1893 } 1894 1895 GE_FUNC_EXIT(sc, ""); 1896 return error; 1897 } 1898 1899 int 1900 gfe_hash_alloc(struct gfe_softc *sc) 1901 { 1902 int error; 1903 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1904 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1905 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1906 BUS_DMA_NOCACHE); 1907 if (error) { 1908 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1909 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1910 GE_FUNC_EXIT(sc, ""); 1911 return error; 1912 } 1913 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1914 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1915 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1916 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1917 GE_FUNC_EXIT(sc, ""); 1918 return 0; 1919 } 1920
Indexes created Tue Sep 30 07:10:03 GMT 2025