if_gfe.c revision 1.21
1 /* $NetBSD: if_gfe.c,v 1.21 2007/03/04 06:02:14 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.21 2007/03/04 06:02:14 christos Exp $"); 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/inttypes.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <sys/callout.h> 58 #include <sys/device.h> 59 #include <sys/errno.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/socket.h> 63 64 #include <machine/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/marvell/gtintrreg.h> 82 #include <dev/marvell/gtethreg.h> 83 84 #include <dev/marvell/gtvar.h> 85 #include <dev/marvell/if_gfevar.h> 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) do \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 while (0) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 STATIC int gfe_match (struct device *, struct cfdata *, void *); 148 STATIC void gfe_attach (struct device *, struct device *, void *); 149 150 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 151 size_t, int); 152 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 153 154 STATIC int gfe_ifioctl (struct ifnet *, u_long, void *); 155 STATIC void gfe_ifstart (struct ifnet *); 156 STATIC void gfe_ifwatchdog (struct ifnet *); 157 158 STATIC int gfe_mii_mediachange (struct ifnet *); 159 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 160 STATIC int gfe_mii_read (struct device *, int, int); 161 STATIC void gfe_mii_write (struct device *, int, int, int); 162 STATIC void gfe_mii_statchg (struct device *); 163 164 STATIC void gfe_tick(void *arg); 165 166 STATIC void gfe_tx_restart(void *); 167 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 168 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 169 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 170 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 171 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 172 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 173 174 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 175 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 176 STATIC int gfe_rx_prime(struct gfe_softc *); 177 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 178 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 179 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 180 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 181 182 STATIC int gfe_intr(void *); 183 184 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 185 186 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 187 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 188 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 189 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 190 u_long); 191 STATIC int gfe_hash_fill(struct gfe_softc *); 192 STATIC int gfe_hash_alloc(struct gfe_softc *); 193 194 /* Linkup to the rest of the kernel */ 195 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 196 gfe_match, gfe_attach, NULL, NULL); 197 198 extern struct cfdriver gfe_cd; 199 200 int 201 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 202 { 203 struct gt_softc *gt = (struct gt_softc *) parent; 204 struct gt_attach_args *ga = aux; 205 uint8_t enaddr[6]; 206 207 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 208 return 0; 209 210 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 211 return 0; 212 213 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 214 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 215 return 0; 216 217 return 1; 218 } 219 220 /* 221 * Attach this instance, and then all the sub-devices 222 */ 223 void 224 gfe_attach(struct device *parent, struct device *self, void *aux) 225 { 226 struct gt_attach_args * const ga = aux; 227 struct gt_softc * const gt = device_private(parent); 228 struct gfe_softc * const sc = device_private(self); 229 struct ifnet * const ifp = &sc->sc_ec.ec_if; 230 uint32_t data; 231 uint8_t enaddr[6]; 232 int phyaddr; 233 uint32_t sdcr; 234 int error; 235 236 GT_ETHERFOUND(gt, ga); 237 238 sc->sc_gt_memt = ga->ga_memt; 239 sc->sc_gt_memh = ga->ga_memh; 240 sc->sc_dmat = ga->ga_dmat; 241 sc->sc_macno = ga->ga_unit; 242 243 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 244 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 245 aprint_error(": failed to map registers\n"); 246 } 247 248 callout_init(&sc->sc_co); 249 250 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 251 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 252 253 gtget_macaddr(gt, sc->sc_macno, enaddr); 254 255 sc->sc_pcr = GE_READ(sc, EPCR); 256 sc->sc_pcxr = GE_READ(sc, EPCXR); 257 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 258 259 aprint_normal(": address %s", ether_sprintf(enaddr)); 260 261 #if defined(DEBUG) 262 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 263 #endif 264 265 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 266 if (device_cfdata(&sc->sc_dev)->cf_flags & 1) { 267 aprint_normal(", phy %d (rmii)", phyaddr); 268 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 269 } else { 270 aprint_normal(", phy %d (mii)", phyaddr); 271 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 272 } 273 if (device_cfdata(&sc->sc_dev)->cf_flags & 2) 274 sc->sc_flags |= GE_NOFREE; 275 sc->sc_pcxr &= ~(3 << 14); 276 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 277 278 if (sc->sc_pcr & ETH_EPCR_EN) { 279 int tries = 1000; 280 /* 281 * Abort transmitter and receiver and wait for them to quiese 282 */ 283 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 284 do { 285 delay(100); 286 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 287 } 288 289 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 290 291 #if defined(DEBUG) 292 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 293 #endif 294 295 /* 296 * Now turn off the GT. If it didn't quiese, too ***ing bad. 297 */ 298 GE_WRITE(sc, EPCR, sc->sc_pcr); 299 GE_WRITE(sc, EIMR, sc->sc_intrmask); 300 sdcr = GE_READ(sc, ESDCR); 301 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 302 sdcr |= ETH_ESDCR_RIFB; 303 GE_WRITE(sc, ESDCR, sdcr); 304 sc->sc_max_frame_length = 1536; 305 306 aprint_normal("\n"); 307 sc->sc_mii.mii_ifp = ifp; 308 sc->sc_mii.mii_readreg = gfe_mii_read; 309 sc->sc_mii.mii_writereg = gfe_mii_write; 310 sc->sc_mii.mii_statchg = gfe_mii_statchg; 311 312 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 313 gfe_mii_mediastatus); 314 315 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 316 MII_OFFSET_ANY, MIIF_NOISOLATE); 317 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 318 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 319 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 320 } else { 321 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 322 } 323 324 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 325 ifp->if_softc = sc; 326 /* ifp->if_mowner = &sc->sc_mowner; */ 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 #if 0 329 ifp->if_flags |= IFF_DEBUG; 330 #endif 331 ifp->if_ioctl = gfe_ifioctl; 332 ifp->if_start = gfe_ifstart; 333 ifp->if_watchdog = gfe_ifwatchdog; 334 335 if (sc->sc_flags & GE_NOFREE) { 336 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 337 if (!error) 338 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 339 if (!error) 340 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 341 if (!error) 342 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 343 if (!error) 344 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 345 if (!error) 346 error = gfe_hash_alloc(sc); 347 if (error) 348 aprint_error( 349 "%s: failed to allocate resources: %d\n", 350 ifp->if_xname, error); 351 } 352 353 if_attach(ifp); 354 ether_ifattach(ifp, enaddr); 355 #if NBPFILTER > 0 356 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 357 #endif 358 #if NRND > 0 359 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 360 #endif 361 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 362 gfe_intr, sc); 363 } 364 365 int 366 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 367 size_t size, int flags) 368 { 369 int error = 0; 370 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 371 372 KASSERT(gdm->gdm_kva == NULL); 373 gdm->gdm_size = size; 374 gdm->gdm_maxsegs = maxsegs; 375 376 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 377 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 378 BUS_DMA_NOWAIT); 379 if (error) 380 goto fail; 381 382 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 383 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 384 if (error) 385 goto fail; 386 387 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 388 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 389 if (error) 390 goto fail; 391 392 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 393 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 394 if (error) 395 goto fail; 396 397 /* invalidate from cache */ 398 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 399 BUS_DMASYNC_PREREAD); 400 fail: 401 if (error) { 402 gfe_dmamem_free(sc, gdm); 403 GE_DPRINTF(sc, (":err=%d", error)); 404 } 405 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 406 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 407 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 408 GE_FUNC_EXIT(sc, ""); 409 return error; 410 } 411 412 void 413 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 414 { 415 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 416 if (gdm->gdm_map) 417 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 418 if (gdm->gdm_kva) 419 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 420 if (gdm->gdm_nsegs > 0) 421 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 422 gdm->gdm_map = NULL; 423 gdm->gdm_kva = NULL; 424 gdm->gdm_nsegs = 0; 425 GE_FUNC_EXIT(sc, ""); 426 } 427 428 int 429 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 430 { 431 struct gfe_softc * const sc = ifp->if_softc; 432 struct ifreq *ifr = (struct ifreq *) data; 433 struct ifaddr *ifa = (struct ifaddr *) data; 434 int s, error = 0; 435 436 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 437 s = splnet(); 438 439 switch (cmd) { 440 case SIOCSIFADDR: 441 ifp->if_flags |= IFF_UP; 442 switch (ifa->ifa_addr->sa_family) { 443 #ifdef INET 444 case AF_INET: 445 error = gfe_whack(sc, GE_WHACK_START); 446 if (error == 0) 447 arp_ifinit(ifp, ifa); 448 break; 449 #endif 450 default: 451 error = gfe_whack(sc, GE_WHACK_START); 452 break; 453 } 454 break; 455 456 case SIOCSIFFLAGS: 457 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 458 case IFF_UP|IFF_RUNNING:/* active->active, update */ 459 error = gfe_whack(sc, GE_WHACK_CHANGE); 460 break; 461 case IFF_RUNNING: /* not up, so we stop */ 462 error = gfe_whack(sc, GE_WHACK_STOP); 463 break; 464 case IFF_UP: /* not running, so we start */ 465 error = gfe_whack(sc, GE_WHACK_START); 466 break; 467 case 0: /* idle->idle: do nothing */ 468 break; 469 } 470 break; 471 472 case SIOCADDMULTI: 473 case SIOCDELMULTI: 474 error = (cmd == SIOCADDMULTI) 475 ? ether_addmulti(ifr, &sc->sc_ec) 476 : ether_delmulti(ifr, &sc->sc_ec); 477 if (error == ENETRESET) { 478 if (ifp->if_flags & IFF_RUNNING) 479 error = gfe_whack(sc, GE_WHACK_CHANGE); 480 else 481 error = 0; 482 } 483 break; 484 485 case SIOCSIFMTU: 486 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 487 error = EINVAL; 488 break; 489 } 490 ifp->if_mtu = ifr->ifr_mtu; 491 break; 492 493 case SIOCSIFMEDIA: 494 case SIOCGIFMEDIA: 495 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 496 break; 497 498 default: 499 error = EINVAL; 500 break; 501 } 502 splx(s); 503 GE_FUNC_EXIT(sc, ""); 504 return error; 505 } 506 507 void 508 gfe_ifstart(struct ifnet *ifp) 509 { 510 struct gfe_softc * const sc = ifp->if_softc; 511 struct mbuf *m; 512 513 GE_FUNC_ENTER(sc, "gfe_ifstart"); 514 515 if ((ifp->if_flags & IFF_RUNNING) == 0) { 516 GE_FUNC_EXIT(sc, "$"); 517 return; 518 } 519 520 for (;;) { 521 IF_DEQUEUE(&ifp->if_snd, m); 522 if (m == NULL) { 523 ifp->if_flags &= ~IFF_OACTIVE; 524 GE_FUNC_EXIT(sc, ""); 525 return; 526 } 527 528 /* 529 * No space in the pending queue? try later. 530 */ 531 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 532 break; 533 534 /* 535 * Try to enqueue a mbuf to the device. If that fails, we 536 * can always try to map the next mbuf. 537 */ 538 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 539 GE_DPRINTF(sc, (">")); 540 #ifndef GE_NOTX 541 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 542 #endif 543 } 544 545 /* 546 * Attempt to queue the mbuf for send failed. 547 */ 548 IF_PREPEND(&ifp->if_snd, m); 549 ifp->if_flags |= IFF_OACTIVE; 550 GE_FUNC_EXIT(sc, "%%"); 551 } 552 553 void 554 gfe_ifwatchdog(struct ifnet *ifp) 555 { 556 struct gfe_softc * const sc = ifp->if_softc; 557 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 558 559 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 560 printf("%s: device timeout", sc->sc_dev.dv_xname); 561 if (ifp->if_flags & IFF_RUNNING) { 562 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 563 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 564 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 565 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 566 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 567 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 568 GE_READ(sc, EICR)); 569 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 570 GE_TXDPRESYNC(sc, txq, curtxdnum); 571 } 572 printf("\n"); 573 ifp->if_oerrors++; 574 (void) gfe_whack(sc, GE_WHACK_RESTART); 575 GE_FUNC_EXIT(sc, ""); 576 } 577 578 int 580 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 581 { 582 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 583 int error; 584 585 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 586 GE_DPRINTF(sc, ("(%d)", rxprio)); 587 588 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 589 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 590 if (error) { 591 GE_FUNC_EXIT(sc, "!!"); 592 return error; 593 } 594 595 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 596 GE_RXBUF_MEMSIZE, 0); 597 if (error) { 598 GE_FUNC_EXIT(sc, "!!!"); 599 return error; 600 } 601 GE_FUNC_EXIT(sc, ""); 602 return error; 603 } 604 605 int 606 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 607 { 608 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 609 volatile struct gt_eth_desc *rxd; 610 const bus_dma_segment_t *ds; 611 int idx; 612 bus_addr_t nxtaddr; 613 bus_size_t boff; 614 615 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 616 GE_DPRINTF(sc, ("(%d)", rxprio)); 617 618 if ((sc->sc_flags & GE_NOFREE) == 0) { 619 int error = gfe_rx_rxqalloc(sc, rxprio); 620 if (error) { 621 GE_FUNC_EXIT(sc, "!"); 622 return error; 623 } 624 } else { 625 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 626 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 627 } 628 629 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 630 631 rxq->rxq_descs = 632 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 633 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 634 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 635 rxq->rxq_fi = 0; 636 rxq->rxq_active = GE_RXDESC_MAX; 637 for (idx = 0, rxd = rxq->rxq_descs, 638 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 639 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 640 idx < GE_RXDESC_MAX; 641 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 642 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 643 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 644 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 645 /* 646 * update the nxtptr to point to the next txd. 647 */ 648 if (idx == GE_RXDESC_MAX - 1) 649 nxtaddr = rxq->rxq_desc_busaddr; 650 rxd->ed_nxtptr = htogt32(nxtaddr); 651 boff += GE_RXBUF_SIZE; 652 if (boff == ds->ds_len) { 653 ds++; 654 boff = 0; 655 } 656 } 657 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 658 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 659 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 660 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 661 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 662 BUS_DMASYNC_PREREAD); 663 664 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 665 switch (rxprio) { 666 case GE_RXPRIO_HI: 667 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 668 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 669 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 670 break; 671 case GE_RXPRIO_MEDHI: 672 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 673 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 674 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 675 break; 676 case GE_RXPRIO_MEDLO: 677 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 678 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 679 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 680 break; 681 case GE_RXPRIO_LO: 682 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 683 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 684 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 685 break; 686 } 687 GE_FUNC_EXIT(sc, ""); 688 return 0; 689 } 690 691 void 692 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 693 { 694 struct ifnet * const ifp = &sc->sc_ec.ec_if; 695 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 696 struct mbuf *m = rxq->rxq_curpkt; 697 698 GE_FUNC_ENTER(sc, "gfe_rx_get"); 699 GE_DPRINTF(sc, ("(%d)", rxprio)); 700 701 while (rxq->rxq_active > 0) { 702 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 703 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 704 const struct ether_header *eh; 705 unsigned int cmdsts; 706 size_t buflen; 707 708 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 709 cmdsts = gt32toh(rxd->ed_cmdsts); 710 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 711 rxq->rxq_cmdsts = cmdsts; 712 /* 713 * Sometimes the GE "forgets" to reset the ownership bit. 714 * But if the length has been rewritten, the packet is ours 715 * so pretend the O bit is set. 716 */ 717 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 718 if ((cmdsts & RX_CMD_O) && buflen == 0) { 719 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 720 break; 721 } 722 723 /* 724 * If this is not a single buffer packet with no errors 725 * or for some reason it's bigger than our frame size, 726 * ignore it and go to the next packet. 727 */ 728 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 729 (RX_CMD_F|RX_CMD_L) || 730 buflen > sc->sc_max_frame_length) { 731 GE_DPRINTF(sc, ("!")); 732 --rxq->rxq_active; 733 ifp->if_ipackets++; 734 ifp->if_ierrors++; 735 goto give_it_back; 736 } 737 738 /* CRC is included with the packet; trim it off. */ 739 buflen -= ETHER_CRC_LEN; 740 741 if (m == NULL) { 742 MGETHDR(m, M_DONTWAIT, MT_DATA); 743 if (m == NULL) { 744 GE_DPRINTF(sc, ("?")); 745 break; 746 } 747 } 748 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 749 MCLGET(m, M_DONTWAIT); 750 if ((m->m_flags & M_EXT) == 0) { 751 GE_DPRINTF(sc, ("?")); 752 break; 753 } 754 } 755 m->m_data += 2; 756 m->m_len = 0; 757 m->m_pkthdr.len = 0; 758 m->m_pkthdr.rcvif = ifp; 759 rxq->rxq_cmdsts = cmdsts; 760 --rxq->rxq_active; 761 762 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 763 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 764 765 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 766 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 767 m->m_len = buflen; 768 m->m_pkthdr.len = buflen; 769 770 ifp->if_ipackets++; 771 #if NBPFILTER > 0 772 if (ifp->if_bpf != NULL) 773 bpf_mtap(ifp->if_bpf, m); 774 #endif 775 776 eh = (const struct ether_header *) m->m_data; 777 if ((ifp->if_flags & IFF_PROMISC) || 778 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 779 (rxq->rxq_cmdsts & RX_STS_HE) || 780 (eh->ether_dhost[0] & 1) != 0 || 781 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 782 ETHER_ADDR_LEN) == 0) { 783 (*ifp->if_input)(ifp, m); 784 m = NULL; 785 GE_DPRINTF(sc, (">")); 786 } else { 787 m->m_len = 0; 788 m->m_pkthdr.len = 0; 789 GE_DPRINTF(sc, ("+")); 790 } 791 rxq->rxq_cmdsts = 0; 792 793 give_it_back: 794 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 795 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 796 #if 0 797 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 798 rxq->rxq_fi, 799 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 800 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 801 #endif 802 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 803 if (++rxq->rxq_fi == GE_RXDESC_MAX) 804 rxq->rxq_fi = 0; 805 rxq->rxq_active++; 806 } 807 rxq->rxq_curpkt = m; 808 GE_FUNC_EXIT(sc, ""); 809 } 810 811 uint32_t 812 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 813 { 814 struct ifnet * const ifp = &sc->sc_ec.ec_if; 815 struct gfe_rxqueue *rxq; 816 uint32_t rxbits; 817 #define RXPRIO_DECODER 0xffffaa50 818 GE_FUNC_ENTER(sc, "gfe_rx_process"); 819 820 rxbits = ETH_IR_RxBuffer_GET(cause); 821 while (rxbits) { 822 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 823 GE_DPRINTF(sc, ("%1x", rxbits)); 824 rxbits &= ~(1 << rxprio); 825 gfe_rx_get(sc, rxprio); 826 } 827 828 rxbits = ETH_IR_RxError_GET(cause); 829 while (rxbits) { 830 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 831 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 832 int idx; 833 rxbits &= ~(1 << rxprio); 834 rxq = &sc->sc_rxq[rxprio]; 835 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 836 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 837 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 838 sc->sc_tickflags |= GE_TICK_RX_RESTART; 839 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 840 } 841 ifp->if_ierrors++; 842 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 843 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 844 memset(masks, 0, sizeof(masks)); 845 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 846 0, rxq->rxq_desc_mem.gdm_size, 847 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 848 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 849 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 850 851 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 852 masks[idx/32] |= 1 << (idx & 31); 853 } 854 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 855 0, rxq->rxq_desc_mem.gdm_size, 856 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 857 #if defined(DEBUG) 858 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 859 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 860 rxq->rxq_cmdsts, masks[0], masks[1]); 861 #endif 862 } 863 if ((intrmask & ETH_IR_RxBits) == 0) 864 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 865 866 GE_FUNC_EXIT(sc, ""); 867 return intrmask; 868 } 869 870 int 871 gfe_rx_prime(struct gfe_softc *sc) 872 { 873 struct gfe_rxqueue *rxq; 874 int error; 875 876 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 877 878 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 879 if (error) 880 goto bail; 881 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 882 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 883 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 884 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 885 } 886 sc->sc_intrmask |= rxq->rxq_intrbits; 887 888 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 889 if (error) 890 goto bail; 891 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 892 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 893 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 894 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 895 sc->sc_intrmask |= rxq->rxq_intrbits; 896 } 897 898 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 899 if (error) 900 goto bail; 901 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 902 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 903 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 904 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 905 sc->sc_intrmask |= rxq->rxq_intrbits; 906 } 907 908 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 909 if (error) 910 goto bail; 911 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 912 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 913 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 914 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 915 sc->sc_intrmask |= rxq->rxq_intrbits; 916 } 917 918 bail: 919 GE_FUNC_EXIT(sc, ""); 920 return error; 921 } 922 923 void 924 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 925 { 926 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 927 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 928 if (rxq == NULL) { 929 GE_FUNC_EXIT(sc, ""); 930 return; 931 } 932 933 if (rxq->rxq_curpkt) 934 m_freem(rxq->rxq_curpkt); 935 if ((sc->sc_flags & GE_NOFREE) == 0) { 936 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 937 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 938 } 939 GE_FUNC_EXIT(sc, ""); 940 } 941 942 void 943 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 944 { 945 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 946 sc->sc_flags &= ~GE_RXACTIVE; 947 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 948 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 949 GE_WRITE(sc, EIMR, sc->sc_intrmask); 950 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 951 do { 952 delay(10); 953 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 954 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 955 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 956 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 957 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 958 GE_FUNC_EXIT(sc, ""); 959 } 960 961 void 963 gfe_tick(void *arg) 964 { 965 struct gfe_softc * const sc = arg; 966 uint32_t intrmask; 967 unsigned int tickflags; 968 int s; 969 970 GE_FUNC_ENTER(sc, "gfe_tick"); 971 972 s = splnet(); 973 974 tickflags = sc->sc_tickflags; 975 sc->sc_tickflags = 0; 976 intrmask = sc->sc_intrmask; 977 if (tickflags & GE_TICK_TX_IFSTART) 978 gfe_ifstart(&sc->sc_ec.ec_if); 979 if (tickflags & GE_TICK_RX_RESTART) { 980 intrmask |= sc->sc_idlemask; 981 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 982 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 983 rxq->rxq_fi = 0; 984 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 985 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 986 } 987 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 988 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 989 rxq->rxq_fi = 0; 990 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 991 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 992 } 993 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 994 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 995 rxq->rxq_fi = 0; 996 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 997 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 998 } 999 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 1000 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1001 rxq->rxq_fi = 0; 1002 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 1003 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 1004 } 1005 sc->sc_idlemask = 0; 1006 } 1007 if (intrmask != sc->sc_intrmask) { 1008 sc->sc_intrmask = intrmask; 1009 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1010 } 1011 gfe_intr(sc); 1012 splx(s); 1013 1014 GE_FUNC_EXIT(sc, ""); 1015 } 1016 1017 int 1018 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1019 { 1020 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1021 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1022 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1023 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1024 uint32_t intrmask = sc->sc_intrmask; 1025 size_t buflen; 1026 struct mbuf *m; 1027 1028 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1029 1030 /* 1031 * Anything in the pending queue to enqueue? if not, punt. Likewise 1032 * if the txq is not yet created. 1033 * otherwise grab its dmamap. 1034 */ 1035 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1036 GE_FUNC_EXIT(sc, "-"); 1037 return 0; 1038 } 1039 1040 /* 1041 * Have we [over]consumed our limit of descriptors? 1042 * Do we have enough free descriptors? 1043 */ 1044 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1045 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1046 uint32_t cmdsts; 1047 size_t pktlen; 1048 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1049 cmdsts = gt32toh(txd2->ed_cmdsts); 1050 if (cmdsts & TX_CMD_O) { 1051 int nextin; 1052 /* 1053 * Sometime the Discovery forgets to update the 1054 * last descriptor. See if we own the descriptor 1055 * after it (since we know we've turned that to 1056 * the discovery and if we owned it, the Discovery 1057 * gave it back). If we do, we know the Discovery 1058 * gave back this one but forgot to mark it as ours. 1059 */ 1060 nextin = txq->txq_fi + 1; 1061 if (nextin == GE_TXDESC_MAX) 1062 nextin = 0; 1063 GE_TXDPOSTSYNC(sc, txq, nextin); 1064 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1065 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1066 GE_TXDPRESYNC(sc, txq, nextin); 1067 GE_FUNC_EXIT(sc, "@"); 1068 return 0; 1069 } 1070 #ifdef DEBUG 1071 printf("%s: txenqueue: transmitter resynced at %d\n", 1072 sc->sc_dev.dv_xname, txq->txq_fi); 1073 #endif 1074 } 1075 if (++txq->txq_fi == GE_TXDESC_MAX) 1076 txq->txq_fi = 0; 1077 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1078 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1079 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1080 txq->txq_nactive--; 1081 1082 /* statistics */ 1083 ifp->if_opackets++; 1084 if (cmdsts & TX_STS_ES) 1085 ifp->if_oerrors++; 1086 GE_DPRINTF(sc, ("%%")); 1087 } 1088 1089 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1090 1091 /* 1092 * If this packet would wrap around the end of the buffer, reset back 1093 * to the beginning. 1094 */ 1095 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1096 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1097 txq->txq_outptr = 0; 1098 } 1099 1100 /* 1101 * Make sure the output packet doesn't run over the beginning of 1102 * what we've already given the GT. 1103 */ 1104 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1105 txq->txq_outptr + buflen > txq->txq_inptr) { 1106 intrmask |= txq->txq_intrbits & 1107 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1108 if (sc->sc_intrmask != intrmask) { 1109 sc->sc_intrmask = intrmask; 1110 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1111 } 1112 GE_FUNC_EXIT(sc, "#"); 1113 return 0; 1114 } 1115 1116 /* 1117 * The end-of-list descriptor we put on last time is the starting point 1118 * for this packet. The GT is supposed to terminate list processing on 1119 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1120 * must terminate the list. 1121 */ 1122 intrmask = sc->sc_intrmask; 1123 1124 m_copydata(m, 0, m->m_pkthdr.len, 1125 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1126 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1127 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1128 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1129 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1130 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1131 1132 /* 1133 * Request a buffer interrupt every 2/3 of the way thru the transmit 1134 * buffer. 1135 */ 1136 txq->txq_ei_gapcount += buflen; 1137 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1138 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1139 txq->txq_ei_gapcount = 0; 1140 } else { 1141 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1142 } 1143 #if 0 1144 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1145 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1146 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1147 #endif 1148 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1149 1150 txq->txq_outptr += buflen; 1151 /* 1152 * Tell the SDMA engine to "Fetch!" 1153 */ 1154 GE_WRITE(sc, ESDCMR, 1155 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1156 1157 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1158 1159 /* 1160 * Update the last out appropriately. 1161 */ 1162 txq->txq_nactive++; 1163 if (++txq->txq_lo == GE_TXDESC_MAX) 1164 txq->txq_lo = 0; 1165 1166 /* 1167 * Move mbuf from the pending queue to the snd queue. 1168 */ 1169 IF_DEQUEUE(&txq->txq_pendq, m); 1170 #if NBPFILTER > 0 1171 if (ifp->if_bpf != NULL) 1172 bpf_mtap(ifp->if_bpf, m); 1173 #endif 1174 m_freem(m); 1175 ifp->if_flags &= ~IFF_OACTIVE; 1176 1177 /* 1178 * Since we have put an item into the packet queue, we now want 1179 * an interrupt when the transmit queue finishes processing the 1180 * list. But only update the mask if needs changing. 1181 */ 1182 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1183 if (sc->sc_intrmask != intrmask) { 1184 sc->sc_intrmask = intrmask; 1185 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1186 } 1187 if (ifp->if_timer == 0) 1188 ifp->if_timer = 5; 1189 GE_FUNC_EXIT(sc, "*"); 1190 return 1; 1191 } 1192 1193 uint32_t 1194 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1195 { 1196 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1197 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1198 1199 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1200 1201 if (txq == NULL) { 1202 GE_FUNC_EXIT(sc, ""); 1203 return intrmask; 1204 } 1205 1206 while (txq->txq_nactive > 0) { 1207 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1208 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1209 uint32_t cmdsts; 1210 size_t pktlen; 1211 1212 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1213 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1214 int nextin; 1215 1216 if (txq->txq_nactive == 1) { 1217 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1218 GE_FUNC_EXIT(sc, ""); 1219 return intrmask; 1220 } 1221 /* 1222 * Sometimes the Discovery forgets to update the 1223 * ownership bit in the descriptor. See if we own the 1224 * descriptor after it (since we know we've turned 1225 * that to the Discovery and if we own it now then the 1226 * Discovery gave it back). If we do, we know the 1227 * Discovery gave back this one but forgot to mark it 1228 * as ours. 1229 */ 1230 nextin = txq->txq_fi + 1; 1231 if (nextin == GE_TXDESC_MAX) 1232 nextin = 0; 1233 GE_TXDPOSTSYNC(sc, txq, nextin); 1234 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1235 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1236 GE_TXDPRESYNC(sc, txq, nextin); 1237 GE_FUNC_EXIT(sc, ""); 1238 return intrmask; 1239 } 1240 #ifdef DEBUG 1241 printf("%s: txdone: transmitter resynced at %d\n", 1242 sc->sc_dev.dv_xname, txq->txq_fi); 1243 #endif 1244 } 1245 #if 0 1246 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1247 txq->txq_lo, 1248 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1249 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1250 #endif 1251 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1252 if (++txq->txq_fi == GE_TXDESC_MAX) 1253 txq->txq_fi = 0; 1254 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1255 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1256 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1257 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1258 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1259 1260 /* statistics */ 1261 ifp->if_opackets++; 1262 if (cmdsts & TX_STS_ES) 1263 ifp->if_oerrors++; 1264 1265 /* txd->ed_bufptr = 0; */ 1266 1267 ifp->if_timer = 5; 1268 --txq->txq_nactive; 1269 } 1270 if (txq->txq_nactive != 0) 1271 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1272 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1273 ifp->if_timer = 0; 1274 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1275 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1276 GE_FUNC_EXIT(sc, ""); 1277 return intrmask; 1278 } 1279 1280 int 1281 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1282 { 1283 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1284 int error; 1285 1286 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1287 1288 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1289 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1290 if (error) { 1291 GE_FUNC_EXIT(sc, ""); 1292 return error; 1293 } 1294 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1295 if (error) { 1296 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1297 GE_FUNC_EXIT(sc, ""); 1298 return error; 1299 } 1300 GE_FUNC_EXIT(sc, ""); 1301 return 0; 1302 } 1303 1304 int 1305 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1306 { 1307 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1308 volatile struct gt_eth_desc *txd; 1309 unsigned int i; 1310 bus_addr_t addr; 1311 1312 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1313 1314 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1315 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1316 1317 if (sc->sc_flags & GE_NOFREE) { 1318 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1319 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1320 } else { 1321 int error = gfe_tx_txqalloc(sc, txprio); 1322 if (error) { 1323 GE_FUNC_EXIT(sc, "!"); 1324 return error; 1325 } 1326 } 1327 1328 txq->txq_descs = 1329 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1330 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1331 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1332 1333 txq->txq_pendq.ifq_maxlen = 10; 1334 txq->txq_ei_gapcount = 0; 1335 txq->txq_nactive = 0; 1336 txq->txq_fi = 0; 1337 txq->txq_lo = 0; 1338 txq->txq_inptr = GE_TXBUF_SIZE; 1339 txq->txq_outptr = 0; 1340 for (i = 0, txd = txq->txq_descs, 1341 addr = txq->txq_desc_busaddr + sizeof(*txd); 1342 i < GE_TXDESC_MAX - 1; 1343 i++, txd++, addr += sizeof(*txd)) { 1344 /* 1345 * update the nxtptr to point to the next txd. 1346 */ 1347 txd->ed_cmdsts = 0; 1348 txd->ed_nxtptr = htogt32(addr); 1349 } 1350 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1351 htogt32(txq->txq_desc_busaddr); 1352 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1353 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1354 1355 switch (txprio) { 1356 case GE_TXPRIO_HI: 1357 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1358 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1359 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1360 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1361 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1362 break; 1363 1364 case GE_TXPRIO_LO: 1365 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1366 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1367 txq->txq_epsrbits = ETH_EPSR_TxLow; 1368 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1369 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1370 break; 1371 1372 case GE_TXPRIO_NONE: 1373 break; 1374 } 1375 #if 0 1376 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1377 gt_write(device_parent(&sc->sc_dev), txq->txq_ectdp, 1378 txq->txq_desc_busaddr); 1379 GE_DPRINTF(sc, (")")); 1380 #endif 1381 1382 /* 1383 * If we are restarting, there may be packets in the pending queue 1384 * waiting to be enqueued. Try enqueuing packets from both priority 1385 * queues until the pending queue is empty or there no room for them 1386 * on the device. 1387 */ 1388 while (gfe_tx_enqueue(sc, txprio)) 1389 continue; 1390 1391 GE_FUNC_EXIT(sc, ""); 1392 return 0; 1393 } 1394 1395 void 1396 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1397 { 1398 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1399 1400 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1401 if (txq == NULL) { 1402 GE_FUNC_EXIT(sc, ""); 1403 return; 1404 } 1405 1406 if (!flush) { 1407 GE_FUNC_EXIT(sc, ""); 1408 return; 1409 } 1410 1411 if ((sc->sc_flags & GE_NOFREE) == 0) { 1412 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1413 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1414 } 1415 GE_FUNC_EXIT(sc, "-F"); 1416 } 1417 1418 void 1419 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1420 { 1421 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1422 1423 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1424 1425 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1426 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1427 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1428 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1429 1430 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1431 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1432 1433 sc->sc_ec.ec_if.if_timer = 0; 1434 GE_FUNC_EXIT(sc, ""); 1435 } 1436 1437 int 1439 gfe_intr(void *arg) 1440 { 1441 struct gfe_softc * const sc = arg; 1442 uint32_t cause; 1443 uint32_t intrmask = sc->sc_intrmask; 1444 int claim = 0; 1445 int cnt; 1446 1447 GE_FUNC_ENTER(sc, "gfe_intr"); 1448 1449 for (cnt = 0; cnt < 4; cnt++) { 1450 if (sc->sc_intrmask != intrmask) { 1451 sc->sc_intrmask = intrmask; 1452 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1453 } 1454 cause = GE_READ(sc, EICR); 1455 cause &= sc->sc_intrmask; 1456 GE_DPRINTF(sc, (".%#x", cause)); 1457 if (cause == 0) 1458 break; 1459 1460 claim = 1; 1461 1462 GE_WRITE(sc, EICR, ~cause); 1463 #ifndef GE_NORX 1464 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1465 intrmask = gfe_rx_process(sc, cause, intrmask); 1466 #endif 1467 1468 #ifndef GE_NOTX 1469 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1470 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1471 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1472 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1473 #endif 1474 if (cause & ETH_IR_MIIPhySTC) { 1475 sc->sc_flags |= GE_PHYSTSCHG; 1476 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1477 } 1478 } 1479 1480 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1481 continue; 1482 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1483 continue; 1484 1485 GE_FUNC_EXIT(sc, ""); 1486 return claim; 1487 } 1488 1489 int 1491 gfe_mii_mediachange (struct ifnet *ifp) 1492 { 1493 struct gfe_softc *sc = ifp->if_softc; 1494 1495 if (ifp->if_flags & IFF_UP) 1496 mii_mediachg(&sc->sc_mii); 1497 1498 return (0); 1499 } 1500 void 1501 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1502 { 1503 struct gfe_softc *sc = ifp->if_softc; 1504 1505 if (sc->sc_flags & GE_PHYSTSCHG) { 1506 sc->sc_flags &= ~GE_PHYSTSCHG; 1507 mii_pollstat(&sc->sc_mii); 1508 } 1509 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1510 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1511 } 1512 1513 int 1514 gfe_mii_read (struct device *self, int phy, int reg) 1515 { 1516 return gt_mii_read(self, device_parent(self), phy, reg); 1517 } 1518 1519 void 1520 gfe_mii_write (struct device *self, int phy, int reg, int value) 1521 { 1522 gt_mii_write(self, device_parent(self), phy, reg, value); 1523 } 1524 1525 void 1526 gfe_mii_statchg (struct device *self) 1527 { 1528 /* struct gfe_softc *sc = device_private(self); */ 1529 /* do nothing? */ 1530 } 1531 1532 int 1534 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1535 { 1536 int error = 0; 1537 GE_FUNC_ENTER(sc, "gfe_whack"); 1538 1539 switch (op) { 1540 case GE_WHACK_RESTART: 1541 #ifndef GE_NOTX 1542 gfe_tx_stop(sc, op); 1543 #endif 1544 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1545 /* FALLTHROUGH */ 1546 case GE_WHACK_START: 1547 #ifndef GE_NOHASH 1548 if (error == 0 && sc->sc_hashtable == NULL) { 1549 error = gfe_hash_alloc(sc); 1550 if (error) 1551 break; 1552 } 1553 if (op != GE_WHACK_RESTART) 1554 gfe_hash_fill(sc); 1555 #endif 1556 #ifndef GE_NORX 1557 if (op != GE_WHACK_RESTART) { 1558 error = gfe_rx_prime(sc); 1559 if (error) 1560 break; 1561 } 1562 #endif 1563 #ifndef GE_NOTX 1564 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1565 if (error) 1566 break; 1567 #endif 1568 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1569 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1570 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1571 GE_WRITE(sc, EICR, 0); 1572 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1573 #ifndef GE_NOHASH 1574 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1575 #endif 1576 #ifndef GE_NORX 1577 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1578 sc->sc_flags |= GE_RXACTIVE; 1579 #endif 1580 /* FALLTHROUGH */ 1581 case GE_WHACK_CHANGE: 1582 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1583 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1584 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1585 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1586 gfe_ifstart(&sc->sc_ec.ec_if); 1587 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1588 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1589 GE_FUNC_EXIT(sc, ""); 1590 return error; 1591 case GE_WHACK_STOP: 1592 break; 1593 } 1594 1595 #ifdef GE_DEBUG 1596 if (error) 1597 GE_DPRINTF(sc, (" failed: %d\n", error)); 1598 #endif 1599 GE_WRITE(sc, EPCR, sc->sc_pcr); 1600 GE_WRITE(sc, EIMR, 0); 1601 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1602 #ifndef GE_NOTX 1603 gfe_tx_stop(sc, GE_WHACK_STOP); 1604 #endif 1605 #ifndef GE_NORX 1606 gfe_rx_stop(sc, GE_WHACK_STOP); 1607 #endif 1608 #ifndef GE_NOHASH 1609 if ((sc->sc_flags & GE_NOFREE) == 0) { 1610 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1611 sc->sc_hashtable = NULL; 1612 } 1613 #endif 1614 1615 GE_FUNC_EXIT(sc, ""); 1616 return error; 1617 } 1618 1619 int 1621 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1622 { 1623 uint32_t w0, add0, add1; 1624 uint32_t result; 1625 1626 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1627 add0 = ((uint32_t) eaddr[5] << 0) | 1628 ((uint32_t) eaddr[4] << 8) | 1629 ((uint32_t) eaddr[3] << 16); 1630 1631 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1632 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1633 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1634 1635 add1 = ((uint32_t) eaddr[2] << 0) | 1636 ((uint32_t) eaddr[1] << 8) | 1637 ((uint32_t) eaddr[0] << 16); 1638 1639 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1640 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1641 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1642 1643 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1644 /* 1645 * hashResult is the 15 bits Hash entry address. 1646 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1647 * MAC address, by nibble swapping in every byte (i.e MAC address 1648 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1649 */ 1650 1651 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1652 /* 1653 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1654 * 1655 * hashFunc0 calculates the hashResult in the following manner: 1656 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1657 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1658 */ 1659 result = (add0 & 3) | ((add0 >> 6) & ~3); 1660 result ^= (add0 >> 15) ^ (add1 >> 0); 1661 result &= 0x1ff; 1662 /* 1663 * hashResult[14:9] = ethernetADD[7:2] 1664 */ 1665 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1666 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1667 } else { 1668 #define TRIBITFLIP 073516240 /* yes its in octal */ 1669 /* 1670 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1671 * 1672 * hashFunc1 calculates the hashResult in the following manner: 1673 * hashResult[08:00] = ethernetADD[06:14] 1674 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1675 */ 1676 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1677 /* 1678 * Now bitswap those 9 bits 1679 */ 1680 result = 0; 1681 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1682 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1683 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1684 1685 /* 1686 * hashResult[14:09] = ethernetADD[00:05] 1687 */ 1688 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1689 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1690 GE_DPRINTF(sc, ("1(%#x)", result)); 1691 } 1692 GE_FUNC_EXIT(sc, ""); 1693 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1694 } 1695 1696 int 1697 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1698 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1699 { 1700 uint64_t he; 1701 uint64_t *maybe_he_p = NULL; 1702 int limit; 1703 int hash; 1704 int maybe_hash = 0; 1705 1706 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1707 1708 hash = gfe_hash_compute(sc, eaddr); 1709 1710 if (sc->sc_hashtable == NULL) { 1711 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1712 __LINE__); 1713 } 1714 1715 /* 1716 * Assume we are going to insert so create the hash entry we 1717 * are going to insert. We also use it to match entries we 1718 * will be removing. 1719 */ 1720 he = ((uint64_t) eaddr[5] << 43) | 1721 ((uint64_t) eaddr[4] << 35) | 1722 ((uint64_t) eaddr[3] << 27) | 1723 ((uint64_t) eaddr[2] << 19) | 1724 ((uint64_t) eaddr[1] << 11) | 1725 ((uint64_t) eaddr[0] << 3) | 1726 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1727 1728 /* 1729 * The GT will search upto 12 entries for a hit, so we must mimic that. 1730 */ 1731 hash &= sc->sc_hashmask / sizeof(he); 1732 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1733 /* 1734 * Does the GT wrap at the end, stop at the, or overrun the 1735 * end? Assume it wraps for now. Stash a copy of the 1736 * current hash entry. 1737 */ 1738 uint64_t *he_p = &sc->sc_hashtable[hash]; 1739 uint64_t thishe = *he_p; 1740 1741 /* 1742 * If the hash entry isn't valid, that break the chain. And 1743 * this entry a good candidate for reuse. 1744 */ 1745 if ((thishe & HSH_V) == 0) { 1746 maybe_he_p = he_p; 1747 break; 1748 } 1749 1750 /* 1751 * If the hash entry has the same address we are looking for 1752 * then ... if we are removing and the skip bit is set, its 1753 * already been removed. if are adding and the skip bit is 1754 * clear, then its already added. In either return EBUSY 1755 * indicating the op has already been done. Otherwise flip 1756 * the skip bit and return 0. 1757 */ 1758 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1759 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1760 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1761 return EBUSY; 1762 *he_p = thishe ^ HSH_S; 1763 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1764 hash * sizeof(he), sizeof(he), 1765 BUS_DMASYNC_PREWRITE); 1766 GE_FUNC_EXIT(sc, "^"); 1767 return 0; 1768 } 1769 1770 /* 1771 * If we haven't found a slot for the entry and this entry 1772 * is currently being skipped, return this entry. 1773 */ 1774 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1775 maybe_he_p = he_p; 1776 maybe_hash = hash; 1777 } 1778 1779 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1780 } 1781 1782 /* 1783 * If we got here, then there was no entry to remove. 1784 */ 1785 if (op == GE_HASH_REMOVE) { 1786 GE_FUNC_EXIT(sc, "?"); 1787 return ENOENT; 1788 } 1789 1790 /* 1791 * If we couldn't find a slot, return an error. 1792 */ 1793 if (maybe_he_p == NULL) { 1794 GE_FUNC_EXIT(sc, "!"); 1795 return ENOSPC; 1796 } 1797 1798 /* Update the entry. 1799 */ 1800 *maybe_he_p = he; 1801 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1802 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1803 GE_FUNC_EXIT(sc, "+"); 1804 return 0; 1805 } 1806 1807 int 1808 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1809 { 1810 struct gfe_softc * const sc = ec->ec_if.if_softc; 1811 int error; 1812 enum gfe_hash_op op; 1813 enum gfe_rxprio prio; 1814 1815 GE_FUNC_ENTER(sc, "hash_multichg"); 1816 /* 1817 * Is this a wildcard entry? If so and its being removed, recompute. 1818 */ 1819 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1820 if (cmd == SIOCDELMULTI) { 1821 GE_FUNC_EXIT(sc, ""); 1822 return ENETRESET; 1823 } 1824 1825 /* 1826 * Switch in 1827 */ 1828 sc->sc_flags |= GE_ALLMULTI; 1829 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1830 sc->sc_pcr |= ETH_EPCR_PM; 1831 GE_WRITE(sc, EPCR, sc->sc_pcr); 1832 GE_FUNC_EXIT(sc, ""); 1833 return 0; 1834 } 1835 GE_FUNC_EXIT(sc, ""); 1836 return ENETRESET; 1837 } 1838 1839 prio = GE_RXPRIO_MEDLO; 1840 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1841 1842 if (sc->sc_hashtable == NULL) { 1843 GE_FUNC_EXIT(sc, ""); 1844 return 0; 1845 } 1846 1847 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1848 if (error == EBUSY) { 1849 printf("%s: multichg: tried to %s %s again\n", 1850 sc->sc_dev.dv_xname, 1851 cmd == SIOCDELMULTI ? "remove" : "add", 1852 ether_sprintf(enm->enm_addrlo)); 1853 GE_FUNC_EXIT(sc, ""); 1854 return 0; 1855 } 1856 1857 if (error == ENOENT) { 1858 printf("%s: multichg: failed to remove %s: not in table\n", 1859 sc->sc_dev.dv_xname, 1860 ether_sprintf(enm->enm_addrlo)); 1861 GE_FUNC_EXIT(sc, ""); 1862 return 0; 1863 } 1864 1865 if (error == ENOSPC) { 1866 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1867 sc->sc_dev.dv_xname, 1868 ether_sprintf(enm->enm_addrlo)); 1869 GE_FUNC_EXIT(sc, ""); 1870 return ENETRESET; 1871 } 1872 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1873 sc->sc_dev.dv_xname, 1874 cmd == SIOCDELMULTI ? "remove" : "add", 1875 ether_sprintf(enm->enm_addrlo))); 1876 GE_FUNC_EXIT(sc, ""); 1877 return 0; 1878 } 1879 1880 int 1881 gfe_hash_fill(struct gfe_softc *sc) 1882 { 1883 struct ether_multistep step; 1884 struct ether_multi *enm; 1885 int error; 1886 1887 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1888 1889 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1890 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1891 if (error) 1892 GE_FUNC_EXIT(sc, "!"); 1893 return error; 1894 1895 sc->sc_flags &= ~GE_ALLMULTI; 1896 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1897 sc->sc_pcr &= ~ETH_EPCR_PM; 1898 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1899 while (enm != NULL) { 1900 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1901 sc->sc_flags |= GE_ALLMULTI; 1902 sc->sc_pcr |= ETH_EPCR_PM; 1903 } else { 1904 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1905 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1906 if (error == ENOSPC) 1907 break; 1908 } 1909 ETHER_NEXT_MULTI(step, enm); 1910 } 1911 1912 GE_FUNC_EXIT(sc, ""); 1913 return error; 1914 } 1915 1916 int 1917 gfe_hash_alloc(struct gfe_softc *sc) 1918 { 1919 int error; 1920 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1921 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1922 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1923 BUS_DMA_NOCACHE); 1924 if (error) { 1925 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1926 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1927 GE_FUNC_EXIT(sc, ""); 1928 return error; 1929 } 1930 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1931 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1932 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1933 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1934 GE_FUNC_EXIT(sc, ""); 1935 return 0; 1936 } 1937
Indexes created Tue Sep 30 11:09:46 GMT 2025