if_gfe.c revision 1.26
1 /* $NetBSD: if_gfe.c,v 1.26 2007/10/19 12:00:33 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.26 2007/10/19 12:00:33 ad Exp $"); 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/inttypes.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <sys/callout.h> 58 #include <sys/device.h> 59 #include <sys/errno.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/socket.h> 63 64 #include <sys/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/marvell/gtintrreg.h> 82 #include <dev/marvell/gtethreg.h> 83 84 #include <dev/marvell/gtvar.h> 85 #include <dev/marvell/if_gfevar.h> 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) do \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 while (0) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 STATIC int gfe_match (struct device *, struct cfdata *, void *); 148 STATIC void gfe_attach (struct device *, struct device *, void *); 149 150 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 151 size_t, int); 152 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 153 154 STATIC int gfe_ifioctl (struct ifnet *, u_long, void *); 155 STATIC void gfe_ifstart (struct ifnet *); 156 STATIC void gfe_ifwatchdog (struct ifnet *); 157 158 STATIC int gfe_mii_mediachange (struct ifnet *); 159 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 160 STATIC int gfe_mii_read (struct device *, int, int); 161 STATIC void gfe_mii_write (struct device *, int, int, int); 162 STATIC void gfe_mii_statchg (struct device *); 163 164 STATIC void gfe_tick(void *arg); 165 166 STATIC void gfe_tx_restart(void *); 167 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 168 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 169 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 170 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 171 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 172 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 173 174 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 175 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 176 STATIC int gfe_rx_prime(struct gfe_softc *); 177 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 178 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 179 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 180 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 181 182 STATIC int gfe_intr(void *); 183 184 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 185 186 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 187 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 188 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 189 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 190 u_long); 191 STATIC int gfe_hash_fill(struct gfe_softc *); 192 STATIC int gfe_hash_alloc(struct gfe_softc *); 193 194 /* Linkup to the rest of the kernel */ 195 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 196 gfe_match, gfe_attach, NULL, NULL); 197 198 extern struct cfdriver gfe_cd; 199 200 int 201 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 202 { 203 struct gt_softc *gt = (struct gt_softc *) parent; 204 struct gt_attach_args *ga = aux; 205 uint8_t enaddr[6]; 206 207 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 208 return 0; 209 210 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 211 return 0; 212 213 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 214 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 215 return 0; 216 217 return 1; 218 } 219 220 /* 221 * Attach this instance, and then all the sub-devices 222 */ 223 void 224 gfe_attach(struct device *parent, struct device *self, void *aux) 225 { 226 struct gt_attach_args * const ga = aux; 227 struct gt_softc * const gt = device_private(parent); 228 struct gfe_softc * const sc = device_private(self); 229 struct ifnet * const ifp = &sc->sc_ec.ec_if; 230 uint32_t data; 231 uint8_t enaddr[6]; 232 int phyaddr; 233 uint32_t sdcr; 234 int error; 235 236 GT_ETHERFOUND(gt, ga); 237 238 sc->sc_gt_memt = ga->ga_memt; 239 sc->sc_gt_memh = ga->ga_memh; 240 sc->sc_dmat = ga->ga_dmat; 241 sc->sc_macno = ga->ga_unit; 242 243 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 244 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 245 aprint_error(": failed to map registers\n"); 246 } 247 248 callout_init(&sc->sc_co, 0); 249 250 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 251 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 252 253 gtget_macaddr(gt, sc->sc_macno, enaddr); 254 255 sc->sc_pcr = GE_READ(sc, EPCR); 256 sc->sc_pcxr = GE_READ(sc, EPCXR); 257 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 258 259 aprint_normal(": address %s", ether_sprintf(enaddr)); 260 261 #if defined(DEBUG) 262 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 263 #endif 264 265 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 266 if (device_cfdata(&sc->sc_dev)->cf_flags & 1) { 267 aprint_normal(", phy %d (rmii)", phyaddr); 268 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 269 } else { 270 aprint_normal(", phy %d (mii)", phyaddr); 271 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 272 } 273 if (device_cfdata(&sc->sc_dev)->cf_flags & 2) 274 sc->sc_flags |= GE_NOFREE; 275 sc->sc_pcxr &= ~(3 << 14); 276 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 277 278 if (sc->sc_pcr & ETH_EPCR_EN) { 279 int tries = 1000; 280 /* 281 * Abort transmitter and receiver and wait for them to quiese 282 */ 283 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 284 do { 285 delay(100); 286 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 287 } 288 289 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 290 291 #if defined(DEBUG) 292 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 293 #endif 294 295 /* 296 * Now turn off the GT. If it didn't quiese, too ***ing bad. 297 */ 298 GE_WRITE(sc, EPCR, sc->sc_pcr); 299 GE_WRITE(sc, EIMR, sc->sc_intrmask); 300 sdcr = GE_READ(sc, ESDCR); 301 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 302 sdcr |= ETH_ESDCR_RIFB; 303 GE_WRITE(sc, ESDCR, sdcr); 304 sc->sc_max_frame_length = 1536; 305 306 aprint_normal("\n"); 307 sc->sc_mii.mii_ifp = ifp; 308 sc->sc_mii.mii_readreg = gfe_mii_read; 309 sc->sc_mii.mii_writereg = gfe_mii_write; 310 sc->sc_mii.mii_statchg = gfe_mii_statchg; 311 312 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 313 gfe_mii_mediastatus); 314 315 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 316 MII_OFFSET_ANY, MIIF_NOISOLATE); 317 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 318 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 319 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 320 } else { 321 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 322 } 323 324 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 325 ifp->if_softc = sc; 326 /* ifp->if_mowner = &sc->sc_mowner; */ 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 #if 0 329 ifp->if_flags |= IFF_DEBUG; 330 #endif 331 ifp->if_ioctl = gfe_ifioctl; 332 ifp->if_start = gfe_ifstart; 333 ifp->if_watchdog = gfe_ifwatchdog; 334 335 if (sc->sc_flags & GE_NOFREE) { 336 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 337 if (!error) 338 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 339 if (!error) 340 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 341 if (!error) 342 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 343 if (!error) 344 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 345 if (!error) 346 error = gfe_hash_alloc(sc); 347 if (error) 348 aprint_error( 349 "%s: failed to allocate resources: %d\n", 350 ifp->if_xname, error); 351 } 352 353 if_attach(ifp); 354 ether_ifattach(ifp, enaddr); 355 #if NBPFILTER > 0 356 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 357 #endif 358 #if NRND > 0 359 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 360 #endif 361 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 362 gfe_intr, sc); 363 } 364 365 int 366 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 367 size_t size, int flags) 368 { 369 int error = 0; 370 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 371 372 KASSERT(gdm->gdm_kva == NULL); 373 gdm->gdm_size = size; 374 gdm->gdm_maxsegs = maxsegs; 375 376 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 377 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 378 BUS_DMA_NOWAIT); 379 if (error) 380 goto fail; 381 382 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 383 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 384 if (error) 385 goto fail; 386 387 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 388 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 389 if (error) 390 goto fail; 391 392 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 393 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 394 if (error) 395 goto fail; 396 397 /* invalidate from cache */ 398 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 399 BUS_DMASYNC_PREREAD); 400 fail: 401 if (error) { 402 gfe_dmamem_free(sc, gdm); 403 GE_DPRINTF(sc, (":err=%d", error)); 404 } 405 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 406 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 407 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 408 GE_FUNC_EXIT(sc, ""); 409 return error; 410 } 411 412 void 413 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 414 { 415 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 416 if (gdm->gdm_map) 417 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 418 if (gdm->gdm_kva) 419 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 420 if (gdm->gdm_nsegs > 0) 421 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 422 gdm->gdm_map = NULL; 423 gdm->gdm_kva = NULL; 424 gdm->gdm_nsegs = 0; 425 GE_FUNC_EXIT(sc, ""); 426 } 427 428 int 429 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 430 { 431 struct gfe_softc * const sc = ifp->if_softc; 432 struct ifreq *ifr = (struct ifreq *) data; 433 struct ifaddr *ifa = (struct ifaddr *) data; 434 int s, error = 0; 435 436 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 437 s = splnet(); 438 439 switch (cmd) { 440 case SIOCSIFADDR: 441 ifp->if_flags |= IFF_UP; 442 switch (ifa->ifa_addr->sa_family) { 443 #ifdef INET 444 case AF_INET: 445 error = gfe_whack(sc, GE_WHACK_START); 446 if (error == 0) 447 arp_ifinit(ifp, ifa); 448 break; 449 #endif 450 default: 451 error = gfe_whack(sc, GE_WHACK_START); 452 break; 453 } 454 break; 455 456 case SIOCSIFFLAGS: 457 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 458 case IFF_UP|IFF_RUNNING:/* active->active, update */ 459 error = gfe_whack(sc, GE_WHACK_CHANGE); 460 break; 461 case IFF_RUNNING: /* not up, so we stop */ 462 error = gfe_whack(sc, GE_WHACK_STOP); 463 break; 464 case IFF_UP: /* not running, so we start */ 465 error = gfe_whack(sc, GE_WHACK_START); 466 break; 467 case 0: /* idle->idle: do nothing */ 468 break; 469 } 470 break; 471 472 case SIOCADDMULTI: 473 case SIOCDELMULTI: 474 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 475 if (ifp->if_flags & IFF_RUNNING) 476 error = gfe_whack(sc, GE_WHACK_CHANGE); 477 else 478 error = 0; 479 } 480 break; 481 482 case SIOCSIFMTU: 483 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 484 error = EINVAL; 485 break; 486 } 487 ifp->if_mtu = ifr->ifr_mtu; 488 break; 489 490 case SIOCSIFMEDIA: 491 case SIOCGIFMEDIA: 492 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 493 break; 494 495 default: 496 error = EINVAL; 497 break; 498 } 499 splx(s); 500 GE_FUNC_EXIT(sc, ""); 501 return error; 502 } 503 504 void 505 gfe_ifstart(struct ifnet *ifp) 506 { 507 struct gfe_softc * const sc = ifp->if_softc; 508 struct mbuf *m; 509 510 GE_FUNC_ENTER(sc, "gfe_ifstart"); 511 512 if ((ifp->if_flags & IFF_RUNNING) == 0) { 513 GE_FUNC_EXIT(sc, "$"); 514 return; 515 } 516 517 for (;;) { 518 IF_DEQUEUE(&ifp->if_snd, m); 519 if (m == NULL) { 520 ifp->if_flags &= ~IFF_OACTIVE; 521 GE_FUNC_EXIT(sc, ""); 522 return; 523 } 524 525 /* 526 * No space in the pending queue? try later. 527 */ 528 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 529 break; 530 531 /* 532 * Try to enqueue a mbuf to the device. If that fails, we 533 * can always try to map the next mbuf. 534 */ 535 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 536 GE_DPRINTF(sc, (">")); 537 #ifndef GE_NOTX 538 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 539 #endif 540 } 541 542 /* 543 * Attempt to queue the mbuf for send failed. 544 */ 545 IF_PREPEND(&ifp->if_snd, m); 546 ifp->if_flags |= IFF_OACTIVE; 547 GE_FUNC_EXIT(sc, "%%"); 548 } 549 550 void 551 gfe_ifwatchdog(struct ifnet *ifp) 552 { 553 struct gfe_softc * const sc = ifp->if_softc; 554 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 555 556 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 557 printf("%s: device timeout", sc->sc_dev.dv_xname); 558 if (ifp->if_flags & IFF_RUNNING) { 559 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 560 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 561 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 562 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 563 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 564 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 565 GE_READ(sc, EICR)); 566 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 567 GE_TXDPRESYNC(sc, txq, curtxdnum); 568 } 569 printf("\n"); 570 ifp->if_oerrors++; 571 (void) gfe_whack(sc, GE_WHACK_RESTART); 572 GE_FUNC_EXIT(sc, ""); 573 } 574 575 int 577 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 578 { 579 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 580 int error; 581 582 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 583 GE_DPRINTF(sc, ("(%d)", rxprio)); 584 585 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 586 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 587 if (error) { 588 GE_FUNC_EXIT(sc, "!!"); 589 return error; 590 } 591 592 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 593 GE_RXBUF_MEMSIZE, 0); 594 if (error) { 595 GE_FUNC_EXIT(sc, "!!!"); 596 return error; 597 } 598 GE_FUNC_EXIT(sc, ""); 599 return error; 600 } 601 602 int 603 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 604 { 605 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 606 volatile struct gt_eth_desc *rxd; 607 const bus_dma_segment_t *ds; 608 int idx; 609 bus_addr_t nxtaddr; 610 bus_size_t boff; 611 612 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 613 GE_DPRINTF(sc, ("(%d)", rxprio)); 614 615 if ((sc->sc_flags & GE_NOFREE) == 0) { 616 int error = gfe_rx_rxqalloc(sc, rxprio); 617 if (error) { 618 GE_FUNC_EXIT(sc, "!"); 619 return error; 620 } 621 } else { 622 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 623 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 624 } 625 626 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 627 628 rxq->rxq_descs = 629 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 630 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 631 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 632 rxq->rxq_fi = 0; 633 rxq->rxq_active = GE_RXDESC_MAX; 634 for (idx = 0, rxd = rxq->rxq_descs, 635 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 636 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 637 idx < GE_RXDESC_MAX; 638 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 639 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 640 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 641 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 642 /* 643 * update the nxtptr to point to the next txd. 644 */ 645 if (idx == GE_RXDESC_MAX - 1) 646 nxtaddr = rxq->rxq_desc_busaddr; 647 rxd->ed_nxtptr = htogt32(nxtaddr); 648 boff += GE_RXBUF_SIZE; 649 if (boff == ds->ds_len) { 650 ds++; 651 boff = 0; 652 } 653 } 654 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 655 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 656 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 657 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 658 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 659 BUS_DMASYNC_PREREAD); 660 661 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 662 switch (rxprio) { 663 case GE_RXPRIO_HI: 664 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 665 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 666 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 667 break; 668 case GE_RXPRIO_MEDHI: 669 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 670 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 671 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 672 break; 673 case GE_RXPRIO_MEDLO: 674 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 675 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 676 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 677 break; 678 case GE_RXPRIO_LO: 679 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 680 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 681 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 682 break; 683 } 684 GE_FUNC_EXIT(sc, ""); 685 return 0; 686 } 687 688 void 689 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 690 { 691 struct ifnet * const ifp = &sc->sc_ec.ec_if; 692 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 693 struct mbuf *m = rxq->rxq_curpkt; 694 695 GE_FUNC_ENTER(sc, "gfe_rx_get"); 696 GE_DPRINTF(sc, ("(%d)", rxprio)); 697 698 while (rxq->rxq_active > 0) { 699 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 700 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 701 const struct ether_header *eh; 702 unsigned int cmdsts; 703 size_t buflen; 704 705 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 706 cmdsts = gt32toh(rxd->ed_cmdsts); 707 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 708 rxq->rxq_cmdsts = cmdsts; 709 /* 710 * Sometimes the GE "forgets" to reset the ownership bit. 711 * But if the length has been rewritten, the packet is ours 712 * so pretend the O bit is set. 713 */ 714 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 715 if ((cmdsts & RX_CMD_O) && buflen == 0) { 716 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 717 break; 718 } 719 720 /* 721 * If this is not a single buffer packet with no errors 722 * or for some reason it's bigger than our frame size, 723 * ignore it and go to the next packet. 724 */ 725 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 726 (RX_CMD_F|RX_CMD_L) || 727 buflen > sc->sc_max_frame_length) { 728 GE_DPRINTF(sc, ("!")); 729 --rxq->rxq_active; 730 ifp->if_ipackets++; 731 ifp->if_ierrors++; 732 goto give_it_back; 733 } 734 735 /* CRC is included with the packet; trim it off. */ 736 buflen -= ETHER_CRC_LEN; 737 738 if (m == NULL) { 739 MGETHDR(m, M_DONTWAIT, MT_DATA); 740 if (m == NULL) { 741 GE_DPRINTF(sc, ("?")); 742 break; 743 } 744 } 745 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 746 MCLGET(m, M_DONTWAIT); 747 if ((m->m_flags & M_EXT) == 0) { 748 GE_DPRINTF(sc, ("?")); 749 break; 750 } 751 } 752 m->m_data += 2; 753 m->m_len = 0; 754 m->m_pkthdr.len = 0; 755 m->m_pkthdr.rcvif = ifp; 756 rxq->rxq_cmdsts = cmdsts; 757 --rxq->rxq_active; 758 759 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 760 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 761 762 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 763 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 764 m->m_len = buflen; 765 m->m_pkthdr.len = buflen; 766 767 ifp->if_ipackets++; 768 #if NBPFILTER > 0 769 if (ifp->if_bpf != NULL) 770 bpf_mtap(ifp->if_bpf, m); 771 #endif 772 773 eh = (const struct ether_header *) m->m_data; 774 if ((ifp->if_flags & IFF_PROMISC) || 775 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 776 (rxq->rxq_cmdsts & RX_STS_HE) || 777 (eh->ether_dhost[0] & 1) != 0 || 778 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 779 ETHER_ADDR_LEN) == 0) { 780 (*ifp->if_input)(ifp, m); 781 m = NULL; 782 GE_DPRINTF(sc, (">")); 783 } else { 784 m->m_len = 0; 785 m->m_pkthdr.len = 0; 786 GE_DPRINTF(sc, ("+")); 787 } 788 rxq->rxq_cmdsts = 0; 789 790 give_it_back: 791 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 792 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 793 #if 0 794 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 795 rxq->rxq_fi, 796 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 797 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 798 #endif 799 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 800 if (++rxq->rxq_fi == GE_RXDESC_MAX) 801 rxq->rxq_fi = 0; 802 rxq->rxq_active++; 803 } 804 rxq->rxq_curpkt = m; 805 GE_FUNC_EXIT(sc, ""); 806 } 807 808 uint32_t 809 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 810 { 811 struct ifnet * const ifp = &sc->sc_ec.ec_if; 812 struct gfe_rxqueue *rxq; 813 uint32_t rxbits; 814 #define RXPRIO_DECODER 0xffffaa50 815 GE_FUNC_ENTER(sc, "gfe_rx_process"); 816 817 rxbits = ETH_IR_RxBuffer_GET(cause); 818 while (rxbits) { 819 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 820 GE_DPRINTF(sc, ("%1x", rxbits)); 821 rxbits &= ~(1 << rxprio); 822 gfe_rx_get(sc, rxprio); 823 } 824 825 rxbits = ETH_IR_RxError_GET(cause); 826 while (rxbits) { 827 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 828 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 829 int idx; 830 rxbits &= ~(1 << rxprio); 831 rxq = &sc->sc_rxq[rxprio]; 832 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 833 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 834 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 835 sc->sc_tickflags |= GE_TICK_RX_RESTART; 836 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 837 } 838 ifp->if_ierrors++; 839 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 840 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 841 memset(masks, 0, sizeof(masks)); 842 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 843 0, rxq->rxq_desc_mem.gdm_size, 844 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 845 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 846 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 847 848 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 849 masks[idx/32] |= 1 << (idx & 31); 850 } 851 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 852 0, rxq->rxq_desc_mem.gdm_size, 853 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 854 #if defined(DEBUG) 855 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 856 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 857 rxq->rxq_cmdsts, masks[0], masks[1]); 858 #endif 859 } 860 if ((intrmask & ETH_IR_RxBits) == 0) 861 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 862 863 GE_FUNC_EXIT(sc, ""); 864 return intrmask; 865 } 866 867 int 868 gfe_rx_prime(struct gfe_softc *sc) 869 { 870 struct gfe_rxqueue *rxq; 871 int error; 872 873 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 874 875 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 876 if (error) 877 goto bail; 878 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 879 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 880 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 881 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 882 } 883 sc->sc_intrmask |= rxq->rxq_intrbits; 884 885 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 886 if (error) 887 goto bail; 888 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 889 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 890 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 891 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 892 sc->sc_intrmask |= rxq->rxq_intrbits; 893 } 894 895 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 896 if (error) 897 goto bail; 898 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 899 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 900 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 901 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 902 sc->sc_intrmask |= rxq->rxq_intrbits; 903 } 904 905 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 906 if (error) 907 goto bail; 908 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 909 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 910 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 911 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 912 sc->sc_intrmask |= rxq->rxq_intrbits; 913 } 914 915 bail: 916 GE_FUNC_EXIT(sc, ""); 917 return error; 918 } 919 920 void 921 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 922 { 923 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 924 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 925 if (rxq == NULL) { 926 GE_FUNC_EXIT(sc, ""); 927 return; 928 } 929 930 if (rxq->rxq_curpkt) 931 m_freem(rxq->rxq_curpkt); 932 if ((sc->sc_flags & GE_NOFREE) == 0) { 933 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 934 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 935 } 936 GE_FUNC_EXIT(sc, ""); 937 } 938 939 void 940 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 941 { 942 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 943 sc->sc_flags &= ~GE_RXACTIVE; 944 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 945 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 946 GE_WRITE(sc, EIMR, sc->sc_intrmask); 947 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 948 do { 949 delay(10); 950 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 951 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 952 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 953 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 954 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 955 GE_FUNC_EXIT(sc, ""); 956 } 957 958 void 960 gfe_tick(void *arg) 961 { 962 struct gfe_softc * const sc = arg; 963 uint32_t intrmask; 964 unsigned int tickflags; 965 int s; 966 967 GE_FUNC_ENTER(sc, "gfe_tick"); 968 969 s = splnet(); 970 971 tickflags = sc->sc_tickflags; 972 sc->sc_tickflags = 0; 973 intrmask = sc->sc_intrmask; 974 if (tickflags & GE_TICK_TX_IFSTART) 975 gfe_ifstart(&sc->sc_ec.ec_if); 976 if (tickflags & GE_TICK_RX_RESTART) { 977 intrmask |= sc->sc_idlemask; 978 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 979 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 980 rxq->rxq_fi = 0; 981 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 982 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 983 } 984 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 985 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 986 rxq->rxq_fi = 0; 987 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 988 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 989 } 990 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 991 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 992 rxq->rxq_fi = 0; 993 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 994 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 995 } 996 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 997 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 998 rxq->rxq_fi = 0; 999 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 1000 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 1001 } 1002 sc->sc_idlemask = 0; 1003 } 1004 if (intrmask != sc->sc_intrmask) { 1005 sc->sc_intrmask = intrmask; 1006 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1007 } 1008 gfe_intr(sc); 1009 splx(s); 1010 1011 GE_FUNC_EXIT(sc, ""); 1012 } 1013 1014 int 1015 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1016 { 1017 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1018 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1019 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1020 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1021 uint32_t intrmask = sc->sc_intrmask; 1022 size_t buflen; 1023 struct mbuf *m; 1024 1025 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1026 1027 /* 1028 * Anything in the pending queue to enqueue? if not, punt. Likewise 1029 * if the txq is not yet created. 1030 * otherwise grab its dmamap. 1031 */ 1032 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1033 GE_FUNC_EXIT(sc, "-"); 1034 return 0; 1035 } 1036 1037 /* 1038 * Have we [over]consumed our limit of descriptors? 1039 * Do we have enough free descriptors? 1040 */ 1041 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1042 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1043 uint32_t cmdsts; 1044 size_t pktlen; 1045 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1046 cmdsts = gt32toh(txd2->ed_cmdsts); 1047 if (cmdsts & TX_CMD_O) { 1048 int nextin; 1049 /* 1050 * Sometime the Discovery forgets to update the 1051 * last descriptor. See if we own the descriptor 1052 * after it (since we know we've turned that to 1053 * the discovery and if we owned it, the Discovery 1054 * gave it back). If we do, we know the Discovery 1055 * gave back this one but forgot to mark it as ours. 1056 */ 1057 nextin = txq->txq_fi + 1; 1058 if (nextin == GE_TXDESC_MAX) 1059 nextin = 0; 1060 GE_TXDPOSTSYNC(sc, txq, nextin); 1061 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1062 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1063 GE_TXDPRESYNC(sc, txq, nextin); 1064 GE_FUNC_EXIT(sc, "@"); 1065 return 0; 1066 } 1067 #ifdef DEBUG 1068 printf("%s: txenqueue: transmitter resynced at %d\n", 1069 sc->sc_dev.dv_xname, txq->txq_fi); 1070 #endif 1071 } 1072 if (++txq->txq_fi == GE_TXDESC_MAX) 1073 txq->txq_fi = 0; 1074 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1075 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1076 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1077 txq->txq_nactive--; 1078 1079 /* statistics */ 1080 ifp->if_opackets++; 1081 if (cmdsts & TX_STS_ES) 1082 ifp->if_oerrors++; 1083 GE_DPRINTF(sc, ("%%")); 1084 } 1085 1086 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1087 1088 /* 1089 * If this packet would wrap around the end of the buffer, reset back 1090 * to the beginning. 1091 */ 1092 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1093 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1094 txq->txq_outptr = 0; 1095 } 1096 1097 /* 1098 * Make sure the output packet doesn't run over the beginning of 1099 * what we've already given the GT. 1100 */ 1101 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1102 txq->txq_outptr + buflen > txq->txq_inptr) { 1103 intrmask |= txq->txq_intrbits & 1104 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1105 if (sc->sc_intrmask != intrmask) { 1106 sc->sc_intrmask = intrmask; 1107 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1108 } 1109 GE_FUNC_EXIT(sc, "#"); 1110 return 0; 1111 } 1112 1113 /* 1114 * The end-of-list descriptor we put on last time is the starting point 1115 * for this packet. The GT is supposed to terminate list processing on 1116 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1117 * must terminate the list. 1118 */ 1119 intrmask = sc->sc_intrmask; 1120 1121 m_copydata(m, 0, m->m_pkthdr.len, 1122 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1123 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1124 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1125 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1126 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1127 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1128 1129 /* 1130 * Request a buffer interrupt every 2/3 of the way thru the transmit 1131 * buffer. 1132 */ 1133 txq->txq_ei_gapcount += buflen; 1134 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1135 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1136 txq->txq_ei_gapcount = 0; 1137 } else { 1138 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1139 } 1140 #if 0 1141 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1142 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1143 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1144 #endif 1145 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1146 1147 txq->txq_outptr += buflen; 1148 /* 1149 * Tell the SDMA engine to "Fetch!" 1150 */ 1151 GE_WRITE(sc, ESDCMR, 1152 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1153 1154 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1155 1156 /* 1157 * Update the last out appropriately. 1158 */ 1159 txq->txq_nactive++; 1160 if (++txq->txq_lo == GE_TXDESC_MAX) 1161 txq->txq_lo = 0; 1162 1163 /* 1164 * Move mbuf from the pending queue to the snd queue. 1165 */ 1166 IF_DEQUEUE(&txq->txq_pendq, m); 1167 #if NBPFILTER > 0 1168 if (ifp->if_bpf != NULL) 1169 bpf_mtap(ifp->if_bpf, m); 1170 #endif 1171 m_freem(m); 1172 ifp->if_flags &= ~IFF_OACTIVE; 1173 1174 /* 1175 * Since we have put an item into the packet queue, we now want 1176 * an interrupt when the transmit queue finishes processing the 1177 * list. But only update the mask if needs changing. 1178 */ 1179 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1180 if (sc->sc_intrmask != intrmask) { 1181 sc->sc_intrmask = intrmask; 1182 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1183 } 1184 if (ifp->if_timer == 0) 1185 ifp->if_timer = 5; 1186 GE_FUNC_EXIT(sc, "*"); 1187 return 1; 1188 } 1189 1190 uint32_t 1191 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1192 { 1193 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1194 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1195 1196 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1197 1198 if (txq == NULL) { 1199 GE_FUNC_EXIT(sc, ""); 1200 return intrmask; 1201 } 1202 1203 while (txq->txq_nactive > 0) { 1204 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1205 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1206 uint32_t cmdsts; 1207 size_t pktlen; 1208 1209 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1210 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1211 int nextin; 1212 1213 if (txq->txq_nactive == 1) { 1214 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1215 GE_FUNC_EXIT(sc, ""); 1216 return intrmask; 1217 } 1218 /* 1219 * Sometimes the Discovery forgets to update the 1220 * ownership bit in the descriptor. See if we own the 1221 * descriptor after it (since we know we've turned 1222 * that to the Discovery and if we own it now then the 1223 * Discovery gave it back). If we do, we know the 1224 * Discovery gave back this one but forgot to mark it 1225 * as ours. 1226 */ 1227 nextin = txq->txq_fi + 1; 1228 if (nextin == GE_TXDESC_MAX) 1229 nextin = 0; 1230 GE_TXDPOSTSYNC(sc, txq, nextin); 1231 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1232 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1233 GE_TXDPRESYNC(sc, txq, nextin); 1234 GE_FUNC_EXIT(sc, ""); 1235 return intrmask; 1236 } 1237 #ifdef DEBUG 1238 printf("%s: txdone: transmitter resynced at %d\n", 1239 sc->sc_dev.dv_xname, txq->txq_fi); 1240 #endif 1241 } 1242 #if 0 1243 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1244 txq->txq_lo, 1245 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1246 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1247 #endif 1248 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1249 if (++txq->txq_fi == GE_TXDESC_MAX) 1250 txq->txq_fi = 0; 1251 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1252 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1253 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1254 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1255 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1256 1257 /* statistics */ 1258 ifp->if_opackets++; 1259 if (cmdsts & TX_STS_ES) 1260 ifp->if_oerrors++; 1261 1262 /* txd->ed_bufptr = 0; */ 1263 1264 ifp->if_timer = 5; 1265 --txq->txq_nactive; 1266 } 1267 if (txq->txq_nactive != 0) 1268 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1269 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1270 ifp->if_timer = 0; 1271 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1272 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1273 GE_FUNC_EXIT(sc, ""); 1274 return intrmask; 1275 } 1276 1277 int 1278 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1279 { 1280 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1281 int error; 1282 1283 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1284 1285 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1286 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1287 if (error) { 1288 GE_FUNC_EXIT(sc, ""); 1289 return error; 1290 } 1291 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1292 if (error) { 1293 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1294 GE_FUNC_EXIT(sc, ""); 1295 return error; 1296 } 1297 GE_FUNC_EXIT(sc, ""); 1298 return 0; 1299 } 1300 1301 int 1302 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1303 { 1304 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1305 volatile struct gt_eth_desc *txd; 1306 unsigned int i; 1307 bus_addr_t addr; 1308 1309 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1310 1311 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1312 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1313 1314 if (sc->sc_flags & GE_NOFREE) { 1315 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1316 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1317 } else { 1318 int error = gfe_tx_txqalloc(sc, txprio); 1319 if (error) { 1320 GE_FUNC_EXIT(sc, "!"); 1321 return error; 1322 } 1323 } 1324 1325 txq->txq_descs = 1326 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1327 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1328 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1329 1330 txq->txq_pendq.ifq_maxlen = 10; 1331 txq->txq_ei_gapcount = 0; 1332 txq->txq_nactive = 0; 1333 txq->txq_fi = 0; 1334 txq->txq_lo = 0; 1335 txq->txq_inptr = GE_TXBUF_SIZE; 1336 txq->txq_outptr = 0; 1337 for (i = 0, txd = txq->txq_descs, 1338 addr = txq->txq_desc_busaddr + sizeof(*txd); 1339 i < GE_TXDESC_MAX - 1; 1340 i++, txd++, addr += sizeof(*txd)) { 1341 /* 1342 * update the nxtptr to point to the next txd. 1343 */ 1344 txd->ed_cmdsts = 0; 1345 txd->ed_nxtptr = htogt32(addr); 1346 } 1347 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1348 htogt32(txq->txq_desc_busaddr); 1349 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1350 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1351 1352 switch (txprio) { 1353 case GE_TXPRIO_HI: 1354 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1355 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1356 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1357 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1358 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1359 break; 1360 1361 case GE_TXPRIO_LO: 1362 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1363 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1364 txq->txq_epsrbits = ETH_EPSR_TxLow; 1365 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1366 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1367 break; 1368 1369 case GE_TXPRIO_NONE: 1370 break; 1371 } 1372 #if 0 1373 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1374 gt_write(device_parent(&sc->sc_dev), txq->txq_ectdp, 1375 txq->txq_desc_busaddr); 1376 GE_DPRINTF(sc, (")")); 1377 #endif 1378 1379 /* 1380 * If we are restarting, there may be packets in the pending queue 1381 * waiting to be enqueued. Try enqueuing packets from both priority 1382 * queues until the pending queue is empty or there no room for them 1383 * on the device. 1384 */ 1385 while (gfe_tx_enqueue(sc, txprio)) 1386 continue; 1387 1388 GE_FUNC_EXIT(sc, ""); 1389 return 0; 1390 } 1391 1392 void 1393 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1394 { 1395 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1396 1397 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1398 if (txq == NULL) { 1399 GE_FUNC_EXIT(sc, ""); 1400 return; 1401 } 1402 1403 if (!flush) { 1404 GE_FUNC_EXIT(sc, ""); 1405 return; 1406 } 1407 1408 if ((sc->sc_flags & GE_NOFREE) == 0) { 1409 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1410 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1411 } 1412 GE_FUNC_EXIT(sc, "-F"); 1413 } 1414 1415 void 1416 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1417 { 1418 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1419 1420 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1421 1422 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1423 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1424 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1425 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1426 1427 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1428 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1429 1430 sc->sc_ec.ec_if.if_timer = 0; 1431 GE_FUNC_EXIT(sc, ""); 1432 } 1433 1434 int 1436 gfe_intr(void *arg) 1437 { 1438 struct gfe_softc * const sc = arg; 1439 uint32_t cause; 1440 uint32_t intrmask = sc->sc_intrmask; 1441 int claim = 0; 1442 int cnt; 1443 1444 GE_FUNC_ENTER(sc, "gfe_intr"); 1445 1446 for (cnt = 0; cnt < 4; cnt++) { 1447 if (sc->sc_intrmask != intrmask) { 1448 sc->sc_intrmask = intrmask; 1449 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1450 } 1451 cause = GE_READ(sc, EICR); 1452 cause &= sc->sc_intrmask; 1453 GE_DPRINTF(sc, (".%#x", cause)); 1454 if (cause == 0) 1455 break; 1456 1457 claim = 1; 1458 1459 GE_WRITE(sc, EICR, ~cause); 1460 #ifndef GE_NORX 1461 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1462 intrmask = gfe_rx_process(sc, cause, intrmask); 1463 #endif 1464 1465 #ifndef GE_NOTX 1466 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1467 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1468 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1469 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1470 #endif 1471 if (cause & ETH_IR_MIIPhySTC) { 1472 sc->sc_flags |= GE_PHYSTSCHG; 1473 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1474 } 1475 } 1476 1477 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1478 continue; 1479 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1480 continue; 1481 1482 GE_FUNC_EXIT(sc, ""); 1483 return claim; 1484 } 1485 1486 int 1488 gfe_mii_mediachange (struct ifnet *ifp) 1489 { 1490 struct gfe_softc *sc = ifp->if_softc; 1491 1492 if (ifp->if_flags & IFF_UP) 1493 mii_mediachg(&sc->sc_mii); 1494 1495 return (0); 1496 } 1497 void 1498 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1499 { 1500 struct gfe_softc *sc = ifp->if_softc; 1501 1502 if (sc->sc_flags & GE_PHYSTSCHG) { 1503 sc->sc_flags &= ~GE_PHYSTSCHG; 1504 mii_pollstat(&sc->sc_mii); 1505 } 1506 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1507 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1508 } 1509 1510 int 1511 gfe_mii_read (struct device *self, int phy, int reg) 1512 { 1513 return gt_mii_read(self, device_parent(self), phy, reg); 1514 } 1515 1516 void 1517 gfe_mii_write (struct device *self, int phy, int reg, int value) 1518 { 1519 gt_mii_write(self, device_parent(self), phy, reg, value); 1520 } 1521 1522 void 1523 gfe_mii_statchg (struct device *self) 1524 { 1525 /* struct gfe_softc *sc = device_private(self); */ 1526 /* do nothing? */ 1527 } 1528 1529 int 1531 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1532 { 1533 int error = 0; 1534 GE_FUNC_ENTER(sc, "gfe_whack"); 1535 1536 switch (op) { 1537 case GE_WHACK_RESTART: 1538 #ifndef GE_NOTX 1539 gfe_tx_stop(sc, op); 1540 #endif 1541 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1542 /* FALLTHROUGH */ 1543 case GE_WHACK_START: 1544 #ifndef GE_NOHASH 1545 if (error == 0 && sc->sc_hashtable == NULL) { 1546 error = gfe_hash_alloc(sc); 1547 if (error) 1548 break; 1549 } 1550 if (op != GE_WHACK_RESTART) 1551 gfe_hash_fill(sc); 1552 #endif 1553 #ifndef GE_NORX 1554 if (op != GE_WHACK_RESTART) { 1555 error = gfe_rx_prime(sc); 1556 if (error) 1557 break; 1558 } 1559 #endif 1560 #ifndef GE_NOTX 1561 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1562 if (error) 1563 break; 1564 #endif 1565 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1566 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1567 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1568 GE_WRITE(sc, EICR, 0); 1569 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1570 #ifndef GE_NOHASH 1571 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1572 #endif 1573 #ifndef GE_NORX 1574 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1575 sc->sc_flags |= GE_RXACTIVE; 1576 #endif 1577 /* FALLTHROUGH */ 1578 case GE_WHACK_CHANGE: 1579 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1580 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1581 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1582 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1583 gfe_ifstart(&sc->sc_ec.ec_if); 1584 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1585 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1586 GE_FUNC_EXIT(sc, ""); 1587 return error; 1588 case GE_WHACK_STOP: 1589 break; 1590 } 1591 1592 #ifdef GE_DEBUG 1593 if (error) 1594 GE_DPRINTF(sc, (" failed: %d\n", error)); 1595 #endif 1596 GE_WRITE(sc, EPCR, sc->sc_pcr); 1597 GE_WRITE(sc, EIMR, 0); 1598 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1599 #ifndef GE_NOTX 1600 gfe_tx_stop(sc, GE_WHACK_STOP); 1601 #endif 1602 #ifndef GE_NORX 1603 gfe_rx_stop(sc, GE_WHACK_STOP); 1604 #endif 1605 #ifndef GE_NOHASH 1606 if ((sc->sc_flags & GE_NOFREE) == 0) { 1607 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1608 sc->sc_hashtable = NULL; 1609 } 1610 #endif 1611 1612 GE_FUNC_EXIT(sc, ""); 1613 return error; 1614 } 1615 1616 int 1618 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1619 { 1620 uint32_t w0, add0, add1; 1621 uint32_t result; 1622 1623 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1624 add0 = ((uint32_t) eaddr[5] << 0) | 1625 ((uint32_t) eaddr[4] << 8) | 1626 ((uint32_t) eaddr[3] << 16); 1627 1628 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1629 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1630 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1631 1632 add1 = ((uint32_t) eaddr[2] << 0) | 1633 ((uint32_t) eaddr[1] << 8) | 1634 ((uint32_t) eaddr[0] << 16); 1635 1636 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1637 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1638 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1639 1640 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1641 /* 1642 * hashResult is the 15 bits Hash entry address. 1643 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1644 * MAC address, by nibble swapping in every byte (i.e MAC address 1645 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1646 */ 1647 1648 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1649 /* 1650 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1651 * 1652 * hashFunc0 calculates the hashResult in the following manner: 1653 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1654 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1655 */ 1656 result = (add0 & 3) | ((add0 >> 6) & ~3); 1657 result ^= (add0 >> 15) ^ (add1 >> 0); 1658 result &= 0x1ff; 1659 /* 1660 * hashResult[14:9] = ethernetADD[7:2] 1661 */ 1662 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1663 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1664 } else { 1665 #define TRIBITFLIP 073516240 /* yes its in octal */ 1666 /* 1667 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1668 * 1669 * hashFunc1 calculates the hashResult in the following manner: 1670 * hashResult[08:00] = ethernetADD[06:14] 1671 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1672 */ 1673 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1674 /* 1675 * Now bitswap those 9 bits 1676 */ 1677 result = 0; 1678 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1679 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1680 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1681 1682 /* 1683 * hashResult[14:09] = ethernetADD[00:05] 1684 */ 1685 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1686 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1687 GE_DPRINTF(sc, ("1(%#x)", result)); 1688 } 1689 GE_FUNC_EXIT(sc, ""); 1690 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1691 } 1692 1693 int 1694 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1695 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1696 { 1697 uint64_t he; 1698 uint64_t *maybe_he_p = NULL; 1699 int limit; 1700 int hash; 1701 int maybe_hash = 0; 1702 1703 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1704 1705 hash = gfe_hash_compute(sc, eaddr); 1706 1707 if (sc->sc_hashtable == NULL) { 1708 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1709 __LINE__); 1710 } 1711 1712 /* 1713 * Assume we are going to insert so create the hash entry we 1714 * are going to insert. We also use it to match entries we 1715 * will be removing. 1716 */ 1717 he = ((uint64_t) eaddr[5] << 43) | 1718 ((uint64_t) eaddr[4] << 35) | 1719 ((uint64_t) eaddr[3] << 27) | 1720 ((uint64_t) eaddr[2] << 19) | 1721 ((uint64_t) eaddr[1] << 11) | 1722 ((uint64_t) eaddr[0] << 3) | 1723 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1724 1725 /* 1726 * The GT will search upto 12 entries for a hit, so we must mimic that. 1727 */ 1728 hash &= sc->sc_hashmask / sizeof(he); 1729 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1730 /* 1731 * Does the GT wrap at the end, stop at the, or overrun the 1732 * end? Assume it wraps for now. Stash a copy of the 1733 * current hash entry. 1734 */ 1735 uint64_t *he_p = &sc->sc_hashtable[hash]; 1736 uint64_t thishe = *he_p; 1737 1738 /* 1739 * If the hash entry isn't valid, that break the chain. And 1740 * this entry a good candidate for reuse. 1741 */ 1742 if ((thishe & HSH_V) == 0) { 1743 maybe_he_p = he_p; 1744 break; 1745 } 1746 1747 /* 1748 * If the hash entry has the same address we are looking for 1749 * then ... if we are removing and the skip bit is set, its 1750 * already been removed. if are adding and the skip bit is 1751 * clear, then its already added. In either return EBUSY 1752 * indicating the op has already been done. Otherwise flip 1753 * the skip bit and return 0. 1754 */ 1755 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1756 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1757 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1758 return EBUSY; 1759 *he_p = thishe ^ HSH_S; 1760 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1761 hash * sizeof(he), sizeof(he), 1762 BUS_DMASYNC_PREWRITE); 1763 GE_FUNC_EXIT(sc, "^"); 1764 return 0; 1765 } 1766 1767 /* 1768 * If we haven't found a slot for the entry and this entry 1769 * is currently being skipped, return this entry. 1770 */ 1771 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1772 maybe_he_p = he_p; 1773 maybe_hash = hash; 1774 } 1775 1776 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1777 } 1778 1779 /* 1780 * If we got here, then there was no entry to remove. 1781 */ 1782 if (op == GE_HASH_REMOVE) { 1783 GE_FUNC_EXIT(sc, "?"); 1784 return ENOENT; 1785 } 1786 1787 /* 1788 * If we couldn't find a slot, return an error. 1789 */ 1790 if (maybe_he_p == NULL) { 1791 GE_FUNC_EXIT(sc, "!"); 1792 return ENOSPC; 1793 } 1794 1795 /* Update the entry. 1796 */ 1797 *maybe_he_p = he; 1798 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1799 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1800 GE_FUNC_EXIT(sc, "+"); 1801 return 0; 1802 } 1803 1804 int 1805 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1806 { 1807 struct gfe_softc * const sc = ec->ec_if.if_softc; 1808 int error; 1809 enum gfe_hash_op op; 1810 enum gfe_rxprio prio; 1811 1812 GE_FUNC_ENTER(sc, "hash_multichg"); 1813 /* 1814 * Is this a wildcard entry? If so and its being removed, recompute. 1815 */ 1816 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1817 if (cmd == SIOCDELMULTI) { 1818 GE_FUNC_EXIT(sc, ""); 1819 return ENETRESET; 1820 } 1821 1822 /* 1823 * Switch in 1824 */ 1825 sc->sc_flags |= GE_ALLMULTI; 1826 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1827 sc->sc_pcr |= ETH_EPCR_PM; 1828 GE_WRITE(sc, EPCR, sc->sc_pcr); 1829 GE_FUNC_EXIT(sc, ""); 1830 return 0; 1831 } 1832 GE_FUNC_EXIT(sc, ""); 1833 return ENETRESET; 1834 } 1835 1836 prio = GE_RXPRIO_MEDLO; 1837 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1838 1839 if (sc->sc_hashtable == NULL) { 1840 GE_FUNC_EXIT(sc, ""); 1841 return 0; 1842 } 1843 1844 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1845 if (error == EBUSY) { 1846 printf("%s: multichg: tried to %s %s again\n", 1847 sc->sc_dev.dv_xname, 1848 cmd == SIOCDELMULTI ? "remove" : "add", 1849 ether_sprintf(enm->enm_addrlo)); 1850 GE_FUNC_EXIT(sc, ""); 1851 return 0; 1852 } 1853 1854 if (error == ENOENT) { 1855 printf("%s: multichg: failed to remove %s: not in table\n", 1856 sc->sc_dev.dv_xname, 1857 ether_sprintf(enm->enm_addrlo)); 1858 GE_FUNC_EXIT(sc, ""); 1859 return 0; 1860 } 1861 1862 if (error == ENOSPC) { 1863 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1864 sc->sc_dev.dv_xname, 1865 ether_sprintf(enm->enm_addrlo)); 1866 GE_FUNC_EXIT(sc, ""); 1867 return ENETRESET; 1868 } 1869 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1870 sc->sc_dev.dv_xname, 1871 cmd == SIOCDELMULTI ? "remove" : "add", 1872 ether_sprintf(enm->enm_addrlo))); 1873 GE_FUNC_EXIT(sc, ""); 1874 return 0; 1875 } 1876 1877 int 1878 gfe_hash_fill(struct gfe_softc *sc) 1879 { 1880 struct ether_multistep step; 1881 struct ether_multi *enm; 1882 int error; 1883 1884 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1885 1886 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1887 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 1888 if (error) 1889 GE_FUNC_EXIT(sc, "!"); 1890 return error; 1891 1892 sc->sc_flags &= ~GE_ALLMULTI; 1893 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1894 sc->sc_pcr &= ~ETH_EPCR_PM; 1895 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1896 while (enm != NULL) { 1897 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1898 sc->sc_flags |= GE_ALLMULTI; 1899 sc->sc_pcr |= ETH_EPCR_PM; 1900 } else { 1901 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1902 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1903 if (error == ENOSPC) 1904 break; 1905 } 1906 ETHER_NEXT_MULTI(step, enm); 1907 } 1908 1909 GE_FUNC_EXIT(sc, ""); 1910 return error; 1911 } 1912 1913 int 1914 gfe_hash_alloc(struct gfe_softc *sc) 1915 { 1916 int error; 1917 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1918 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1919 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1920 BUS_DMA_NOCACHE); 1921 if (error) { 1922 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1923 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1924 GE_FUNC_EXIT(sc, ""); 1925 return error; 1926 } 1927 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1928 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1929 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1930 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1931 GE_FUNC_EXIT(sc, ""); 1932 return 0; 1933 } 1934
Indexes created Tue Sep 30 11:09:46 GMT 2025