if_gfe.c revision 1.27
1 /* $NetBSD: if_gfe.c,v 1.27 2008/01/19 22:10:18 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.27 2008/01/19 22:10:18 dyoung Exp $"); 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/inttypes.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <sys/callout.h> 58 #include <sys/device.h> 59 #include <sys/errno.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/socket.h> 63 64 #include <sys/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/marvell/gtintrreg.h> 82 #include <dev/marvell/gtethreg.h> 83 84 #include <dev/marvell/gtvar.h> 85 #include <dev/marvell/if_gfevar.h> 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) do \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 while (0) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 STATIC int gfe_match (struct device *, struct cfdata *, void *); 148 STATIC void gfe_attach (struct device *, struct device *, void *); 149 150 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 151 size_t, int); 152 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 153 154 STATIC int gfe_ifioctl (struct ifnet *, u_long, void *); 155 STATIC void gfe_ifstart (struct ifnet *); 156 STATIC void gfe_ifwatchdog (struct ifnet *); 157 158 STATIC int gfe_mii_read (struct device *, int, int); 159 STATIC void gfe_mii_write (struct device *, int, int, int); 160 STATIC void gfe_mii_statchg (struct device *); 161 162 STATIC void gfe_tick(void *arg); 163 164 STATIC void gfe_tx_restart(void *); 165 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 166 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 167 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 168 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 169 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 170 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 171 172 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 173 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 174 STATIC int gfe_rx_prime(struct gfe_softc *); 175 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 176 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 177 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 178 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 179 180 STATIC int gfe_intr(void *); 181 182 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 183 184 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 185 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 186 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 187 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 188 u_long); 189 STATIC int gfe_hash_fill(struct gfe_softc *); 190 STATIC int gfe_hash_alloc(struct gfe_softc *); 191 192 /* Linkup to the rest of the kernel */ 193 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 194 gfe_match, gfe_attach, NULL, NULL); 195 196 extern struct cfdriver gfe_cd; 197 198 int 199 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 200 { 201 struct gt_softc *gt = (struct gt_softc *) parent; 202 struct gt_attach_args *ga = aux; 203 uint8_t enaddr[6]; 204 205 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 206 return 0; 207 208 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 209 return 0; 210 211 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 212 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 213 return 0; 214 215 return 1; 216 } 217 218 /* 219 * Attach this instance, and then all the sub-devices 220 */ 221 void 222 gfe_attach(struct device *parent, struct device *self, void *aux) 223 { 224 struct gt_attach_args * const ga = aux; 225 struct gt_softc * const gt = device_private(parent); 226 struct gfe_softc * const sc = device_private(self); 227 struct ifnet * const ifp = &sc->sc_ec.ec_if; 228 uint32_t data; 229 uint8_t enaddr[6]; 230 int phyaddr; 231 uint32_t sdcr; 232 int error; 233 234 GT_ETHERFOUND(gt, ga); 235 236 sc->sc_gt_memt = ga->ga_memt; 237 sc->sc_gt_memh = ga->ga_memh; 238 sc->sc_dmat = ga->ga_dmat; 239 sc->sc_macno = ga->ga_unit; 240 241 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 242 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 243 aprint_error(": failed to map registers\n"); 244 } 245 246 callout_init(&sc->sc_co, 0); 247 248 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 249 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 250 251 gtget_macaddr(gt, sc->sc_macno, enaddr); 252 253 sc->sc_pcr = GE_READ(sc, EPCR); 254 sc->sc_pcxr = GE_READ(sc, EPCXR); 255 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 256 257 aprint_normal(": address %s", ether_sprintf(enaddr)); 258 259 #if defined(DEBUG) 260 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 261 #endif 262 263 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 264 if (device_cfdata(&sc->sc_dev)->cf_flags & 1) { 265 aprint_normal(", phy %d (rmii)", phyaddr); 266 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 267 } else { 268 aprint_normal(", phy %d (mii)", phyaddr); 269 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 270 } 271 if (device_cfdata(&sc->sc_dev)->cf_flags & 2) 272 sc->sc_flags |= GE_NOFREE; 273 sc->sc_pcxr &= ~(3 << 14); 274 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 275 276 if (sc->sc_pcr & ETH_EPCR_EN) { 277 int tries = 1000; 278 /* 279 * Abort transmitter and receiver and wait for them to quiese 280 */ 281 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 282 do { 283 delay(100); 284 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 285 } 286 287 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 288 289 #if defined(DEBUG) 290 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 291 #endif 292 293 /* 294 * Now turn off the GT. If it didn't quiese, too ***ing bad. 295 */ 296 GE_WRITE(sc, EPCR, sc->sc_pcr); 297 GE_WRITE(sc, EIMR, sc->sc_intrmask); 298 sdcr = GE_READ(sc, ESDCR); 299 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 300 sdcr |= ETH_ESDCR_RIFB; 301 GE_WRITE(sc, ESDCR, sdcr); 302 sc->sc_max_frame_length = 1536; 303 304 aprint_normal("\n"); 305 sc->sc_mii.mii_ifp = ifp; 306 sc->sc_mii.mii_readreg = gfe_mii_read; 307 sc->sc_mii.mii_writereg = gfe_mii_write; 308 sc->sc_mii.mii_statchg = gfe_mii_statchg; 309 310 sc->sc_ec.ec_mii = &sc->sc_mii; 311 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 312 ether_mediastatus); 313 314 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 315 MII_OFFSET_ANY, MIIF_NOISOLATE); 316 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 317 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 318 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 319 } else { 320 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 321 } 322 323 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 324 ifp->if_softc = sc; 325 /* ifp->if_mowner = &sc->sc_mowner; */ 326 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 327 #if 0 328 ifp->if_flags |= IFF_DEBUG; 329 #endif 330 ifp->if_ioctl = gfe_ifioctl; 331 ifp->if_start = gfe_ifstart; 332 ifp->if_watchdog = gfe_ifwatchdog; 333 334 if (sc->sc_flags & GE_NOFREE) { 335 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 336 if (!error) 337 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 338 if (!error) 339 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 340 if (!error) 341 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 342 if (!error) 343 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 344 if (!error) 345 error = gfe_hash_alloc(sc); 346 if (error) 347 aprint_error( 348 "%s: failed to allocate resources: %d\n", 349 ifp->if_xname, error); 350 } 351 352 if_attach(ifp); 353 ether_ifattach(ifp, enaddr); 354 #if NBPFILTER > 0 355 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 356 #endif 357 #if NRND > 0 358 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 359 #endif 360 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 361 gfe_intr, sc); 362 } 363 364 int 365 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 366 size_t size, int flags) 367 { 368 int error = 0; 369 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 370 371 KASSERT(gdm->gdm_kva == NULL); 372 gdm->gdm_size = size; 373 gdm->gdm_maxsegs = maxsegs; 374 375 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 376 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 377 BUS_DMA_NOWAIT); 378 if (error) 379 goto fail; 380 381 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 382 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 383 if (error) 384 goto fail; 385 386 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 387 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 388 if (error) 389 goto fail; 390 391 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 392 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 393 if (error) 394 goto fail; 395 396 /* invalidate from cache */ 397 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 398 BUS_DMASYNC_PREREAD); 399 fail: 400 if (error) { 401 gfe_dmamem_free(sc, gdm); 402 GE_DPRINTF(sc, (":err=%d", error)); 403 } 404 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 405 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 406 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 407 GE_FUNC_EXIT(sc, ""); 408 return error; 409 } 410 411 void 412 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 413 { 414 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 415 if (gdm->gdm_map) 416 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 417 if (gdm->gdm_kva) 418 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 419 if (gdm->gdm_nsegs > 0) 420 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 421 gdm->gdm_map = NULL; 422 gdm->gdm_kva = NULL; 423 gdm->gdm_nsegs = 0; 424 GE_FUNC_EXIT(sc, ""); 425 } 426 427 int 428 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 429 { 430 struct gfe_softc * const sc = ifp->if_softc; 431 struct ifreq *ifr = (struct ifreq *) data; 432 struct ifaddr *ifa = (struct ifaddr *) data; 433 int s, error = 0; 434 435 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 436 s = splnet(); 437 438 switch (cmd) { 439 case SIOCSIFADDR: 440 ifp->if_flags |= IFF_UP; 441 switch (ifa->ifa_addr->sa_family) { 442 #ifdef INET 443 case AF_INET: 444 error = gfe_whack(sc, GE_WHACK_START); 445 if (error == 0) 446 arp_ifinit(ifp, ifa); 447 break; 448 #endif 449 default: 450 error = gfe_whack(sc, GE_WHACK_START); 451 break; 452 } 453 break; 454 455 case SIOCSIFFLAGS: 456 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 457 case IFF_UP|IFF_RUNNING:/* active->active, update */ 458 error = gfe_whack(sc, GE_WHACK_CHANGE); 459 break; 460 case IFF_RUNNING: /* not up, so we stop */ 461 error = gfe_whack(sc, GE_WHACK_STOP); 462 break; 463 case IFF_UP: /* not running, so we start */ 464 error = gfe_whack(sc, GE_WHACK_START); 465 break; 466 case 0: /* idle->idle: do nothing */ 467 break; 468 } 469 break; 470 471 case SIOCSIFMEDIA: 472 case SIOCGIFMEDIA: 473 case SIOCADDMULTI: 474 case SIOCDELMULTI: 475 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 476 if (ifp->if_flags & IFF_RUNNING) 477 error = gfe_whack(sc, GE_WHACK_CHANGE); 478 else 479 error = 0; 480 } 481 break; 482 483 case SIOCSIFMTU: 484 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 485 error = EINVAL; 486 break; 487 } 488 ifp->if_mtu = ifr->ifr_mtu; 489 break; 490 491 default: 492 error = EINVAL; 493 break; 494 } 495 splx(s); 496 GE_FUNC_EXIT(sc, ""); 497 return error; 498 } 499 500 void 501 gfe_ifstart(struct ifnet *ifp) 502 { 503 struct gfe_softc * const sc = ifp->if_softc; 504 struct mbuf *m; 505 506 GE_FUNC_ENTER(sc, "gfe_ifstart"); 507 508 if ((ifp->if_flags & IFF_RUNNING) == 0) { 509 GE_FUNC_EXIT(sc, "$"); 510 return; 511 } 512 513 for (;;) { 514 IF_DEQUEUE(&ifp->if_snd, m); 515 if (m == NULL) { 516 ifp->if_flags &= ~IFF_OACTIVE; 517 GE_FUNC_EXIT(sc, ""); 518 return; 519 } 520 521 /* 522 * No space in the pending queue? try later. 523 */ 524 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 525 break; 526 527 /* 528 * Try to enqueue a mbuf to the device. If that fails, we 529 * can always try to map the next mbuf. 530 */ 531 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 532 GE_DPRINTF(sc, (">")); 533 #ifndef GE_NOTX 534 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 535 #endif 536 } 537 538 /* 539 * Attempt to queue the mbuf for send failed. 540 */ 541 IF_PREPEND(&ifp->if_snd, m); 542 ifp->if_flags |= IFF_OACTIVE; 543 GE_FUNC_EXIT(sc, "%%"); 544 } 545 546 void 547 gfe_ifwatchdog(struct ifnet *ifp) 548 { 549 struct gfe_softc * const sc = ifp->if_softc; 550 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 551 552 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 553 printf("%s: device timeout", sc->sc_dev.dv_xname); 554 if (ifp->if_flags & IFF_RUNNING) { 555 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 556 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 557 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 558 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 559 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 560 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 561 GE_READ(sc, EICR)); 562 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 563 GE_TXDPRESYNC(sc, txq, curtxdnum); 564 } 565 printf("\n"); 566 ifp->if_oerrors++; 567 (void) gfe_whack(sc, GE_WHACK_RESTART); 568 GE_FUNC_EXIT(sc, ""); 569 } 570 571 int 573 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 574 { 575 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 576 int error; 577 578 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 579 GE_DPRINTF(sc, ("(%d)", rxprio)); 580 581 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 582 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 583 if (error) { 584 GE_FUNC_EXIT(sc, "!!"); 585 return error; 586 } 587 588 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 589 GE_RXBUF_MEMSIZE, 0); 590 if (error) { 591 GE_FUNC_EXIT(sc, "!!!"); 592 return error; 593 } 594 GE_FUNC_EXIT(sc, ""); 595 return error; 596 } 597 598 int 599 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 600 { 601 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 602 volatile struct gt_eth_desc *rxd; 603 const bus_dma_segment_t *ds; 604 int idx; 605 bus_addr_t nxtaddr; 606 bus_size_t boff; 607 608 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 609 GE_DPRINTF(sc, ("(%d)", rxprio)); 610 611 if ((sc->sc_flags & GE_NOFREE) == 0) { 612 int error = gfe_rx_rxqalloc(sc, rxprio); 613 if (error) { 614 GE_FUNC_EXIT(sc, "!"); 615 return error; 616 } 617 } else { 618 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 619 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 620 } 621 622 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 623 624 rxq->rxq_descs = 625 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 626 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 627 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 628 rxq->rxq_fi = 0; 629 rxq->rxq_active = GE_RXDESC_MAX; 630 for (idx = 0, rxd = rxq->rxq_descs, 631 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 632 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 633 idx < GE_RXDESC_MAX; 634 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 635 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 636 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 637 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 638 /* 639 * update the nxtptr to point to the next txd. 640 */ 641 if (idx == GE_RXDESC_MAX - 1) 642 nxtaddr = rxq->rxq_desc_busaddr; 643 rxd->ed_nxtptr = htogt32(nxtaddr); 644 boff += GE_RXBUF_SIZE; 645 if (boff == ds->ds_len) { 646 ds++; 647 boff = 0; 648 } 649 } 650 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 651 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 652 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 653 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 654 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 655 BUS_DMASYNC_PREREAD); 656 657 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 658 switch (rxprio) { 659 case GE_RXPRIO_HI: 660 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 661 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 662 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 663 break; 664 case GE_RXPRIO_MEDHI: 665 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 666 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 667 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 668 break; 669 case GE_RXPRIO_MEDLO: 670 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 671 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 672 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 673 break; 674 case GE_RXPRIO_LO: 675 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 676 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 677 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 678 break; 679 } 680 GE_FUNC_EXIT(sc, ""); 681 return 0; 682 } 683 684 void 685 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 686 { 687 struct ifnet * const ifp = &sc->sc_ec.ec_if; 688 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 689 struct mbuf *m = rxq->rxq_curpkt; 690 691 GE_FUNC_ENTER(sc, "gfe_rx_get"); 692 GE_DPRINTF(sc, ("(%d)", rxprio)); 693 694 while (rxq->rxq_active > 0) { 695 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 696 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 697 const struct ether_header *eh; 698 unsigned int cmdsts; 699 size_t buflen; 700 701 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 702 cmdsts = gt32toh(rxd->ed_cmdsts); 703 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 704 rxq->rxq_cmdsts = cmdsts; 705 /* 706 * Sometimes the GE "forgets" to reset the ownership bit. 707 * But if the length has been rewritten, the packet is ours 708 * so pretend the O bit is set. 709 */ 710 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 711 if ((cmdsts & RX_CMD_O) && buflen == 0) { 712 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 713 break; 714 } 715 716 /* 717 * If this is not a single buffer packet with no errors 718 * or for some reason it's bigger than our frame size, 719 * ignore it and go to the next packet. 720 */ 721 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 722 (RX_CMD_F|RX_CMD_L) || 723 buflen > sc->sc_max_frame_length) { 724 GE_DPRINTF(sc, ("!")); 725 --rxq->rxq_active; 726 ifp->if_ipackets++; 727 ifp->if_ierrors++; 728 goto give_it_back; 729 } 730 731 /* CRC is included with the packet; trim it off. */ 732 buflen -= ETHER_CRC_LEN; 733 734 if (m == NULL) { 735 MGETHDR(m, M_DONTWAIT, MT_DATA); 736 if (m == NULL) { 737 GE_DPRINTF(sc, ("?")); 738 break; 739 } 740 } 741 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 742 MCLGET(m, M_DONTWAIT); 743 if ((m->m_flags & M_EXT) == 0) { 744 GE_DPRINTF(sc, ("?")); 745 break; 746 } 747 } 748 m->m_data += 2; 749 m->m_len = 0; 750 m->m_pkthdr.len = 0; 751 m->m_pkthdr.rcvif = ifp; 752 rxq->rxq_cmdsts = cmdsts; 753 --rxq->rxq_active; 754 755 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 756 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 757 758 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 759 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 760 m->m_len = buflen; 761 m->m_pkthdr.len = buflen; 762 763 ifp->if_ipackets++; 764 #if NBPFILTER > 0 765 if (ifp->if_bpf != NULL) 766 bpf_mtap(ifp->if_bpf, m); 767 #endif 768 769 eh = (const struct ether_header *) m->m_data; 770 if ((ifp->if_flags & IFF_PROMISC) || 771 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 772 (rxq->rxq_cmdsts & RX_STS_HE) || 773 (eh->ether_dhost[0] & 1) != 0 || 774 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 775 ETHER_ADDR_LEN) == 0) { 776 (*ifp->if_input)(ifp, m); 777 m = NULL; 778 GE_DPRINTF(sc, (">")); 779 } else { 780 m->m_len = 0; 781 m->m_pkthdr.len = 0; 782 GE_DPRINTF(sc, ("+")); 783 } 784 rxq->rxq_cmdsts = 0; 785 786 give_it_back: 787 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 788 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 789 #if 0 790 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 791 rxq->rxq_fi, 792 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 793 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 794 #endif 795 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 796 if (++rxq->rxq_fi == GE_RXDESC_MAX) 797 rxq->rxq_fi = 0; 798 rxq->rxq_active++; 799 } 800 rxq->rxq_curpkt = m; 801 GE_FUNC_EXIT(sc, ""); 802 } 803 804 uint32_t 805 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 806 { 807 struct ifnet * const ifp = &sc->sc_ec.ec_if; 808 struct gfe_rxqueue *rxq; 809 uint32_t rxbits; 810 #define RXPRIO_DECODER 0xffffaa50 811 GE_FUNC_ENTER(sc, "gfe_rx_process"); 812 813 rxbits = ETH_IR_RxBuffer_GET(cause); 814 while (rxbits) { 815 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 816 GE_DPRINTF(sc, ("%1x", rxbits)); 817 rxbits &= ~(1 << rxprio); 818 gfe_rx_get(sc, rxprio); 819 } 820 821 rxbits = ETH_IR_RxError_GET(cause); 822 while (rxbits) { 823 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 824 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 825 int idx; 826 rxbits &= ~(1 << rxprio); 827 rxq = &sc->sc_rxq[rxprio]; 828 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 829 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 830 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 831 sc->sc_tickflags |= GE_TICK_RX_RESTART; 832 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 833 } 834 ifp->if_ierrors++; 835 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 836 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 837 memset(masks, 0, sizeof(masks)); 838 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 839 0, rxq->rxq_desc_mem.gdm_size, 840 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 841 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 842 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 843 844 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 845 masks[idx/32] |= 1 << (idx & 31); 846 } 847 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 848 0, rxq->rxq_desc_mem.gdm_size, 849 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 850 #if defined(DEBUG) 851 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 852 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 853 rxq->rxq_cmdsts, masks[0], masks[1]); 854 #endif 855 } 856 if ((intrmask & ETH_IR_RxBits) == 0) 857 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 858 859 GE_FUNC_EXIT(sc, ""); 860 return intrmask; 861 } 862 863 int 864 gfe_rx_prime(struct gfe_softc *sc) 865 { 866 struct gfe_rxqueue *rxq; 867 int error; 868 869 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 870 871 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 872 if (error) 873 goto bail; 874 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 875 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 876 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 877 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 878 } 879 sc->sc_intrmask |= rxq->rxq_intrbits; 880 881 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 882 if (error) 883 goto bail; 884 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 885 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 886 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 887 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 888 sc->sc_intrmask |= rxq->rxq_intrbits; 889 } 890 891 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 892 if (error) 893 goto bail; 894 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 895 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 896 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 897 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 898 sc->sc_intrmask |= rxq->rxq_intrbits; 899 } 900 901 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 902 if (error) 903 goto bail; 904 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 905 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 906 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 907 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 908 sc->sc_intrmask |= rxq->rxq_intrbits; 909 } 910 911 bail: 912 GE_FUNC_EXIT(sc, ""); 913 return error; 914 } 915 916 void 917 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 918 { 919 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 920 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 921 if (rxq == NULL) { 922 GE_FUNC_EXIT(sc, ""); 923 return; 924 } 925 926 if (rxq->rxq_curpkt) 927 m_freem(rxq->rxq_curpkt); 928 if ((sc->sc_flags & GE_NOFREE) == 0) { 929 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 930 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 931 } 932 GE_FUNC_EXIT(sc, ""); 933 } 934 935 void 936 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 937 { 938 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 939 sc->sc_flags &= ~GE_RXACTIVE; 940 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 941 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 942 GE_WRITE(sc, EIMR, sc->sc_intrmask); 943 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 944 do { 945 delay(10); 946 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 947 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 948 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 949 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 950 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 951 GE_FUNC_EXIT(sc, ""); 952 } 953 954 void 956 gfe_tick(void *arg) 957 { 958 struct gfe_softc * const sc = arg; 959 uint32_t intrmask; 960 unsigned int tickflags; 961 int s; 962 963 GE_FUNC_ENTER(sc, "gfe_tick"); 964 965 s = splnet(); 966 967 tickflags = sc->sc_tickflags; 968 sc->sc_tickflags = 0; 969 intrmask = sc->sc_intrmask; 970 if (tickflags & GE_TICK_TX_IFSTART) 971 gfe_ifstart(&sc->sc_ec.ec_if); 972 if (tickflags & GE_TICK_RX_RESTART) { 973 intrmask |= sc->sc_idlemask; 974 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 975 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 976 rxq->rxq_fi = 0; 977 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 978 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 979 } 980 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 981 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 982 rxq->rxq_fi = 0; 983 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 984 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 985 } 986 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 987 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 988 rxq->rxq_fi = 0; 989 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 990 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 991 } 992 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 993 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 994 rxq->rxq_fi = 0; 995 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 996 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 997 } 998 sc->sc_idlemask = 0; 999 } 1000 if (intrmask != sc->sc_intrmask) { 1001 sc->sc_intrmask = intrmask; 1002 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1003 } 1004 gfe_intr(sc); 1005 splx(s); 1006 1007 GE_FUNC_EXIT(sc, ""); 1008 } 1009 1010 int 1011 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1012 { 1013 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1014 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1015 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1016 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1017 uint32_t intrmask = sc->sc_intrmask; 1018 size_t buflen; 1019 struct mbuf *m; 1020 1021 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1022 1023 /* 1024 * Anything in the pending queue to enqueue? if not, punt. Likewise 1025 * if the txq is not yet created. 1026 * otherwise grab its dmamap. 1027 */ 1028 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1029 GE_FUNC_EXIT(sc, "-"); 1030 return 0; 1031 } 1032 1033 /* 1034 * Have we [over]consumed our limit of descriptors? 1035 * Do we have enough free descriptors? 1036 */ 1037 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1038 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1039 uint32_t cmdsts; 1040 size_t pktlen; 1041 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1042 cmdsts = gt32toh(txd2->ed_cmdsts); 1043 if (cmdsts & TX_CMD_O) { 1044 int nextin; 1045 /* 1046 * Sometime the Discovery forgets to update the 1047 * last descriptor. See if we own the descriptor 1048 * after it (since we know we've turned that to 1049 * the discovery and if we owned it, the Discovery 1050 * gave it back). If we do, we know the Discovery 1051 * gave back this one but forgot to mark it as ours. 1052 */ 1053 nextin = txq->txq_fi + 1; 1054 if (nextin == GE_TXDESC_MAX) 1055 nextin = 0; 1056 GE_TXDPOSTSYNC(sc, txq, nextin); 1057 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1058 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1059 GE_TXDPRESYNC(sc, txq, nextin); 1060 GE_FUNC_EXIT(sc, "@"); 1061 return 0; 1062 } 1063 #ifdef DEBUG 1064 printf("%s: txenqueue: transmitter resynced at %d\n", 1065 sc->sc_dev.dv_xname, txq->txq_fi); 1066 #endif 1067 } 1068 if (++txq->txq_fi == GE_TXDESC_MAX) 1069 txq->txq_fi = 0; 1070 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1071 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1072 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1073 txq->txq_nactive--; 1074 1075 /* statistics */ 1076 ifp->if_opackets++; 1077 if (cmdsts & TX_STS_ES) 1078 ifp->if_oerrors++; 1079 GE_DPRINTF(sc, ("%%")); 1080 } 1081 1082 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1083 1084 /* 1085 * If this packet would wrap around the end of the buffer, reset back 1086 * to the beginning. 1087 */ 1088 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1089 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1090 txq->txq_outptr = 0; 1091 } 1092 1093 /* 1094 * Make sure the output packet doesn't run over the beginning of 1095 * what we've already given the GT. 1096 */ 1097 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1098 txq->txq_outptr + buflen > txq->txq_inptr) { 1099 intrmask |= txq->txq_intrbits & 1100 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1101 if (sc->sc_intrmask != intrmask) { 1102 sc->sc_intrmask = intrmask; 1103 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1104 } 1105 GE_FUNC_EXIT(sc, "#"); 1106 return 0; 1107 } 1108 1109 /* 1110 * The end-of-list descriptor we put on last time is the starting point 1111 * for this packet. The GT is supposed to terminate list processing on 1112 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1113 * must terminate the list. 1114 */ 1115 intrmask = sc->sc_intrmask; 1116 1117 m_copydata(m, 0, m->m_pkthdr.len, 1118 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1119 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1120 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1121 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1122 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1123 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1124 1125 /* 1126 * Request a buffer interrupt every 2/3 of the way thru the transmit 1127 * buffer. 1128 */ 1129 txq->txq_ei_gapcount += buflen; 1130 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1131 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1132 txq->txq_ei_gapcount = 0; 1133 } else { 1134 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1135 } 1136 #if 0 1137 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1138 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1139 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1140 #endif 1141 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1142 1143 txq->txq_outptr += buflen; 1144 /* 1145 * Tell the SDMA engine to "Fetch!" 1146 */ 1147 GE_WRITE(sc, ESDCMR, 1148 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1149 1150 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1151 1152 /* 1153 * Update the last out appropriately. 1154 */ 1155 txq->txq_nactive++; 1156 if (++txq->txq_lo == GE_TXDESC_MAX) 1157 txq->txq_lo = 0; 1158 1159 /* 1160 * Move mbuf from the pending queue to the snd queue. 1161 */ 1162 IF_DEQUEUE(&txq->txq_pendq, m); 1163 #if NBPFILTER > 0 1164 if (ifp->if_bpf != NULL) 1165 bpf_mtap(ifp->if_bpf, m); 1166 #endif 1167 m_freem(m); 1168 ifp->if_flags &= ~IFF_OACTIVE; 1169 1170 /* 1171 * Since we have put an item into the packet queue, we now want 1172 * an interrupt when the transmit queue finishes processing the 1173 * list. But only update the mask if needs changing. 1174 */ 1175 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1176 if (sc->sc_intrmask != intrmask) { 1177 sc->sc_intrmask = intrmask; 1178 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1179 } 1180 if (ifp->if_timer == 0) 1181 ifp->if_timer = 5; 1182 GE_FUNC_EXIT(sc, "*"); 1183 return 1; 1184 } 1185 1186 uint32_t 1187 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1188 { 1189 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1190 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1191 1192 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1193 1194 if (txq == NULL) { 1195 GE_FUNC_EXIT(sc, ""); 1196 return intrmask; 1197 } 1198 1199 while (txq->txq_nactive > 0) { 1200 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1201 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1202 uint32_t cmdsts; 1203 size_t pktlen; 1204 1205 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1206 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1207 int nextin; 1208 1209 if (txq->txq_nactive == 1) { 1210 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1211 GE_FUNC_EXIT(sc, ""); 1212 return intrmask; 1213 } 1214 /* 1215 * Sometimes the Discovery forgets to update the 1216 * ownership bit in the descriptor. See if we own the 1217 * descriptor after it (since we know we've turned 1218 * that to the Discovery and if we own it now then the 1219 * Discovery gave it back). If we do, we know the 1220 * Discovery gave back this one but forgot to mark it 1221 * as ours. 1222 */ 1223 nextin = txq->txq_fi + 1; 1224 if (nextin == GE_TXDESC_MAX) 1225 nextin = 0; 1226 GE_TXDPOSTSYNC(sc, txq, nextin); 1227 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1228 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1229 GE_TXDPRESYNC(sc, txq, nextin); 1230 GE_FUNC_EXIT(sc, ""); 1231 return intrmask; 1232 } 1233 #ifdef DEBUG 1234 printf("%s: txdone: transmitter resynced at %d\n", 1235 sc->sc_dev.dv_xname, txq->txq_fi); 1236 #endif 1237 } 1238 #if 0 1239 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1240 txq->txq_lo, 1241 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1242 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1243 #endif 1244 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1245 if (++txq->txq_fi == GE_TXDESC_MAX) 1246 txq->txq_fi = 0; 1247 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1248 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1249 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1250 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1251 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1252 1253 /* statistics */ 1254 ifp->if_opackets++; 1255 if (cmdsts & TX_STS_ES) 1256 ifp->if_oerrors++; 1257 1258 /* txd->ed_bufptr = 0; */ 1259 1260 ifp->if_timer = 5; 1261 --txq->txq_nactive; 1262 } 1263 if (txq->txq_nactive != 0) 1264 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1265 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1266 ifp->if_timer = 0; 1267 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1268 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1269 GE_FUNC_EXIT(sc, ""); 1270 return intrmask; 1271 } 1272 1273 int 1274 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1275 { 1276 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1277 int error; 1278 1279 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1280 1281 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1282 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1283 if (error) { 1284 GE_FUNC_EXIT(sc, ""); 1285 return error; 1286 } 1287 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1288 if (error) { 1289 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1290 GE_FUNC_EXIT(sc, ""); 1291 return error; 1292 } 1293 GE_FUNC_EXIT(sc, ""); 1294 return 0; 1295 } 1296 1297 int 1298 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1299 { 1300 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1301 volatile struct gt_eth_desc *txd; 1302 unsigned int i; 1303 bus_addr_t addr; 1304 1305 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1306 1307 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1308 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1309 1310 if (sc->sc_flags & GE_NOFREE) { 1311 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1312 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1313 } else { 1314 int error = gfe_tx_txqalloc(sc, txprio); 1315 if (error) { 1316 GE_FUNC_EXIT(sc, "!"); 1317 return error; 1318 } 1319 } 1320 1321 txq->txq_descs = 1322 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1323 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1324 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1325 1326 txq->txq_pendq.ifq_maxlen = 10; 1327 txq->txq_ei_gapcount = 0; 1328 txq->txq_nactive = 0; 1329 txq->txq_fi = 0; 1330 txq->txq_lo = 0; 1331 txq->txq_inptr = GE_TXBUF_SIZE; 1332 txq->txq_outptr = 0; 1333 for (i = 0, txd = txq->txq_descs, 1334 addr = txq->txq_desc_busaddr + sizeof(*txd); 1335 i < GE_TXDESC_MAX - 1; 1336 i++, txd++, addr += sizeof(*txd)) { 1337 /* 1338 * update the nxtptr to point to the next txd. 1339 */ 1340 txd->ed_cmdsts = 0; 1341 txd->ed_nxtptr = htogt32(addr); 1342 } 1343 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1344 htogt32(txq->txq_desc_busaddr); 1345 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1346 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1347 1348 switch (txprio) { 1349 case GE_TXPRIO_HI: 1350 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1351 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1352 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1353 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1354 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1355 break; 1356 1357 case GE_TXPRIO_LO: 1358 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1359 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1360 txq->txq_epsrbits = ETH_EPSR_TxLow; 1361 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1362 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1363 break; 1364 1365 case GE_TXPRIO_NONE: 1366 break; 1367 } 1368 #if 0 1369 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1370 gt_write(device_parent(&sc->sc_dev), txq->txq_ectdp, 1371 txq->txq_desc_busaddr); 1372 GE_DPRINTF(sc, (")")); 1373 #endif 1374 1375 /* 1376 * If we are restarting, there may be packets in the pending queue 1377 * waiting to be enqueued. Try enqueuing packets from both priority 1378 * queues until the pending queue is empty or there no room for them 1379 * on the device. 1380 */ 1381 while (gfe_tx_enqueue(sc, txprio)) 1382 continue; 1383 1384 GE_FUNC_EXIT(sc, ""); 1385 return 0; 1386 } 1387 1388 void 1389 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1390 { 1391 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1392 1393 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1394 if (txq == NULL) { 1395 GE_FUNC_EXIT(sc, ""); 1396 return; 1397 } 1398 1399 if (!flush) { 1400 GE_FUNC_EXIT(sc, ""); 1401 return; 1402 } 1403 1404 if ((sc->sc_flags & GE_NOFREE) == 0) { 1405 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1406 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1407 } 1408 GE_FUNC_EXIT(sc, "-F"); 1409 } 1410 1411 void 1412 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1413 { 1414 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1415 1416 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1417 1418 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1419 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1420 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1421 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1422 1423 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1424 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1425 1426 sc->sc_ec.ec_if.if_timer = 0; 1427 GE_FUNC_EXIT(sc, ""); 1428 } 1429 1430 int 1432 gfe_intr(void *arg) 1433 { 1434 struct gfe_softc * const sc = arg; 1435 uint32_t cause; 1436 uint32_t intrmask = sc->sc_intrmask; 1437 int claim = 0; 1438 int cnt; 1439 1440 GE_FUNC_ENTER(sc, "gfe_intr"); 1441 1442 for (cnt = 0; cnt < 4; cnt++) { 1443 if (sc->sc_intrmask != intrmask) { 1444 sc->sc_intrmask = intrmask; 1445 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1446 } 1447 cause = GE_READ(sc, EICR); 1448 cause &= sc->sc_intrmask; 1449 GE_DPRINTF(sc, (".%#x", cause)); 1450 if (cause == 0) 1451 break; 1452 1453 claim = 1; 1454 1455 GE_WRITE(sc, EICR, ~cause); 1456 #ifndef GE_NORX 1457 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1458 intrmask = gfe_rx_process(sc, cause, intrmask); 1459 #endif 1460 1461 #ifndef GE_NOTX 1462 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1463 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1464 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1465 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1466 #endif 1467 if (cause & ETH_IR_MIIPhySTC) { 1468 sc->sc_flags |= GE_PHYSTSCHG; 1469 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1470 } 1471 } 1472 1473 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1474 continue; 1475 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1476 continue; 1477 1478 GE_FUNC_EXIT(sc, ""); 1479 return claim; 1480 } 1481 1482 int 1484 gfe_mii_read (struct device *self, int phy, int reg) 1485 { 1486 return gt_mii_read(self, device_parent(self), phy, reg); 1487 } 1488 1489 void 1490 gfe_mii_write (struct device *self, int phy, int reg, int value) 1491 { 1492 gt_mii_write(self, device_parent(self), phy, reg, value); 1493 } 1494 1495 void 1496 gfe_mii_statchg (struct device *self) 1497 { 1498 /* struct gfe_softc *sc = device_private(self); */ 1499 /* do nothing? */ 1500 } 1501 1502 int 1504 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1505 { 1506 int error = 0; 1507 GE_FUNC_ENTER(sc, "gfe_whack"); 1508 1509 switch (op) { 1510 case GE_WHACK_RESTART: 1511 #ifndef GE_NOTX 1512 gfe_tx_stop(sc, op); 1513 #endif 1514 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1515 /* FALLTHROUGH */ 1516 case GE_WHACK_START: 1517 #ifndef GE_NOHASH 1518 if (error == 0 && sc->sc_hashtable == NULL) { 1519 error = gfe_hash_alloc(sc); 1520 if (error) 1521 break; 1522 } 1523 if (op != GE_WHACK_RESTART) 1524 gfe_hash_fill(sc); 1525 #endif 1526 #ifndef GE_NORX 1527 if (op != GE_WHACK_RESTART) { 1528 error = gfe_rx_prime(sc); 1529 if (error) 1530 break; 1531 } 1532 #endif 1533 #ifndef GE_NOTX 1534 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1535 if (error) 1536 break; 1537 #endif 1538 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1539 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1540 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1541 GE_WRITE(sc, EICR, 0); 1542 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1543 #ifndef GE_NOHASH 1544 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1545 #endif 1546 #ifndef GE_NORX 1547 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1548 sc->sc_flags |= GE_RXACTIVE; 1549 #endif 1550 /* FALLTHROUGH */ 1551 case GE_WHACK_CHANGE: 1552 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1553 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1554 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1555 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1556 gfe_ifstart(&sc->sc_ec.ec_if); 1557 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1558 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1559 GE_FUNC_EXIT(sc, ""); 1560 return error; 1561 case GE_WHACK_STOP: 1562 break; 1563 } 1564 1565 #ifdef GE_DEBUG 1566 if (error) 1567 GE_DPRINTF(sc, (" failed: %d\n", error)); 1568 #endif 1569 GE_WRITE(sc, EPCR, sc->sc_pcr); 1570 GE_WRITE(sc, EIMR, 0); 1571 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1572 #ifndef GE_NOTX 1573 gfe_tx_stop(sc, GE_WHACK_STOP); 1574 #endif 1575 #ifndef GE_NORX 1576 gfe_rx_stop(sc, GE_WHACK_STOP); 1577 #endif 1578 #ifndef GE_NOHASH 1579 if ((sc->sc_flags & GE_NOFREE) == 0) { 1580 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1581 sc->sc_hashtable = NULL; 1582 } 1583 #endif 1584 1585 GE_FUNC_EXIT(sc, ""); 1586 return error; 1587 } 1588 1589 int 1591 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1592 { 1593 uint32_t w0, add0, add1; 1594 uint32_t result; 1595 1596 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1597 add0 = ((uint32_t) eaddr[5] << 0) | 1598 ((uint32_t) eaddr[4] << 8) | 1599 ((uint32_t) eaddr[3] << 16); 1600 1601 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1602 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1603 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1604 1605 add1 = ((uint32_t) eaddr[2] << 0) | 1606 ((uint32_t) eaddr[1] << 8) | 1607 ((uint32_t) eaddr[0] << 16); 1608 1609 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1610 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1611 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1612 1613 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1614 /* 1615 * hashResult is the 15 bits Hash entry address. 1616 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1617 * MAC address, by nibble swapping in every byte (i.e MAC address 1618 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1619 */ 1620 1621 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1622 /* 1623 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1624 * 1625 * hashFunc0 calculates the hashResult in the following manner: 1626 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1627 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1628 */ 1629 result = (add0 & 3) | ((add0 >> 6) & ~3); 1630 result ^= (add0 >> 15) ^ (add1 >> 0); 1631 result &= 0x1ff; 1632 /* 1633 * hashResult[14:9] = ethernetADD[7:2] 1634 */ 1635 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1636 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1637 } else { 1638 #define TRIBITFLIP 073516240 /* yes its in octal */ 1639 /* 1640 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1641 * 1642 * hashFunc1 calculates the hashResult in the following manner: 1643 * hashResult[08:00] = ethernetADD[06:14] 1644 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1645 */ 1646 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1647 /* 1648 * Now bitswap those 9 bits 1649 */ 1650 result = 0; 1651 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1652 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1653 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1654 1655 /* 1656 * hashResult[14:09] = ethernetADD[00:05] 1657 */ 1658 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1659 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1660 GE_DPRINTF(sc, ("1(%#x)", result)); 1661 } 1662 GE_FUNC_EXIT(sc, ""); 1663 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1664 } 1665 1666 int 1667 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1668 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1669 { 1670 uint64_t he; 1671 uint64_t *maybe_he_p = NULL; 1672 int limit; 1673 int hash; 1674 int maybe_hash = 0; 1675 1676 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1677 1678 hash = gfe_hash_compute(sc, eaddr); 1679 1680 if (sc->sc_hashtable == NULL) { 1681 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1682 __LINE__); 1683 } 1684 1685 /* 1686 * Assume we are going to insert so create the hash entry we 1687 * are going to insert. We also use it to match entries we 1688 * will be removing. 1689 */ 1690 he = ((uint64_t) eaddr[5] << 43) | 1691 ((uint64_t) eaddr[4] << 35) | 1692 ((uint64_t) eaddr[3] << 27) | 1693 ((uint64_t) eaddr[2] << 19) | 1694 ((uint64_t) eaddr[1] << 11) | 1695 ((uint64_t) eaddr[0] << 3) | 1696 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1697 1698 /* 1699 * The GT will search upto 12 entries for a hit, so we must mimic that. 1700 */ 1701 hash &= sc->sc_hashmask / sizeof(he); 1702 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1703 /* 1704 * Does the GT wrap at the end, stop at the, or overrun the 1705 * end? Assume it wraps for now. Stash a copy of the 1706 * current hash entry. 1707 */ 1708 uint64_t *he_p = &sc->sc_hashtable[hash]; 1709 uint64_t thishe = *he_p; 1710 1711 /* 1712 * If the hash entry isn't valid, that break the chain. And 1713 * this entry a good candidate for reuse. 1714 */ 1715 if ((thishe & HSH_V) == 0) { 1716 maybe_he_p = he_p; 1717 break; 1718 } 1719 1720 /* 1721 * If the hash entry has the same address we are looking for 1722 * then ... if we are removing and the skip bit is set, its 1723 * already been removed. if are adding and the skip bit is 1724 * clear, then its already added. In either return EBUSY 1725 * indicating the op has already been done. Otherwise flip 1726 * the skip bit and return 0. 1727 */ 1728 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1729 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1730 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1731 return EBUSY; 1732 *he_p = thishe ^ HSH_S; 1733 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1734 hash * sizeof(he), sizeof(he), 1735 BUS_DMASYNC_PREWRITE); 1736 GE_FUNC_EXIT(sc, "^"); 1737 return 0; 1738 } 1739 1740 /* 1741 * If we haven't found a slot for the entry and this entry 1742 * is currently being skipped, return this entry. 1743 */ 1744 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1745 maybe_he_p = he_p; 1746 maybe_hash = hash; 1747 } 1748 1749 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1750 } 1751 1752 /* 1753 * If we got here, then there was no entry to remove. 1754 */ 1755 if (op == GE_HASH_REMOVE) { 1756 GE_FUNC_EXIT(sc, "?"); 1757 return ENOENT; 1758 } 1759 1760 /* 1761 * If we couldn't find a slot, return an error. 1762 */ 1763 if (maybe_he_p == NULL) { 1764 GE_FUNC_EXIT(sc, "!"); 1765 return ENOSPC; 1766 } 1767 1768 /* Update the entry. 1769 */ 1770 *maybe_he_p = he; 1771 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1772 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1773 GE_FUNC_EXIT(sc, "+"); 1774 return 0; 1775 } 1776 1777 int 1778 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1779 { 1780 struct gfe_softc * const sc = ec->ec_if.if_softc; 1781 int error; 1782 enum gfe_hash_op op; 1783 enum gfe_rxprio prio; 1784 1785 GE_FUNC_ENTER(sc, "hash_multichg"); 1786 /* 1787 * Is this a wildcard entry? If so and its being removed, recompute. 1788 */ 1789 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1790 if (cmd == SIOCDELMULTI) { 1791 GE_FUNC_EXIT(sc, ""); 1792 return ENETRESET; 1793 } 1794 1795 /* 1796 * Switch in 1797 */ 1798 sc->sc_flags |= GE_ALLMULTI; 1799 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1800 sc->sc_pcr |= ETH_EPCR_PM; 1801 GE_WRITE(sc, EPCR, sc->sc_pcr); 1802 GE_FUNC_EXIT(sc, ""); 1803 return 0; 1804 } 1805 GE_FUNC_EXIT(sc, ""); 1806 return ENETRESET; 1807 } 1808 1809 prio = GE_RXPRIO_MEDLO; 1810 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1811 1812 if (sc->sc_hashtable == NULL) { 1813 GE_FUNC_EXIT(sc, ""); 1814 return 0; 1815 } 1816 1817 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1818 if (error == EBUSY) { 1819 printf("%s: multichg: tried to %s %s again\n", 1820 sc->sc_dev.dv_xname, 1821 cmd == SIOCDELMULTI ? "remove" : "add", 1822 ether_sprintf(enm->enm_addrlo)); 1823 GE_FUNC_EXIT(sc, ""); 1824 return 0; 1825 } 1826 1827 if (error == ENOENT) { 1828 printf("%s: multichg: failed to remove %s: not in table\n", 1829 sc->sc_dev.dv_xname, 1830 ether_sprintf(enm->enm_addrlo)); 1831 GE_FUNC_EXIT(sc, ""); 1832 return 0; 1833 } 1834 1835 if (error == ENOSPC) { 1836 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1837 sc->sc_dev.dv_xname, 1838 ether_sprintf(enm->enm_addrlo)); 1839 GE_FUNC_EXIT(sc, ""); 1840 return ENETRESET; 1841 } 1842 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1843 sc->sc_dev.dv_xname, 1844 cmd == SIOCDELMULTI ? "remove" : "add", 1845 ether_sprintf(enm->enm_addrlo))); 1846 GE_FUNC_EXIT(sc, ""); 1847 return 0; 1848 } 1849 1850 int 1851 gfe_hash_fill(struct gfe_softc *sc) 1852 { 1853 struct ether_multistep step; 1854 struct ether_multi *enm; 1855 int error; 1856 1857 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1858 1859 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1860 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 1861 if (error) 1862 GE_FUNC_EXIT(sc, "!"); 1863 return error; 1864 1865 sc->sc_flags &= ~GE_ALLMULTI; 1866 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1867 sc->sc_pcr &= ~ETH_EPCR_PM; 1868 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1869 while (enm != NULL) { 1870 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1871 sc->sc_flags |= GE_ALLMULTI; 1872 sc->sc_pcr |= ETH_EPCR_PM; 1873 } else { 1874 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1875 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1876 if (error == ENOSPC) 1877 break; 1878 } 1879 ETHER_NEXT_MULTI(step, enm); 1880 } 1881 1882 GE_FUNC_EXIT(sc, ""); 1883 return error; 1884 } 1885 1886 int 1887 gfe_hash_alloc(struct gfe_softc *sc) 1888 { 1889 int error; 1890 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1891 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1892 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1893 BUS_DMA_NOCACHE); 1894 if (error) { 1895 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1896 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1897 GE_FUNC_EXIT(sc, ""); 1898 return error; 1899 } 1900 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1901 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1902 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1903 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1904 GE_FUNC_EXIT(sc, ""); 1905 return 0; 1906 } 1907
Indexes created Tue Sep 30 11:09:46 GMT 2025