if_gfe.c revision 1.29.4.3
1 /* $NetBSD: if_gfe.c,v 1.29.4.3 2010/03/11 15:03:40 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.29.4.3 2010/03/11 15:03:40 yamt Exp $"); 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/types.h> 51 #include <sys/inttypes.h> 52 #include <sys/queue.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/callout.h> 57 #include <sys/device.h> 58 #include <sys/errno.h> 59 #include <sys/ioctl.h> 60 #include <sys/mbuf.h> 61 #include <sys/socket.h> 62 63 #include <sys/bus.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_ether.h> 68 #include <net/if_media.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 #include <net/bpf.h> 75 76 #include <dev/mii/miivar.h> 77 78 #include <dev/marvell/gtintrreg.h> 79 #include <dev/marvell/gtethreg.h> 80 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/if_gfevar.h> 83 84 #define GE_READ(sc, reg) \ 85 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 86 #define GE_WRITE(sc, reg, v) \ 87 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 88 89 #define GE_DEBUG 90 #if 0 91 #define GE_NOHASH 92 #define GE_NORX 93 #endif 94 95 #ifdef GE_DEBUG 96 #define GE_DPRINTF(sc, a) do \ 97 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 98 printf a; \ 99 while (0) 100 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 101 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 102 #else 103 #define GE_DPRINTF(sc, a) do { } while (0) 104 #define GE_FUNC_ENTER(sc, func) do { } while (0) 105 #define GE_FUNC_EXIT(sc, str) do { } while (0) 106 #endif 107 enum gfe_whack_op { 108 GE_WHACK_START, GE_WHACK_RESTART, 109 GE_WHACK_CHANGE, GE_WHACK_STOP 110 }; 111 112 enum gfe_hash_op { 113 GE_HASH_ADD, GE_HASH_REMOVE, 114 }; 115 116 #if 1 117 #define htogt32(a) htobe32(a) 118 #define gt32toh(a) be32toh(a) 119 #else 120 #define htogt32(a) htole32(a) 121 #define gt32toh(a) le32toh(a) 122 #endif 123 124 #define GE_RXDSYNC(sc, rxq, n, ops) \ 125 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 126 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 127 (ops)) 128 #define GE_RXDPRESYNC(sc, rxq, n) \ 129 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 130 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 131 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 132 133 #define GE_TXDSYNC(sc, txq, n, ops) \ 134 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 135 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 136 (ops)) 137 #define GE_TXDPRESYNC(sc, txq, n) \ 138 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 139 #define GE_TXDPOSTSYNC(sc, txq, n) \ 140 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 141 142 #define STATIC 143 144 STATIC int gfe_match (device_t, cfdata_t, void *); 145 STATIC void gfe_attach (device_t, device_t, void *); 146 147 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 148 size_t, int); 149 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 150 151 STATIC int gfe_ifioctl (struct ifnet *, u_long, void *); 152 STATIC void gfe_ifstart (struct ifnet *); 153 STATIC void gfe_ifwatchdog (struct ifnet *); 154 155 STATIC int gfe_mii_read (device_t, int, int); 156 STATIC void gfe_mii_write (device_t, int, int, int); 157 STATIC void gfe_mii_statchg (device_t); 158 159 STATIC void gfe_tick(void *arg); 160 161 STATIC void gfe_tx_restart(void *); 162 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 163 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 164 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 165 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 166 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 167 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 168 169 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 170 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 171 STATIC int gfe_rx_prime(struct gfe_softc *); 172 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 173 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 174 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 175 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 176 177 STATIC int gfe_intr(void *); 178 179 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 180 181 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 182 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 183 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 184 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 185 u_long); 186 STATIC int gfe_hash_fill(struct gfe_softc *); 187 STATIC int gfe_hash_alloc(struct gfe_softc *); 188 189 /* Linkup to the rest of the kernel */ 190 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 191 gfe_match, gfe_attach, NULL, NULL); 192 193 extern struct cfdriver gfe_cd; 194 195 int 196 gfe_match(device_t parent, cfdata_t cf, void *aux) 197 { 198 struct gt_softc *gt = (struct gt_softc *) parent; 199 struct gt_attach_args *ga = aux; 200 uint8_t enaddr[6]; 201 202 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 203 return 0; 204 205 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 206 return 0; 207 208 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 209 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 210 return 0; 211 212 return 1; 213 } 214 215 /* 216 * Attach this instance, and then all the sub-devices 217 */ 218 void 219 gfe_attach(device_t parent, device_t self, void *aux) 220 { 221 struct gt_attach_args * const ga = aux; 222 struct gt_softc * const gt = device_private(parent); 223 struct gfe_softc * const sc = device_private(self); 224 struct ifnet * const ifp = &sc->sc_ec.ec_if; 225 uint32_t data; 226 uint8_t enaddr[6]; 227 int phyaddr; 228 uint32_t sdcr; 229 int error; 230 231 GT_ETHERFOUND(gt, ga); 232 233 sc->sc_gt_memt = ga->ga_memt; 234 sc->sc_gt_memh = ga->ga_memh; 235 sc->sc_dmat = ga->ga_dmat; 236 sc->sc_macno = ga->ga_unit; 237 238 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 239 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 240 aprint_error(": failed to map registers\n"); 241 } 242 243 callout_init(&sc->sc_co, 0); 244 245 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 246 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 247 248 gtget_macaddr(gt, sc->sc_macno, enaddr); 249 250 sc->sc_pcr = GE_READ(sc, EPCR); 251 sc->sc_pcxr = GE_READ(sc, EPCXR); 252 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 253 254 aprint_normal(": address %s", ether_sprintf(enaddr)); 255 256 #if defined(DEBUG) 257 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 258 #endif 259 260 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 261 if (device_cfdata(&sc->sc_dev)->cf_flags & 1) { 262 aprint_normal(", phy %d (rmii)", phyaddr); 263 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 264 } else { 265 aprint_normal(", phy %d (mii)", phyaddr); 266 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 267 } 268 if (device_cfdata(&sc->sc_dev)->cf_flags & 2) 269 sc->sc_flags |= GE_NOFREE; 270 sc->sc_pcxr &= ~(3 << 14); 271 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 272 273 if (sc->sc_pcr & ETH_EPCR_EN) { 274 int tries = 1000; 275 /* 276 * Abort transmitter and receiver and wait for them to quiese 277 */ 278 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 279 do { 280 delay(100); 281 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 282 } 283 284 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 285 286 #if defined(DEBUG) 287 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 288 #endif 289 290 /* 291 * Now turn off the GT. If it didn't quiese, too ***ing bad. 292 */ 293 GE_WRITE(sc, EPCR, sc->sc_pcr); 294 GE_WRITE(sc, EIMR, sc->sc_intrmask); 295 sdcr = GE_READ(sc, ESDCR); 296 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 297 sdcr |= ETH_ESDCR_RIFB; 298 GE_WRITE(sc, ESDCR, sdcr); 299 sc->sc_max_frame_length = 1536; 300 301 aprint_normal("\n"); 302 sc->sc_mii.mii_ifp = ifp; 303 sc->sc_mii.mii_readreg = gfe_mii_read; 304 sc->sc_mii.mii_writereg = gfe_mii_write; 305 sc->sc_mii.mii_statchg = gfe_mii_statchg; 306 307 sc->sc_ec.ec_mii = &sc->sc_mii; 308 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 309 ether_mediastatus); 310 311 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 312 MII_OFFSET_ANY, MIIF_NOISOLATE); 313 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 314 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 315 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 316 } else { 317 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 318 } 319 320 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 321 ifp->if_softc = sc; 322 /* ifp->if_mowner = &sc->sc_mowner; */ 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 #if 0 325 ifp->if_flags |= IFF_DEBUG; 326 #endif 327 ifp->if_ioctl = gfe_ifioctl; 328 ifp->if_start = gfe_ifstart; 329 ifp->if_watchdog = gfe_ifwatchdog; 330 331 if (sc->sc_flags & GE_NOFREE) { 332 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 333 if (!error) 334 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 335 if (!error) 336 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 337 if (!error) 338 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 339 if (!error) 340 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 341 if (!error) 342 error = gfe_hash_alloc(sc); 343 if (error) 344 aprint_error( 345 "%s: failed to allocate resources: %d\n", 346 ifp->if_xname, error); 347 } 348 349 if_attach(ifp); 350 ether_ifattach(ifp, enaddr); 351 bpf_ops->bpf_attach(ifp, DLT_EN10MB, 352 sizeof(struct ether_header), &ifp->if_bpf); 353 #if NRND > 0 354 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 0); 355 #endif 356 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 357 gfe_intr, sc); 358 } 359 360 int 361 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 362 size_t size, int flags) 363 { 364 int error = 0; 365 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 366 367 KASSERT(gdm->gdm_kva == NULL); 368 gdm->gdm_size = size; 369 gdm->gdm_maxsegs = maxsegs; 370 371 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 372 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 373 BUS_DMA_NOWAIT); 374 if (error) 375 goto fail; 376 377 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 378 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 379 if (error) 380 goto fail; 381 382 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 383 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 384 if (error) 385 goto fail; 386 387 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 388 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 389 if (error) 390 goto fail; 391 392 /* invalidate from cache */ 393 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 394 BUS_DMASYNC_PREREAD); 395 fail: 396 if (error) { 397 gfe_dmamem_free(sc, gdm); 398 GE_DPRINTF(sc, (":err=%d", error)); 399 } 400 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 401 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 402 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 403 GE_FUNC_EXIT(sc, ""); 404 return error; 405 } 406 407 void 408 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 409 { 410 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 411 if (gdm->gdm_map) 412 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 413 if (gdm->gdm_kva) 414 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 415 if (gdm->gdm_nsegs > 0) 416 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 417 gdm->gdm_map = NULL; 418 gdm->gdm_kva = NULL; 419 gdm->gdm_nsegs = 0; 420 GE_FUNC_EXIT(sc, ""); 421 } 422 423 int 424 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 425 { 426 struct gfe_softc * const sc = ifp->if_softc; 427 struct ifreq *ifr = (struct ifreq *) data; 428 struct ifaddr *ifa = (struct ifaddr *) data; 429 int s, error = 0; 430 431 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 432 s = splnet(); 433 434 switch (cmd) { 435 case SIOCINITIFADDR: 436 ifp->if_flags |= IFF_UP; 437 error = gfe_whack(sc, GE_WHACK_START); 438 switch (ifa->ifa_addr->sa_family) { 439 #ifdef INET 440 case AF_INET: 441 if (error == 0) 442 arp_ifinit(ifp, ifa); 443 break; 444 #endif 445 default: 446 break; 447 } 448 break; 449 450 case SIOCSIFFLAGS: 451 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 452 break; 453 /* XXX re-use ether_ioctl() */ 454 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 455 case IFF_UP|IFF_RUNNING:/* active->active, update */ 456 error = gfe_whack(sc, GE_WHACK_CHANGE); 457 break; 458 case IFF_RUNNING: /* not up, so we stop */ 459 error = gfe_whack(sc, GE_WHACK_STOP); 460 break; 461 case IFF_UP: /* not running, so we start */ 462 error = gfe_whack(sc, GE_WHACK_START); 463 break; 464 case 0: /* idle->idle: do nothing */ 465 break; 466 } 467 break; 468 469 case SIOCSIFMEDIA: 470 case SIOCGIFMEDIA: 471 case SIOCADDMULTI: 472 case SIOCDELMULTI: 473 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 474 if (ifp->if_flags & IFF_RUNNING) 475 error = gfe_whack(sc, GE_WHACK_CHANGE); 476 else 477 error = 0; 478 } 479 break; 480 481 case SIOCSIFMTU: 482 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 483 error = EINVAL; 484 break; 485 } 486 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 487 error = 0; 488 break; 489 490 default: 491 error = ether_ioctl(ifp, cmd, data); 492 break; 493 } 494 splx(s); 495 GE_FUNC_EXIT(sc, ""); 496 return error; 497 } 498 499 void 500 gfe_ifstart(struct ifnet *ifp) 501 { 502 struct gfe_softc * const sc = ifp->if_softc; 503 struct mbuf *m; 504 505 GE_FUNC_ENTER(sc, "gfe_ifstart"); 506 507 if ((ifp->if_flags & IFF_RUNNING) == 0) { 508 GE_FUNC_EXIT(sc, "$"); 509 return; 510 } 511 512 for (;;) { 513 IF_DEQUEUE(&ifp->if_snd, m); 514 if (m == NULL) { 515 ifp->if_flags &= ~IFF_OACTIVE; 516 GE_FUNC_EXIT(sc, ""); 517 return; 518 } 519 520 /* 521 * No space in the pending queue? try later. 522 */ 523 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 524 break; 525 526 /* 527 * Try to enqueue a mbuf to the device. If that fails, we 528 * can always try to map the next mbuf. 529 */ 530 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 531 GE_DPRINTF(sc, (">")); 532 #ifndef GE_NOTX 533 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 534 #endif 535 } 536 537 /* 538 * Attempt to queue the mbuf for send failed. 539 */ 540 IF_PREPEND(&ifp->if_snd, m); 541 ifp->if_flags |= IFF_OACTIVE; 542 GE_FUNC_EXIT(sc, "%%"); 543 } 544 545 void 546 gfe_ifwatchdog(struct ifnet *ifp) 547 { 548 struct gfe_softc * const sc = ifp->if_softc; 549 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 550 551 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 552 printf("%s: device timeout", device_xname(&sc->sc_dev)); 553 if (ifp->if_flags & IFF_RUNNING) { 554 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 555 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 556 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 557 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 558 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 559 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 560 GE_READ(sc, EICR)); 561 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 562 GE_TXDPRESYNC(sc, txq, curtxdnum); 563 } 564 printf("\n"); 565 ifp->if_oerrors++; 566 (void) gfe_whack(sc, GE_WHACK_RESTART); 567 GE_FUNC_EXIT(sc, ""); 568 } 569 570 int 572 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 573 { 574 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 575 int error; 576 577 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 578 GE_DPRINTF(sc, ("(%d)", rxprio)); 579 580 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 581 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 582 if (error) { 583 GE_FUNC_EXIT(sc, "!!"); 584 return error; 585 } 586 587 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 588 GE_RXBUF_MEMSIZE, 0); 589 if (error) { 590 GE_FUNC_EXIT(sc, "!!!"); 591 return error; 592 } 593 GE_FUNC_EXIT(sc, ""); 594 return error; 595 } 596 597 int 598 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 599 { 600 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 601 volatile struct gt_eth_desc *rxd; 602 const bus_dma_segment_t *ds; 603 int idx; 604 bus_addr_t nxtaddr; 605 bus_size_t boff; 606 607 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 608 GE_DPRINTF(sc, ("(%d)", rxprio)); 609 610 if ((sc->sc_flags & GE_NOFREE) == 0) { 611 int error = gfe_rx_rxqalloc(sc, rxprio); 612 if (error) { 613 GE_FUNC_EXIT(sc, "!"); 614 return error; 615 } 616 } else { 617 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 618 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 619 } 620 621 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 622 623 rxq->rxq_descs = 624 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 625 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 626 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 627 rxq->rxq_fi = 0; 628 rxq->rxq_active = GE_RXDESC_MAX; 629 for (idx = 0, rxd = rxq->rxq_descs, 630 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 631 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 632 idx < GE_RXDESC_MAX; 633 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 634 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 635 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 636 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 637 /* 638 * update the nxtptr to point to the next txd. 639 */ 640 if (idx == GE_RXDESC_MAX - 1) 641 nxtaddr = rxq->rxq_desc_busaddr; 642 rxd->ed_nxtptr = htogt32(nxtaddr); 643 boff += GE_RXBUF_SIZE; 644 if (boff == ds->ds_len) { 645 ds++; 646 boff = 0; 647 } 648 } 649 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 650 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 651 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 652 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 653 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 654 BUS_DMASYNC_PREREAD); 655 656 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 657 switch (rxprio) { 658 case GE_RXPRIO_HI: 659 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 660 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 661 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 662 break; 663 case GE_RXPRIO_MEDHI: 664 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 665 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 666 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 667 break; 668 case GE_RXPRIO_MEDLO: 669 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 670 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 671 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 672 break; 673 case GE_RXPRIO_LO: 674 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 675 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 676 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 677 break; 678 } 679 GE_FUNC_EXIT(sc, ""); 680 return 0; 681 } 682 683 void 684 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 685 { 686 struct ifnet * const ifp = &sc->sc_ec.ec_if; 687 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 688 struct mbuf *m = rxq->rxq_curpkt; 689 690 GE_FUNC_ENTER(sc, "gfe_rx_get"); 691 GE_DPRINTF(sc, ("(%d)", rxprio)); 692 693 while (rxq->rxq_active > 0) { 694 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 695 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 696 const struct ether_header *eh; 697 unsigned int cmdsts; 698 size_t buflen; 699 700 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 701 cmdsts = gt32toh(rxd->ed_cmdsts); 702 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 703 rxq->rxq_cmdsts = cmdsts; 704 /* 705 * Sometimes the GE "forgets" to reset the ownership bit. 706 * But if the length has been rewritten, the packet is ours 707 * so pretend the O bit is set. 708 */ 709 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 710 if ((cmdsts & RX_CMD_O) && buflen == 0) { 711 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 712 break; 713 } 714 715 /* 716 * If this is not a single buffer packet with no errors 717 * or for some reason it's bigger than our frame size, 718 * ignore it and go to the next packet. 719 */ 720 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 721 (RX_CMD_F|RX_CMD_L) || 722 buflen > sc->sc_max_frame_length) { 723 GE_DPRINTF(sc, ("!")); 724 --rxq->rxq_active; 725 ifp->if_ipackets++; 726 ifp->if_ierrors++; 727 goto give_it_back; 728 } 729 730 /* CRC is included with the packet; trim it off. */ 731 buflen -= ETHER_CRC_LEN; 732 733 if (m == NULL) { 734 MGETHDR(m, M_DONTWAIT, MT_DATA); 735 if (m == NULL) { 736 GE_DPRINTF(sc, ("?")); 737 break; 738 } 739 } 740 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 741 MCLGET(m, M_DONTWAIT); 742 if ((m->m_flags & M_EXT) == 0) { 743 GE_DPRINTF(sc, ("?")); 744 break; 745 } 746 } 747 m->m_data += 2; 748 m->m_len = 0; 749 m->m_pkthdr.len = 0; 750 m->m_pkthdr.rcvif = ifp; 751 rxq->rxq_cmdsts = cmdsts; 752 --rxq->rxq_active; 753 754 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 755 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 756 757 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 758 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 759 m->m_len = buflen; 760 m->m_pkthdr.len = buflen; 761 762 ifp->if_ipackets++; 763 if (ifp->if_bpf != NULL) 764 bpf_ops->bpf_mtap(ifp->if_bpf, m); 765 766 eh = (const struct ether_header *) m->m_data; 767 if ((ifp->if_flags & IFF_PROMISC) || 768 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 769 (rxq->rxq_cmdsts & RX_STS_HE) || 770 (eh->ether_dhost[0] & 1) != 0 || 771 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 772 ETHER_ADDR_LEN) == 0) { 773 (*ifp->if_input)(ifp, m); 774 m = NULL; 775 GE_DPRINTF(sc, (">")); 776 } else { 777 m->m_len = 0; 778 m->m_pkthdr.len = 0; 779 GE_DPRINTF(sc, ("+")); 780 } 781 rxq->rxq_cmdsts = 0; 782 783 give_it_back: 784 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 785 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 786 #if 0 787 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 788 rxq->rxq_fi, 789 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 790 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 791 #endif 792 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 793 if (++rxq->rxq_fi == GE_RXDESC_MAX) 794 rxq->rxq_fi = 0; 795 rxq->rxq_active++; 796 } 797 rxq->rxq_curpkt = m; 798 GE_FUNC_EXIT(sc, ""); 799 } 800 801 uint32_t 802 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 803 { 804 struct ifnet * const ifp = &sc->sc_ec.ec_if; 805 struct gfe_rxqueue *rxq; 806 uint32_t rxbits; 807 #define RXPRIO_DECODER 0xffffaa50 808 GE_FUNC_ENTER(sc, "gfe_rx_process"); 809 810 rxbits = ETH_IR_RxBuffer_GET(cause); 811 while (rxbits) { 812 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 813 GE_DPRINTF(sc, ("%1x", rxbits)); 814 rxbits &= ~(1 << rxprio); 815 gfe_rx_get(sc, rxprio); 816 } 817 818 rxbits = ETH_IR_RxError_GET(cause); 819 while (rxbits) { 820 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 821 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 822 int idx; 823 rxbits &= ~(1 << rxprio); 824 rxq = &sc->sc_rxq[rxprio]; 825 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 826 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 827 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 828 sc->sc_tickflags |= GE_TICK_RX_RESTART; 829 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 830 } 831 ifp->if_ierrors++; 832 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 833 device_xname(&sc->sc_dev), rxprio, rxq->rxq_fi)); 834 memset(masks, 0, sizeof(masks)); 835 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 836 0, rxq->rxq_desc_mem.gdm_size, 837 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 838 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 839 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 840 841 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 842 masks[idx/32] |= 1 << (idx & 31); 843 } 844 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 845 0, rxq->rxq_desc_mem.gdm_size, 846 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 847 #if defined(DEBUG) 848 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 849 device_xname(&sc->sc_dev), rxprio, rxq->rxq_fi, 850 rxq->rxq_cmdsts, masks[0], masks[1]); 851 #endif 852 } 853 if ((intrmask & ETH_IR_RxBits) == 0) 854 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 855 856 GE_FUNC_EXIT(sc, ""); 857 return intrmask; 858 } 859 860 int 861 gfe_rx_prime(struct gfe_softc *sc) 862 { 863 struct gfe_rxqueue *rxq; 864 int error; 865 866 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 867 868 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 869 if (error) 870 goto bail; 871 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 872 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 873 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 874 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 875 } 876 sc->sc_intrmask |= rxq->rxq_intrbits; 877 878 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 879 if (error) 880 goto bail; 881 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 882 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 883 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 884 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 885 sc->sc_intrmask |= rxq->rxq_intrbits; 886 } 887 888 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 889 if (error) 890 goto bail; 891 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 892 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 893 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 894 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 895 sc->sc_intrmask |= rxq->rxq_intrbits; 896 } 897 898 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 899 if (error) 900 goto bail; 901 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 902 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 903 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 904 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 905 sc->sc_intrmask |= rxq->rxq_intrbits; 906 } 907 908 bail: 909 GE_FUNC_EXIT(sc, ""); 910 return error; 911 } 912 913 void 914 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 915 { 916 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 917 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 918 if (rxq == NULL) { 919 GE_FUNC_EXIT(sc, ""); 920 return; 921 } 922 923 if (rxq->rxq_curpkt) 924 m_freem(rxq->rxq_curpkt); 925 if ((sc->sc_flags & GE_NOFREE) == 0) { 926 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 927 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 928 } 929 GE_FUNC_EXIT(sc, ""); 930 } 931 932 void 933 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 934 { 935 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 936 sc->sc_flags &= ~GE_RXACTIVE; 937 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 938 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 939 GE_WRITE(sc, EIMR, sc->sc_intrmask); 940 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 941 do { 942 delay(10); 943 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 944 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 945 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 946 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 947 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 948 GE_FUNC_EXIT(sc, ""); 949 } 950 951 void 953 gfe_tick(void *arg) 954 { 955 struct gfe_softc * const sc = arg; 956 uint32_t intrmask; 957 unsigned int tickflags; 958 int s; 959 960 GE_FUNC_ENTER(sc, "gfe_tick"); 961 962 s = splnet(); 963 964 tickflags = sc->sc_tickflags; 965 sc->sc_tickflags = 0; 966 intrmask = sc->sc_intrmask; 967 if (tickflags & GE_TICK_TX_IFSTART) 968 gfe_ifstart(&sc->sc_ec.ec_if); 969 if (tickflags & GE_TICK_RX_RESTART) { 970 intrmask |= sc->sc_idlemask; 971 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 972 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 973 rxq->rxq_fi = 0; 974 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 975 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 976 } 977 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 978 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 979 rxq->rxq_fi = 0; 980 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 981 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 982 } 983 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 984 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 985 rxq->rxq_fi = 0; 986 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 987 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 988 } 989 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 990 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 991 rxq->rxq_fi = 0; 992 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 993 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 994 } 995 sc->sc_idlemask = 0; 996 } 997 if (intrmask != sc->sc_intrmask) { 998 sc->sc_intrmask = intrmask; 999 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1000 } 1001 gfe_intr(sc); 1002 splx(s); 1003 1004 GE_FUNC_EXIT(sc, ""); 1005 } 1006 1007 int 1008 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1009 { 1010 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1011 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1012 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1013 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1014 uint32_t intrmask = sc->sc_intrmask; 1015 size_t buflen; 1016 struct mbuf *m; 1017 1018 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1019 1020 /* 1021 * Anything in the pending queue to enqueue? if not, punt. Likewise 1022 * if the txq is not yet created. 1023 * otherwise grab its dmamap. 1024 */ 1025 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1026 GE_FUNC_EXIT(sc, "-"); 1027 return 0; 1028 } 1029 1030 /* 1031 * Have we [over]consumed our limit of descriptors? 1032 * Do we have enough free descriptors? 1033 */ 1034 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1035 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1036 uint32_t cmdsts; 1037 size_t pktlen; 1038 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1039 cmdsts = gt32toh(txd2->ed_cmdsts); 1040 if (cmdsts & TX_CMD_O) { 1041 int nextin; 1042 /* 1043 * Sometime the Discovery forgets to update the 1044 * last descriptor. See if we own the descriptor 1045 * after it (since we know we've turned that to 1046 * the discovery and if we owned it, the Discovery 1047 * gave it back). If we do, we know the Discovery 1048 * gave back this one but forgot to mark it as ours. 1049 */ 1050 nextin = txq->txq_fi + 1; 1051 if (nextin == GE_TXDESC_MAX) 1052 nextin = 0; 1053 GE_TXDPOSTSYNC(sc, txq, nextin); 1054 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1055 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1056 GE_TXDPRESYNC(sc, txq, nextin); 1057 GE_FUNC_EXIT(sc, "@"); 1058 return 0; 1059 } 1060 #ifdef DEBUG 1061 printf("%s: txenqueue: transmitter resynced at %d\n", 1062 device_xname(&sc->sc_dev), txq->txq_fi); 1063 #endif 1064 } 1065 if (++txq->txq_fi == GE_TXDESC_MAX) 1066 txq->txq_fi = 0; 1067 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1068 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1069 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1070 txq->txq_nactive--; 1071 1072 /* statistics */ 1073 ifp->if_opackets++; 1074 if (cmdsts & TX_STS_ES) 1075 ifp->if_oerrors++; 1076 GE_DPRINTF(sc, ("%%")); 1077 } 1078 1079 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1080 1081 /* 1082 * If this packet would wrap around the end of the buffer, reset back 1083 * to the beginning. 1084 */ 1085 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1086 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1087 txq->txq_outptr = 0; 1088 } 1089 1090 /* 1091 * Make sure the output packet doesn't run over the beginning of 1092 * what we've already given the GT. 1093 */ 1094 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1095 txq->txq_outptr + buflen > txq->txq_inptr) { 1096 intrmask |= txq->txq_intrbits & 1097 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1098 if (sc->sc_intrmask != intrmask) { 1099 sc->sc_intrmask = intrmask; 1100 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1101 } 1102 GE_FUNC_EXIT(sc, "#"); 1103 return 0; 1104 } 1105 1106 /* 1107 * The end-of-list descriptor we put on last time is the starting point 1108 * for this packet. The GT is supposed to terminate list processing on 1109 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1110 * must terminate the list. 1111 */ 1112 intrmask = sc->sc_intrmask; 1113 1114 m_copydata(m, 0, m->m_pkthdr.len, 1115 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1116 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1117 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1118 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1119 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1120 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1121 1122 /* 1123 * Request a buffer interrupt every 2/3 of the way thru the transmit 1124 * buffer. 1125 */ 1126 txq->txq_ei_gapcount += buflen; 1127 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1128 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1129 txq->txq_ei_gapcount = 0; 1130 } else { 1131 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1132 } 1133 #if 0 1134 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1135 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1136 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1137 #endif 1138 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1139 1140 txq->txq_outptr += buflen; 1141 /* 1142 * Tell the SDMA engine to "Fetch!" 1143 */ 1144 GE_WRITE(sc, ESDCMR, 1145 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1146 1147 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1148 1149 /* 1150 * Update the last out appropriately. 1151 */ 1152 txq->txq_nactive++; 1153 if (++txq->txq_lo == GE_TXDESC_MAX) 1154 txq->txq_lo = 0; 1155 1156 /* 1157 * Move mbuf from the pending queue to the snd queue. 1158 */ 1159 IF_DEQUEUE(&txq->txq_pendq, m); 1160 if (ifp->if_bpf != NULL) 1161 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1162 m_freem(m); 1163 ifp->if_flags &= ~IFF_OACTIVE; 1164 1165 /* 1166 * Since we have put an item into the packet queue, we now want 1167 * an interrupt when the transmit queue finishes processing the 1168 * list. But only update the mask if needs changing. 1169 */ 1170 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1171 if (sc->sc_intrmask != intrmask) { 1172 sc->sc_intrmask = intrmask; 1173 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1174 } 1175 if (ifp->if_timer == 0) 1176 ifp->if_timer = 5; 1177 GE_FUNC_EXIT(sc, "*"); 1178 return 1; 1179 } 1180 1181 uint32_t 1182 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1183 { 1184 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1185 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1186 1187 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1188 1189 if (txq == NULL) { 1190 GE_FUNC_EXIT(sc, ""); 1191 return intrmask; 1192 } 1193 1194 while (txq->txq_nactive > 0) { 1195 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1196 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1197 uint32_t cmdsts; 1198 size_t pktlen; 1199 1200 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1201 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1202 int nextin; 1203 1204 if (txq->txq_nactive == 1) { 1205 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1206 GE_FUNC_EXIT(sc, ""); 1207 return intrmask; 1208 } 1209 /* 1210 * Sometimes the Discovery forgets to update the 1211 * ownership bit in the descriptor. See if we own the 1212 * descriptor after it (since we know we've turned 1213 * that to the Discovery and if we own it now then the 1214 * Discovery gave it back). If we do, we know the 1215 * Discovery gave back this one but forgot to mark it 1216 * as ours. 1217 */ 1218 nextin = txq->txq_fi + 1; 1219 if (nextin == GE_TXDESC_MAX) 1220 nextin = 0; 1221 GE_TXDPOSTSYNC(sc, txq, nextin); 1222 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1223 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1224 GE_TXDPRESYNC(sc, txq, nextin); 1225 GE_FUNC_EXIT(sc, ""); 1226 return intrmask; 1227 } 1228 #ifdef DEBUG 1229 printf("%s: txdone: transmitter resynced at %d\n", 1230 device_xname(&sc->sc_dev), txq->txq_fi); 1231 #endif 1232 } 1233 #if 0 1234 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1235 txq->txq_lo, 1236 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1237 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1238 #endif 1239 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1240 if (++txq->txq_fi == GE_TXDESC_MAX) 1241 txq->txq_fi = 0; 1242 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1243 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1244 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1245 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1246 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1247 1248 /* statistics */ 1249 ifp->if_opackets++; 1250 if (cmdsts & TX_STS_ES) 1251 ifp->if_oerrors++; 1252 1253 /* txd->ed_bufptr = 0; */ 1254 1255 ifp->if_timer = 5; 1256 --txq->txq_nactive; 1257 } 1258 if (txq->txq_nactive != 0) 1259 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1260 device_xname(&sc->sc_dev), txprio, txq->txq_nactive); 1261 ifp->if_timer = 0; 1262 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1263 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1264 GE_FUNC_EXIT(sc, ""); 1265 return intrmask; 1266 } 1267 1268 int 1269 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1270 { 1271 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1272 int error; 1273 1274 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1275 1276 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1277 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1278 if (error) { 1279 GE_FUNC_EXIT(sc, ""); 1280 return error; 1281 } 1282 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1283 if (error) { 1284 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1285 GE_FUNC_EXIT(sc, ""); 1286 return error; 1287 } 1288 GE_FUNC_EXIT(sc, ""); 1289 return 0; 1290 } 1291 1292 int 1293 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1294 { 1295 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1296 volatile struct gt_eth_desc *txd; 1297 unsigned int i; 1298 bus_addr_t addr; 1299 1300 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1301 1302 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1303 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1304 1305 if (sc->sc_flags & GE_NOFREE) { 1306 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1307 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1308 } else { 1309 int error = gfe_tx_txqalloc(sc, txprio); 1310 if (error) { 1311 GE_FUNC_EXIT(sc, "!"); 1312 return error; 1313 } 1314 } 1315 1316 txq->txq_descs = 1317 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1318 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1319 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1320 1321 txq->txq_pendq.ifq_maxlen = 10; 1322 txq->txq_ei_gapcount = 0; 1323 txq->txq_nactive = 0; 1324 txq->txq_fi = 0; 1325 txq->txq_lo = 0; 1326 txq->txq_inptr = GE_TXBUF_SIZE; 1327 txq->txq_outptr = 0; 1328 for (i = 0, txd = txq->txq_descs, 1329 addr = txq->txq_desc_busaddr + sizeof(*txd); 1330 i < GE_TXDESC_MAX - 1; 1331 i++, txd++, addr += sizeof(*txd)) { 1332 /* 1333 * update the nxtptr to point to the next txd. 1334 */ 1335 txd->ed_cmdsts = 0; 1336 txd->ed_nxtptr = htogt32(addr); 1337 } 1338 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1339 htogt32(txq->txq_desc_busaddr); 1340 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1341 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1342 1343 switch (txprio) { 1344 case GE_TXPRIO_HI: 1345 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1346 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1347 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1348 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1349 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1350 break; 1351 1352 case GE_TXPRIO_LO: 1353 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1354 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1355 txq->txq_epsrbits = ETH_EPSR_TxLow; 1356 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1357 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1358 break; 1359 1360 case GE_TXPRIO_NONE: 1361 break; 1362 } 1363 #if 0 1364 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1365 gt_write(device_parent(&sc->sc_dev), txq->txq_ectdp, 1366 txq->txq_desc_busaddr); 1367 GE_DPRINTF(sc, (")")); 1368 #endif 1369 1370 /* 1371 * If we are restarting, there may be packets in the pending queue 1372 * waiting to be enqueued. Try enqueuing packets from both priority 1373 * queues until the pending queue is empty or there no room for them 1374 * on the device. 1375 */ 1376 while (gfe_tx_enqueue(sc, txprio)) 1377 continue; 1378 1379 GE_FUNC_EXIT(sc, ""); 1380 return 0; 1381 } 1382 1383 void 1384 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1385 { 1386 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1387 1388 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1389 if (txq == NULL) { 1390 GE_FUNC_EXIT(sc, ""); 1391 return; 1392 } 1393 1394 if (!flush) { 1395 GE_FUNC_EXIT(sc, ""); 1396 return; 1397 } 1398 1399 if ((sc->sc_flags & GE_NOFREE) == 0) { 1400 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1401 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1402 } 1403 GE_FUNC_EXIT(sc, "-F"); 1404 } 1405 1406 void 1407 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1408 { 1409 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1410 1411 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1412 1413 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1414 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1415 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1416 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1417 1418 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1419 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1420 1421 sc->sc_ec.ec_if.if_timer = 0; 1422 GE_FUNC_EXIT(sc, ""); 1423 } 1424 1425 int 1427 gfe_intr(void *arg) 1428 { 1429 struct gfe_softc * const sc = arg; 1430 uint32_t cause; 1431 uint32_t intrmask = sc->sc_intrmask; 1432 int claim = 0; 1433 int cnt; 1434 1435 GE_FUNC_ENTER(sc, "gfe_intr"); 1436 1437 for (cnt = 0; cnt < 4; cnt++) { 1438 if (sc->sc_intrmask != intrmask) { 1439 sc->sc_intrmask = intrmask; 1440 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1441 } 1442 cause = GE_READ(sc, EICR); 1443 cause &= sc->sc_intrmask; 1444 GE_DPRINTF(sc, (".%#x", cause)); 1445 if (cause == 0) 1446 break; 1447 1448 claim = 1; 1449 1450 GE_WRITE(sc, EICR, ~cause); 1451 #ifndef GE_NORX 1452 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1453 intrmask = gfe_rx_process(sc, cause, intrmask); 1454 #endif 1455 1456 #ifndef GE_NOTX 1457 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1458 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1459 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1460 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1461 #endif 1462 if (cause & ETH_IR_MIIPhySTC) { 1463 sc->sc_flags |= GE_PHYSTSCHG; 1464 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1465 } 1466 } 1467 1468 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1469 continue; 1470 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1471 continue; 1472 1473 GE_FUNC_EXIT(sc, ""); 1474 return claim; 1475 } 1476 1477 int 1479 gfe_mii_read (device_t self, int phy, int reg) 1480 { 1481 return gt_mii_read(self, device_parent(self), phy, reg); 1482 } 1483 1484 void 1485 gfe_mii_write (device_t self, int phy, int reg, int value) 1486 { 1487 gt_mii_write(self, device_parent(self), phy, reg, value); 1488 } 1489 1490 void 1491 gfe_mii_statchg (device_t self) 1492 { 1493 /* struct gfe_softc *sc = device_private(self); */ 1494 /* do nothing? */ 1495 } 1496 1497 int 1499 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1500 { 1501 int error = 0; 1502 GE_FUNC_ENTER(sc, "gfe_whack"); 1503 1504 switch (op) { 1505 case GE_WHACK_RESTART: 1506 #ifndef GE_NOTX 1507 gfe_tx_stop(sc, op); 1508 #endif 1509 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1510 /* FALLTHROUGH */ 1511 case GE_WHACK_START: 1512 #ifndef GE_NOHASH 1513 if (error == 0 && sc->sc_hashtable == NULL) { 1514 error = gfe_hash_alloc(sc); 1515 if (error) 1516 break; 1517 } 1518 if (op != GE_WHACK_RESTART) 1519 gfe_hash_fill(sc); 1520 #endif 1521 #ifndef GE_NORX 1522 if (op != GE_WHACK_RESTART) { 1523 error = gfe_rx_prime(sc); 1524 if (error) 1525 break; 1526 } 1527 #endif 1528 #ifndef GE_NOTX 1529 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1530 if (error) 1531 break; 1532 #endif 1533 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1534 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1535 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1536 GE_WRITE(sc, EICR, 0); 1537 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1538 #ifndef GE_NOHASH 1539 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1540 #endif 1541 #ifndef GE_NORX 1542 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1543 sc->sc_flags |= GE_RXACTIVE; 1544 #endif 1545 /* FALLTHROUGH */ 1546 case GE_WHACK_CHANGE: 1547 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1548 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1549 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1550 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1551 gfe_ifstart(&sc->sc_ec.ec_if); 1552 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1553 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1554 GE_FUNC_EXIT(sc, ""); 1555 return error; 1556 case GE_WHACK_STOP: 1557 break; 1558 } 1559 1560 #ifdef GE_DEBUG 1561 if (error) 1562 GE_DPRINTF(sc, (" failed: %d\n", error)); 1563 #endif 1564 GE_WRITE(sc, EPCR, sc->sc_pcr); 1565 GE_WRITE(sc, EIMR, 0); 1566 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1567 #ifndef GE_NOTX 1568 gfe_tx_stop(sc, GE_WHACK_STOP); 1569 #endif 1570 #ifndef GE_NORX 1571 gfe_rx_stop(sc, GE_WHACK_STOP); 1572 #endif 1573 #ifndef GE_NOHASH 1574 if ((sc->sc_flags & GE_NOFREE) == 0) { 1575 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1576 sc->sc_hashtable = NULL; 1577 } 1578 #endif 1579 1580 GE_FUNC_EXIT(sc, ""); 1581 return error; 1582 } 1583 1584 int 1586 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1587 { 1588 uint32_t w0, add0, add1; 1589 uint32_t result; 1590 1591 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1592 add0 = ((uint32_t) eaddr[5] << 0) | 1593 ((uint32_t) eaddr[4] << 8) | 1594 ((uint32_t) eaddr[3] << 16); 1595 1596 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1597 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1598 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1599 1600 add1 = ((uint32_t) eaddr[2] << 0) | 1601 ((uint32_t) eaddr[1] << 8) | 1602 ((uint32_t) eaddr[0] << 16); 1603 1604 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1605 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1606 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1607 1608 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1609 /* 1610 * hashResult is the 15 bits Hash entry address. 1611 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1612 * MAC address, by nibble swapping in every byte (i.e MAC address 1613 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1614 */ 1615 1616 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1617 /* 1618 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1619 * 1620 * hashFunc0 calculates the hashResult in the following manner: 1621 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1622 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1623 */ 1624 result = (add0 & 3) | ((add0 >> 6) & ~3); 1625 result ^= (add0 >> 15) ^ (add1 >> 0); 1626 result &= 0x1ff; 1627 /* 1628 * hashResult[14:9] = ethernetADD[7:2] 1629 */ 1630 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1631 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1632 } else { 1633 #define TRIBITFLIP 073516240 /* yes its in octal */ 1634 /* 1635 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1636 * 1637 * hashFunc1 calculates the hashResult in the following manner: 1638 * hashResult[08:00] = ethernetADD[06:14] 1639 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1640 */ 1641 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1642 /* 1643 * Now bitswap those 9 bits 1644 */ 1645 result = 0; 1646 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1647 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1648 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1649 1650 /* 1651 * hashResult[14:09] = ethernetADD[00:05] 1652 */ 1653 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1654 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1655 GE_DPRINTF(sc, ("1(%#x)", result)); 1656 } 1657 GE_FUNC_EXIT(sc, ""); 1658 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1659 } 1660 1661 int 1662 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1663 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1664 { 1665 uint64_t he; 1666 uint64_t *maybe_he_p = NULL; 1667 int limit; 1668 int hash; 1669 int maybe_hash = 0; 1670 1671 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1672 1673 hash = gfe_hash_compute(sc, eaddr); 1674 1675 if (sc->sc_hashtable == NULL) { 1676 panic("%s:%d: hashtable == NULL!", device_xname(&sc->sc_dev), 1677 __LINE__); 1678 } 1679 1680 /* 1681 * Assume we are going to insert so create the hash entry we 1682 * are going to insert. We also use it to match entries we 1683 * will be removing. 1684 */ 1685 he = ((uint64_t) eaddr[5] << 43) | 1686 ((uint64_t) eaddr[4] << 35) | 1687 ((uint64_t) eaddr[3] << 27) | 1688 ((uint64_t) eaddr[2] << 19) | 1689 ((uint64_t) eaddr[1] << 11) | 1690 ((uint64_t) eaddr[0] << 3) | 1691 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1692 1693 /* 1694 * The GT will search upto 12 entries for a hit, so we must mimic that. 1695 */ 1696 hash &= sc->sc_hashmask / sizeof(he); 1697 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1698 /* 1699 * Does the GT wrap at the end, stop at the, or overrun the 1700 * end? Assume it wraps for now. Stash a copy of the 1701 * current hash entry. 1702 */ 1703 uint64_t *he_p = &sc->sc_hashtable[hash]; 1704 uint64_t thishe = *he_p; 1705 1706 /* 1707 * If the hash entry isn't valid, that break the chain. And 1708 * this entry a good candidate for reuse. 1709 */ 1710 if ((thishe & HSH_V) == 0) { 1711 maybe_he_p = he_p; 1712 break; 1713 } 1714 1715 /* 1716 * If the hash entry has the same address we are looking for 1717 * then ... if we are removing and the skip bit is set, its 1718 * already been removed. if are adding and the skip bit is 1719 * clear, then its already added. In either return EBUSY 1720 * indicating the op has already been done. Otherwise flip 1721 * the skip bit and return 0. 1722 */ 1723 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1724 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1725 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1726 return EBUSY; 1727 *he_p = thishe ^ HSH_S; 1728 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1729 hash * sizeof(he), sizeof(he), 1730 BUS_DMASYNC_PREWRITE); 1731 GE_FUNC_EXIT(sc, "^"); 1732 return 0; 1733 } 1734 1735 /* 1736 * If we haven't found a slot for the entry and this entry 1737 * is currently being skipped, return this entry. 1738 */ 1739 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1740 maybe_he_p = he_p; 1741 maybe_hash = hash; 1742 } 1743 1744 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1745 } 1746 1747 /* 1748 * If we got here, then there was no entry to remove. 1749 */ 1750 if (op == GE_HASH_REMOVE) { 1751 GE_FUNC_EXIT(sc, "?"); 1752 return ENOENT; 1753 } 1754 1755 /* 1756 * If we couldn't find a slot, return an error. 1757 */ 1758 if (maybe_he_p == NULL) { 1759 GE_FUNC_EXIT(sc, "!"); 1760 return ENOSPC; 1761 } 1762 1763 /* Update the entry. 1764 */ 1765 *maybe_he_p = he; 1766 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1767 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1768 GE_FUNC_EXIT(sc, "+"); 1769 return 0; 1770 } 1771 1772 int 1773 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1774 { 1775 struct gfe_softc * const sc = ec->ec_if.if_softc; 1776 int error; 1777 enum gfe_hash_op op; 1778 enum gfe_rxprio prio; 1779 1780 GE_FUNC_ENTER(sc, "hash_multichg"); 1781 /* 1782 * Is this a wildcard entry? If so and its being removed, recompute. 1783 */ 1784 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1785 if (cmd == SIOCDELMULTI) { 1786 GE_FUNC_EXIT(sc, ""); 1787 return ENETRESET; 1788 } 1789 1790 /* 1791 * Switch in 1792 */ 1793 sc->sc_flags |= GE_ALLMULTI; 1794 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1795 sc->sc_pcr |= ETH_EPCR_PM; 1796 GE_WRITE(sc, EPCR, sc->sc_pcr); 1797 GE_FUNC_EXIT(sc, ""); 1798 return 0; 1799 } 1800 GE_FUNC_EXIT(sc, ""); 1801 return ENETRESET; 1802 } 1803 1804 prio = GE_RXPRIO_MEDLO; 1805 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1806 1807 if (sc->sc_hashtable == NULL) { 1808 GE_FUNC_EXIT(sc, ""); 1809 return 0; 1810 } 1811 1812 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1813 if (error == EBUSY) { 1814 printf("%s: multichg: tried to %s %s again\n", 1815 device_xname(&sc->sc_dev), 1816 cmd == SIOCDELMULTI ? "remove" : "add", 1817 ether_sprintf(enm->enm_addrlo)); 1818 GE_FUNC_EXIT(sc, ""); 1819 return 0; 1820 } 1821 1822 if (error == ENOENT) { 1823 printf("%s: multichg: failed to remove %s: not in table\n", 1824 device_xname(&sc->sc_dev), 1825 ether_sprintf(enm->enm_addrlo)); 1826 GE_FUNC_EXIT(sc, ""); 1827 return 0; 1828 } 1829 1830 if (error == ENOSPC) { 1831 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1832 device_xname(&sc->sc_dev), 1833 ether_sprintf(enm->enm_addrlo)); 1834 GE_FUNC_EXIT(sc, ""); 1835 return ENETRESET; 1836 } 1837 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1838 device_xname(&sc->sc_dev), 1839 cmd == SIOCDELMULTI ? "remove" : "add", 1840 ether_sprintf(enm->enm_addrlo))); 1841 GE_FUNC_EXIT(sc, ""); 1842 return 0; 1843 } 1844 1845 int 1846 gfe_hash_fill(struct gfe_softc *sc) 1847 { 1848 struct ether_multistep step; 1849 struct ether_multi *enm; 1850 int error; 1851 1852 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1853 1854 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1855 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 1856 if (error) 1857 GE_FUNC_EXIT(sc, "!"); 1858 return error; 1859 1860 sc->sc_flags &= ~GE_ALLMULTI; 1861 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1862 sc->sc_pcr &= ~ETH_EPCR_PM; 1863 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1864 while (enm != NULL) { 1865 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1866 sc->sc_flags |= GE_ALLMULTI; 1867 sc->sc_pcr |= ETH_EPCR_PM; 1868 } else { 1869 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1870 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1871 if (error == ENOSPC) 1872 break; 1873 } 1874 ETHER_NEXT_MULTI(step, enm); 1875 } 1876 1877 GE_FUNC_EXIT(sc, ""); 1878 return error; 1879 } 1880 1881 int 1882 gfe_hash_alloc(struct gfe_softc *sc) 1883 { 1884 int error; 1885 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1886 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1887 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1888 BUS_DMA_NOCACHE); 1889 if (error) { 1890 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1891 device_xname(&sc->sc_dev), sc->sc_hashmask + 1, error); 1892 GE_FUNC_EXIT(sc, ""); 1893 return error; 1894 } 1895 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1896 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1897 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1898 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1899 GE_FUNC_EXIT(sc, ""); 1900 return 0; 1901 } 1902
Indexes created Sun Oct 19 16:10:00 GMT 2025