if_gfe.c revision 1.29.4.4
1 /* $NetBSD: if_gfe.c,v 1.29.4.4 2010/08/11 22:53:38 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.29.4.4 2010/08/11 22:53:38 yamt Exp $"); 46 47 #include "opt_inet.h" 48 #include "rnd.h" 49 50 #include <sys/param.h> 51 #include <sys/bus.h> 52 #include <sys/callout.h> 53 #include <sys/device.h> 54 #include <sys/errno.h> 55 #include <sys/ioctl.h> 56 #include <sys/mbuf.h> 57 #include <sys/mutex.h> 58 #include <sys/socket.h> 59 60 #include <uvm/uvm.h> 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 #include <net/bpf.h> 73 #if NRND > 0 74 #include <sys/rnd.h> 75 #endif 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <dev/marvell/gtreg.h> 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/gtethreg.h> 83 #include <dev/marvell/if_gfevar.h> 84 #include <dev/marvell/marvellreg.h> 85 #include <dev/marvell/marvellvar.h> 86 87 #include <prop/proplib.h> 88 89 #include "locators.h" 90 91 92 #define GE_READ(sc, reg) \ 93 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg)) 94 #define GE_WRITE(sc, reg, v) \ 95 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v)) 96 97 #define GE_DEBUG 98 #if 0 99 #define GE_NOHASH 100 #define GE_NORX 101 #endif 102 103 #ifdef GE_DEBUG 104 #define GE_DPRINTF(sc, a) \ 105 do { \ 106 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 107 printf a; \ 108 } while (0 /* CONSTCOND */) 109 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 110 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 111 #else 112 #define GE_DPRINTF(sc, a) do { } while (0) 113 #define GE_FUNC_ENTER(sc, func) do { } while (0) 114 #define GE_FUNC_EXIT(sc, str) do { } while (0) 115 #endif 116 enum gfe_whack_op { 117 GE_WHACK_START, GE_WHACK_RESTART, 118 GE_WHACK_CHANGE, GE_WHACK_STOP 119 }; 120 121 enum gfe_hash_op { 122 GE_HASH_ADD, GE_HASH_REMOVE, 123 }; 124 125 #if 1 126 #define htogt32(a) htobe32(a) 127 #define gt32toh(a) be32toh(a) 128 #else 129 #define htogt32(a) htole32(a) 130 #define gt32toh(a) le32toh(a) 131 #endif 132 133 #define GE_RXDSYNC(sc, rxq, n, ops) \ 134 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 135 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 136 (ops)) 137 #define GE_RXDPRESYNC(sc, rxq, n) \ 138 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 139 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 140 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 141 142 #define GE_TXDSYNC(sc, txq, n, ops) \ 143 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 144 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 145 (ops)) 146 #define GE_TXDPRESYNC(sc, txq, n) \ 147 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 148 #define GE_TXDPOSTSYNC(sc, txq, n) \ 149 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 150 151 #define STATIC 152 153 154 STATIC int gfec_match(device_t, cfdata_t, void *); 155 STATIC void gfec_attach(device_t, device_t, void *); 156 157 STATIC int gfec_print(void *, const char *); 158 STATIC int gfec_search(device_t, cfdata_t, const int *, void *); 159 160 STATIC int gfec_enet_phy(device_t, int); 161 STATIC int gfec_mii_read(device_t, int, int); 162 STATIC void gfec_mii_write(device_t, int, int, int); 163 STATIC void gfec_mii_statchg(device_t); 164 165 STATIC int gfe_match(device_t, cfdata_t, void *); 166 STATIC void gfe_attach(device_t, device_t, void *); 167 168 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 169 size_t, int); 170 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 171 172 STATIC int gfe_ifioctl(struct ifnet *, u_long, void *); 173 STATIC void gfe_ifstart(struct ifnet *); 174 STATIC void gfe_ifwatchdog(struct ifnet *); 175 176 STATIC void gfe_tick(void *arg); 177 178 STATIC void gfe_tx_restart(void *); 179 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 180 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 181 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 182 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 183 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 184 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 185 186 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 187 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 188 STATIC int gfe_rx_prime(struct gfe_softc *); 189 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 190 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 191 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 192 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 193 194 STATIC int gfe_intr(void *); 195 196 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 197 198 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 199 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 200 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 201 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 202 u_long); 203 STATIC int gfe_hash_fill(struct gfe_softc *); 204 STATIC int gfe_hash_alloc(struct gfe_softc *); 205 206 207 CFATTACH_DECL_NEW(gfec, sizeof(struct gfec_softc), 208 gfec_match, gfec_attach, NULL, NULL); 209 CFATTACH_DECL_NEW(gfe, sizeof(struct gfe_softc), 210 gfe_match, gfe_attach, NULL, NULL); 211 212 213 /* ARGSUSED */ 214 int 215 gfec_match(device_t parent, cfdata_t cf, void *aux) 216 { 217 struct marvell_attach_args *mva = aux; 218 219 if (strcmp(mva->mva_name, cf->cf_name) != 0) 220 return 0; 221 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 222 return 0; 223 224 mva->mva_size = ETHC_SIZE; 225 return 1; 226 } 227 228 /* ARGSUSED */ 229 void 230 gfec_attach(device_t parent, device_t self, void *aux) 231 { 232 struct gfec_softc *sc = device_private(self); 233 struct marvell_attach_args *mva = aux, gfea; 234 static int gfe_irqs[] = { 32, 33, 34 }; 235 int i; 236 237 aprint_naive("\n"); 238 aprint_normal(": Ethernet Controller\n"); 239 240 sc->sc_dev = self; 241 sc->sc_iot = mva->mva_iot; 242 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 243 mva->mva_size, &sc->sc_ioh)) { 244 aprint_error_dev(self, "Cannot map registers\n"); 245 return; 246 } 247 248 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 249 250 for (i = 0; i < ETH_NUM; i++) { 251 gfea.mva_name = "gfe"; 252 gfea.mva_model = mva->mva_model; 253 gfea.mva_iot = sc->sc_iot; 254 gfea.mva_ioh = sc->sc_ioh; 255 gfea.mva_unit = i; 256 gfea.mva_dmat = mva->mva_dmat; 257 gfea.mva_irq = gfe_irqs[i]; 258 config_found_sm_loc(sc->sc_dev, "gfec", NULL, &gfea, 259 gfec_print, gfec_search); 260 } 261 } 262 263 int 264 gfec_print(void *aux, const char *pnp) 265 { 266 struct marvell_attach_args *gfea = aux; 267 268 if (pnp) 269 aprint_normal("%s at %s port %d", 270 gfea->mva_name, pnp, gfea->mva_unit); 271 else { 272 if (gfea->mva_unit != GFECCF_PORT_DEFAULT) 273 aprint_normal(" port %d", gfea->mva_unit); 274 if (gfea->mva_irq != GFECCF_IRQ_DEFAULT) 275 aprint_normal(" irq %d", gfea->mva_irq); 276 } 277 return UNCONF; 278 } 279 280 /* ARGSUSED */ 281 int 282 gfec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 283 { 284 struct marvell_attach_args *gfea = aux; 285 286 if (cf->cf_loc[GFECCF_PORT] == gfea->mva_unit && 287 cf->cf_loc[GFECCF_IRQ] != GFECCF_IRQ_DEFAULT) 288 gfea->mva_irq = cf->cf_loc[GFECCF_IRQ]; 289 290 return config_match(parent, cf, aux); 291 } 292 293 int 294 gfec_enet_phy(device_t dev, int unit) 295 { 296 struct gfec_softc *sc = device_private(dev); 297 uint32_t epar; 298 299 epar = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ETH_EPAR); 300 return ETH_EPAR_PhyAD_GET(epar, unit); 301 } 302 303 int 304 gfec_mii_read(device_t dev, int phy, int reg) 305 { 306 struct gfec_softc *csc = device_private(device_parent(dev)); 307 uint32_t data; 308 int count = 10000; 309 310 mutex_enter(&csc->sc_mtx); 311 312 do { 313 DELAY(10); 314 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 315 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 316 317 if (count == 0) { 318 aprint_error_dev(dev, 319 "mii read for phy %d reg %d busied out\n", phy, reg); 320 mutex_exit(&csc->sc_mtx); 321 return ETH_ESMIR_Value_GET(data); 322 } 323 324 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 325 ETH_ESMIR_READ(phy, reg)); 326 327 count = 10000; 328 do { 329 DELAY(10); 330 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 331 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0); 332 333 mutex_exit(&csc->sc_mtx); 334 335 if (count == 0) 336 aprint_error_dev(dev, 337 "mii read for phy %d reg %d timed out\n", phy, reg); 338 #if defined(GTMIIDEBUG) 339 aprint_normal_dev(dev, "mii_read(%d, %d): %#x data %#x\n", 340 phy, reg, data, ETH_ESMIR_Value_GET(data)); 341 #endif 342 return ETH_ESMIR_Value_GET(data); 343 } 344 345 void 346 gfec_mii_write (device_t dev, int phy, int reg, int value) 347 { 348 struct gfec_softc *csc = device_private(device_parent(dev)); 349 uint32_t data; 350 int count = 10000; 351 352 mutex_enter(&csc->sc_mtx); 353 354 do { 355 DELAY(10); 356 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 357 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 358 359 if (count == 0) { 360 aprint_error_dev(dev, 361 "mii write for phy %d reg %d busied out (busy)\n", 362 phy, reg); 363 mutex_exit(&csc->sc_mtx); 364 return; 365 } 366 367 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR, 368 ETH_ESMIR_WRITE(phy, reg, value)); 369 370 count = 10000; 371 do { 372 DELAY(10); 373 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR); 374 } while ((data & ETH_ESMIR_Busy) && count-- > 0); 375 376 mutex_exit(&csc->sc_mtx); 377 378 if (count == 0) 379 aprint_error_dev(dev, 380 "mii write for phy %d reg %d timed out\n", phy, reg); 381 #if defined(GTMIIDEBUG) 382 aprint_normal_dev(dev, "mii_write(%d, %d, %#x)\n", phy, reg, value); 383 #endif 384 } 385 386 void 387 gfec_mii_statchg(device_t dev) 388 { 389 /* struct gfe_softc *sc = device_private(self); */ 390 /* do nothing? */ 391 } 392 393 /* ARGSUSED */ 394 int 395 gfe_match(device_t parent, cfdata_t cf, void *aux) 396 { 397 398 return 1; 399 } 400 401 /* ARGSUSED */ 402 void 403 gfe_attach(device_t parent, device_t self, void *aux) 404 { 405 struct marvell_attach_args *mva = aux; 406 struct gfe_softc * const sc = device_private(self); 407 struct ifnet * const ifp = &sc->sc_ec.ec_if; 408 uint32_t sdcr; 409 int phyaddr, error; 410 prop_data_t ea; 411 uint8_t enaddr[6]; 412 413 aprint_naive("\n"); 414 aprint_normal(": Ethernet Controller\n"); 415 416 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 417 mva->mva_offset, mva->mva_size, &sc->sc_memh)) { 418 aprint_error_dev(self, "failed to map registers\n"); 419 return; 420 } 421 sc->sc_dev = self; 422 sc->sc_memt = mva->mva_iot; 423 sc->sc_dmat = mva->mva_dmat; 424 sc->sc_macno = (mva->mva_offset == ETH_BASE(0)) ? 0 : 425 ((mva->mva_offset == ETH_BASE(1)) ? 1 : 2); 426 427 callout_init(&sc->sc_co, 0); 428 429 phyaddr = gfec_enet_phy(parent, sc->sc_macno); 430 431 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-addr"); 432 if (ea != NULL) { 433 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 434 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 435 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN); 436 } 437 438 sc->sc_pcr = GE_READ(sc, ETH_EPCR); 439 sc->sc_pcxr = GE_READ(sc, ETH_EPCXR); 440 sc->sc_intrmask = GE_READ(sc, ETH_EIMR) | ETH_IR_MIIPhySTC; 441 442 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 443 444 #if defined(DEBUG) 445 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 446 #endif 447 448 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 449 if (device_cfdata(self)->cf_flags & 1) { 450 aprint_normal_dev(self, "phy %d (rmii)\n", phyaddr); 451 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 452 } else { 453 aprint_normal_dev(self, "phy %d (mii)\n", phyaddr); 454 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 455 } 456 if (device_cfdata(self)->cf_flags & 2) 457 sc->sc_flags |= GE_NOFREE; 458 /* Set Max Frame Length is 1536 */ 459 sc->sc_pcxr &= ~ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_MASK); 460 sc->sc_pcxr |= ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_1536); 461 sc->sc_max_frame_length = 1536; 462 463 if (sc->sc_pcr & ETH_EPCR_EN) { 464 int tries = 1000; 465 /* 466 * Abort transmitter and receiver and wait for them to quiese 467 */ 468 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR | ETH_ESDCMR_AT); 469 do { 470 delay(100); 471 if (tries-- <= 0) { 472 aprint_error_dev(self, "Abort TX/RX failed\n"); 473 break; 474 } 475 } while (GE_READ(sc, ETH_ESDCMR) & 476 (ETH_ESDCMR_AR | ETH_ESDCMR_AT)); 477 } 478 479 sc->sc_pcr &= 480 ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 481 482 #if defined(DEBUG) 483 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr); 484 #endif 485 486 /* 487 * Now turn off the GT. If it didn't quiese, too ***ing bad. 488 */ 489 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 490 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 491 sdcr = GE_READ(sc, ETH_ESDCR); 492 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 493 sdcr |= ETH_ESDCR_RIFB; 494 GE_WRITE(sc, ETH_ESDCR, sdcr); 495 496 sc->sc_mii.mii_ifp = ifp; 497 sc->sc_mii.mii_readreg = gfec_mii_read; 498 sc->sc_mii.mii_writereg = gfec_mii_write; 499 sc->sc_mii.mii_statchg = gfec_mii_statchg; 500 501 sc->sc_ec.ec_mii = &sc->sc_mii; 502 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 503 ether_mediastatus); 504 505 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 506 MII_OFFSET_ANY, MIIF_NOISOLATE); 507 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 508 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 509 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 510 } else { 511 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 512 } 513 514 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 515 ifp->if_softc = sc; 516 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 517 #if 0 518 ifp->if_flags |= IFF_DEBUG; 519 #endif 520 ifp->if_ioctl = gfe_ifioctl; 521 ifp->if_start = gfe_ifstart; 522 ifp->if_watchdog = gfe_ifwatchdog; 523 524 if (sc->sc_flags & GE_NOFREE) { 525 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 526 if (!error) 527 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 528 if (!error) 529 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 530 if (!error) 531 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 532 if (!error) 533 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 534 if (!error) 535 error = gfe_hash_alloc(sc); 536 if (error) 537 aprint_error_dev(self, 538 "failed to allocate resources: %d\n", error); 539 } 540 541 if_attach(ifp); 542 ether_ifattach(ifp, enaddr); 543 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 544 #if NRND > 0 545 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 546 0); 547 #endif 548 marvell_intr_establish(mva->mva_irq, IPL_NET, gfe_intr, sc); 549 } 550 551 int 552 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 553 size_t size, int flags) 554 { 555 int error = 0; 556 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 557 558 KASSERT(gdm->gdm_kva == NULL); 559 gdm->gdm_size = size; 560 gdm->gdm_maxsegs = maxsegs; 561 562 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 563 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 564 BUS_DMA_NOWAIT); 565 if (error) 566 goto fail; 567 568 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 569 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 570 if (error) 571 goto fail; 572 573 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 574 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 575 if (error) 576 goto fail; 577 578 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 579 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 580 if (error) 581 goto fail; 582 583 /* invalidate from cache */ 584 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 585 BUS_DMASYNC_PREREAD); 586 fail: 587 if (error) { 588 gfe_dmamem_free(sc, gdm); 589 GE_DPRINTF(sc, (":err=%d", error)); 590 } 591 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 592 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 593 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 594 GE_FUNC_EXIT(sc, ""); 595 return error; 596 } 597 598 void 599 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 600 { 601 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 602 if (gdm->gdm_map) 603 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 604 if (gdm->gdm_kva) 605 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 606 if (gdm->gdm_nsegs > 0) 607 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 608 gdm->gdm_map = NULL; 609 gdm->gdm_kva = NULL; 610 gdm->gdm_nsegs = 0; 611 GE_FUNC_EXIT(sc, ""); 612 } 613 614 int 615 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 616 { 617 struct gfe_softc * const sc = ifp->if_softc; 618 struct ifreq *ifr = (struct ifreq *) data; 619 struct ifaddr *ifa = (struct ifaddr *) data; 620 int s, error = 0; 621 622 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 623 s = splnet(); 624 625 switch (cmd) { 626 case SIOCINITIFADDR: 627 ifp->if_flags |= IFF_UP; 628 error = gfe_whack(sc, GE_WHACK_START); 629 switch (ifa->ifa_addr->sa_family) { 630 #ifdef INET 631 case AF_INET: 632 if (error == 0) 633 arp_ifinit(ifp, ifa); 634 break; 635 #endif 636 default: 637 break; 638 } 639 break; 640 641 case SIOCSIFFLAGS: 642 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 643 break; 644 /* XXX re-use ether_ioctl() */ 645 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 646 case IFF_UP|IFF_RUNNING:/* active->active, update */ 647 error = gfe_whack(sc, GE_WHACK_CHANGE); 648 break; 649 case IFF_RUNNING: /* not up, so we stop */ 650 error = gfe_whack(sc, GE_WHACK_STOP); 651 break; 652 case IFF_UP: /* not running, so we start */ 653 error = gfe_whack(sc, GE_WHACK_START); 654 break; 655 case 0: /* idle->idle: do nothing */ 656 break; 657 } 658 break; 659 660 case SIOCSIFMEDIA: 661 case SIOCGIFMEDIA: 662 case SIOCADDMULTI: 663 case SIOCDELMULTI: 664 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 665 if (ifp->if_flags & IFF_RUNNING) 666 error = gfe_whack(sc, GE_WHACK_CHANGE); 667 else 668 error = 0; 669 } 670 break; 671 672 case SIOCSIFMTU: 673 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 674 error = EINVAL; 675 break; 676 } 677 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 678 error = 0; 679 break; 680 681 default: 682 error = ether_ioctl(ifp, cmd, data); 683 break; 684 } 685 splx(s); 686 GE_FUNC_EXIT(sc, ""); 687 return error; 688 } 689 690 void 691 gfe_ifstart(struct ifnet *ifp) 692 { 693 struct gfe_softc * const sc = ifp->if_softc; 694 struct mbuf *m; 695 696 GE_FUNC_ENTER(sc, "gfe_ifstart"); 697 698 if ((ifp->if_flags & IFF_RUNNING) == 0) { 699 GE_FUNC_EXIT(sc, "$"); 700 return; 701 } 702 703 for (;;) { 704 IF_DEQUEUE(&ifp->if_snd, m); 705 if (m == NULL) { 706 ifp->if_flags &= ~IFF_OACTIVE; 707 GE_FUNC_EXIT(sc, ""); 708 return; 709 } 710 711 /* 712 * No space in the pending queue? try later. 713 */ 714 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 715 break; 716 717 /* 718 * Try to enqueue a mbuf to the device. If that fails, we 719 * can always try to map the next mbuf. 720 */ 721 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 722 GE_DPRINTF(sc, (">")); 723 #ifndef GE_NOTX 724 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 725 #endif 726 } 727 728 /* 729 * Attempt to queue the mbuf for send failed. 730 */ 731 IF_PREPEND(&ifp->if_snd, m); 732 ifp->if_flags |= IFF_OACTIVE; 733 GE_FUNC_EXIT(sc, "%%"); 734 } 735 736 void 737 gfe_ifwatchdog(struct ifnet *ifp) 738 { 739 struct gfe_softc * const sc = ifp->if_softc; 740 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 741 742 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 743 aprint_error_dev(sc->sc_dev, "device timeout"); 744 if (ifp->if_flags & IFF_RUNNING) { 745 uint32_t curtxdnum; 746 747 curtxdnum = (GE_READ(sc, txq->txq_ectdp) - 748 txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 749 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 750 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 751 aprint_error(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 752 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 753 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 754 GE_READ(sc, ETH_EICR)); 755 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 756 GE_TXDPRESYNC(sc, txq, curtxdnum); 757 } 758 aprint_error("\n"); 759 ifp->if_oerrors++; 760 (void) gfe_whack(sc, GE_WHACK_RESTART); 761 GE_FUNC_EXIT(sc, ""); 762 } 763 764 int 765 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 766 { 767 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 768 int error; 769 770 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 771 GE_DPRINTF(sc, ("(%d)", rxprio)); 772 773 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 774 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 775 if (error) { 776 GE_FUNC_EXIT(sc, "!!"); 777 return error; 778 } 779 780 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 781 GE_RXBUF_MEMSIZE, 0); 782 if (error) { 783 GE_FUNC_EXIT(sc, "!!!"); 784 return error; 785 } 786 GE_FUNC_EXIT(sc, ""); 787 return error; 788 } 789 790 int 791 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 792 { 793 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 794 volatile struct gt_eth_desc *rxd; 795 const bus_dma_segment_t *ds; 796 int idx; 797 bus_addr_t nxtaddr; 798 bus_size_t boff; 799 800 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 801 GE_DPRINTF(sc, ("(%d)", rxprio)); 802 803 if ((sc->sc_flags & GE_NOFREE) == 0) { 804 int error = gfe_rx_rxqalloc(sc, rxprio); 805 if (error) { 806 GE_FUNC_EXIT(sc, "!"); 807 return error; 808 } 809 } else { 810 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 811 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 812 } 813 814 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 815 816 rxq->rxq_descs = 817 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 818 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 819 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 820 rxq->rxq_fi = 0; 821 rxq->rxq_active = GE_RXDESC_MAX; 822 boff = 0; 823 ds = rxq->rxq_buf_mem.gdm_map->dm_segs; 824 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 825 for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX; 826 idx++, nxtaddr += sizeof(*(++rxd))) { 827 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 828 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 829 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 830 /* 831 * update the nxtptr to point to the next txd. 832 */ 833 if (idx == GE_RXDESC_MAX - 1) 834 nxtaddr = rxq->rxq_desc_busaddr; 835 rxd->ed_nxtptr = htogt32(nxtaddr); 836 boff += GE_RXBUF_SIZE; 837 if (boff == ds->ds_len) { 838 ds++; 839 boff = 0; 840 } 841 } 842 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 843 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 844 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 845 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 846 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 847 BUS_DMASYNC_PREREAD); 848 849 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 850 switch (rxprio) { 851 case GE_RXPRIO_HI: 852 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 853 rxq->rxq_efrdp = ETH_EFRDP3; 854 rxq->rxq_ecrdp = ETH_ECRDP3; 855 break; 856 case GE_RXPRIO_MEDHI: 857 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 858 rxq->rxq_efrdp = ETH_EFRDP2; 859 rxq->rxq_ecrdp = ETH_ECRDP2; 860 break; 861 case GE_RXPRIO_MEDLO: 862 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 863 rxq->rxq_efrdp = ETH_EFRDP1; 864 rxq->rxq_ecrdp = ETH_ECRDP1; 865 break; 866 case GE_RXPRIO_LO: 867 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 868 rxq->rxq_efrdp = ETH_EFRDP0; 869 rxq->rxq_ecrdp = ETH_ECRDP0; 870 break; 871 } 872 GE_FUNC_EXIT(sc, ""); 873 return 0; 874 } 875 876 void 877 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 878 { 879 struct ifnet * const ifp = &sc->sc_ec.ec_if; 880 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 881 struct mbuf *m = rxq->rxq_curpkt; 882 883 GE_FUNC_ENTER(sc, "gfe_rx_get"); 884 GE_DPRINTF(sc, ("(%d)", rxprio)); 885 886 while (rxq->rxq_active > 0) { 887 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 888 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 889 const struct ether_header *eh; 890 unsigned int cmdsts; 891 size_t buflen; 892 893 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 894 cmdsts = gt32toh(rxd->ed_cmdsts); 895 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 896 rxq->rxq_cmdsts = cmdsts; 897 /* 898 * Sometimes the GE "forgets" to reset the ownership bit. 899 * But if the length has been rewritten, the packet is ours 900 * so pretend the O bit is set. 901 */ 902 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 903 if ((cmdsts & RX_CMD_O) && buflen == 0) { 904 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 905 break; 906 } 907 908 /* 909 * If this is not a single buffer packet with no errors 910 * or for some reason it's bigger than our frame size, 911 * ignore it and go to the next packet. 912 */ 913 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 914 (RX_CMD_F|RX_CMD_L) || 915 buflen > sc->sc_max_frame_length) { 916 GE_DPRINTF(sc, ("!")); 917 --rxq->rxq_active; 918 ifp->if_ipackets++; 919 ifp->if_ierrors++; 920 goto give_it_back; 921 } 922 923 /* CRC is included with the packet; trim it off. */ 924 buflen -= ETHER_CRC_LEN; 925 926 if (m == NULL) { 927 MGETHDR(m, M_DONTWAIT, MT_DATA); 928 if (m == NULL) { 929 GE_DPRINTF(sc, ("?")); 930 break; 931 } 932 } 933 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 934 MCLGET(m, M_DONTWAIT); 935 if ((m->m_flags & M_EXT) == 0) { 936 GE_DPRINTF(sc, ("?")); 937 break; 938 } 939 } 940 m->m_data += 2; 941 m->m_len = 0; 942 m->m_pkthdr.len = 0; 943 m->m_pkthdr.rcvif = ifp; 944 rxq->rxq_cmdsts = cmdsts; 945 --rxq->rxq_active; 946 947 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 948 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 949 950 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 951 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 952 m->m_len = buflen; 953 m->m_pkthdr.len = buflen; 954 955 ifp->if_ipackets++; 956 bpf_mtap(ifp, m); 957 958 eh = (const struct ether_header *) m->m_data; 959 if ((ifp->if_flags & IFF_PROMISC) || 960 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 961 (rxq->rxq_cmdsts & RX_STS_HE) || 962 (eh->ether_dhost[0] & 1) != 0 || 963 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 964 ETHER_ADDR_LEN) == 0) { 965 (*ifp->if_input)(ifp, m); 966 m = NULL; 967 GE_DPRINTF(sc, (">")); 968 } else { 969 m->m_len = 0; 970 m->m_pkthdr.len = 0; 971 GE_DPRINTF(sc, ("+")); 972 } 973 rxq->rxq_cmdsts = 0; 974 975 give_it_back: 976 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 977 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 978 #if 0 979 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 980 rxq->rxq_fi, 981 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 982 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 983 #endif 984 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 985 if (++rxq->rxq_fi == GE_RXDESC_MAX) 986 rxq->rxq_fi = 0; 987 rxq->rxq_active++; 988 } 989 rxq->rxq_curpkt = m; 990 GE_FUNC_EXIT(sc, ""); 991 } 992 993 uint32_t 994 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 995 { 996 struct ifnet * const ifp = &sc->sc_ec.ec_if; 997 struct gfe_rxqueue *rxq; 998 uint32_t rxbits; 999 #define RXPRIO_DECODER 0xffffaa50 1000 GE_FUNC_ENTER(sc, "gfe_rx_process"); 1001 1002 rxbits = ETH_IR_RxBuffer_GET(cause); 1003 while (rxbits) { 1004 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 1005 GE_DPRINTF(sc, ("%1x", rxbits)); 1006 rxbits &= ~(1 << rxprio); 1007 gfe_rx_get(sc, rxprio); 1008 } 1009 1010 rxbits = ETH_IR_RxError_GET(cause); 1011 while (rxbits) { 1012 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 1013 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 1014 int idx; 1015 rxbits &= ~(1 << rxprio); 1016 rxq = &sc->sc_rxq[rxprio]; 1017 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 1018 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 1019 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 1020 sc->sc_tickflags |= GE_TICK_RX_RESTART; 1021 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 1022 } 1023 ifp->if_ierrors++; 1024 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 1025 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi)); 1026 memset(masks, 0, sizeof(masks)); 1027 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1028 0, rxq->rxq_desc_mem.gdm_size, 1029 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1030 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 1031 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 1032 1033 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 1034 masks[idx/32] |= 1 << (idx & 31); 1035 } 1036 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 1037 0, rxq->rxq_desc_mem.gdm_size, 1038 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1039 #if defined(DEBUG) 1040 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 1041 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi, 1042 rxq->rxq_cmdsts, masks[0], masks[1]); 1043 #endif 1044 } 1045 if ((intrmask & ETH_IR_RxBits) == 0) 1046 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 1047 1048 GE_FUNC_EXIT(sc, ""); 1049 return intrmask; 1050 } 1051 1052 int 1053 gfe_rx_prime(struct gfe_softc *sc) 1054 { 1055 struct gfe_rxqueue *rxq; 1056 int error; 1057 1058 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 1059 1060 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 1061 if (error) 1062 goto bail; 1063 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1064 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1065 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1066 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1067 } 1068 sc->sc_intrmask |= rxq->rxq_intrbits; 1069 1070 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 1071 if (error) 1072 goto bail; 1073 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1074 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1075 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1076 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1077 sc->sc_intrmask |= rxq->rxq_intrbits; 1078 } 1079 1080 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 1081 if (error) 1082 goto bail; 1083 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1084 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1085 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1086 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1087 sc->sc_intrmask |= rxq->rxq_intrbits; 1088 } 1089 1090 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 1091 if (error) 1092 goto bail; 1093 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 1094 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1095 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1096 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1097 sc->sc_intrmask |= rxq->rxq_intrbits; 1098 } 1099 1100 bail: 1101 GE_FUNC_EXIT(sc, ""); 1102 return error; 1103 } 1104 1105 void 1106 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 1107 { 1108 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 1109 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 1110 if (rxq == NULL) { 1111 GE_FUNC_EXIT(sc, ""); 1112 return; 1113 } 1114 1115 if (rxq->rxq_curpkt) 1116 m_freem(rxq->rxq_curpkt); 1117 if ((sc->sc_flags & GE_NOFREE) == 0) { 1118 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 1119 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 1120 } 1121 GE_FUNC_EXIT(sc, ""); 1122 } 1123 1124 void 1125 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1126 { 1127 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 1128 sc->sc_flags &= ~GE_RXACTIVE; 1129 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1130 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 1131 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1132 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR); 1133 do { 1134 delay(10); 1135 } while (GE_READ(sc, ETH_ESDCMR) & ETH_ESDCMR_AR); 1136 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 1137 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 1138 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 1139 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 1140 GE_FUNC_EXIT(sc, ""); 1141 } 1142 1143 void 1144 gfe_tick(void *arg) 1145 { 1146 struct gfe_softc * const sc = arg; 1147 uint32_t intrmask; 1148 unsigned int tickflags; 1149 int s; 1150 1151 GE_FUNC_ENTER(sc, "gfe_tick"); 1152 1153 s = splnet(); 1154 1155 tickflags = sc->sc_tickflags; 1156 sc->sc_tickflags = 0; 1157 intrmask = sc->sc_intrmask; 1158 if (tickflags & GE_TICK_TX_IFSTART) 1159 gfe_ifstart(&sc->sc_ec.ec_if); 1160 if (tickflags & GE_TICK_RX_RESTART) { 1161 intrmask |= sc->sc_idlemask; 1162 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 1163 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 1164 rxq->rxq_fi = 0; 1165 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr); 1166 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr); 1167 } 1168 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 1169 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 1170 rxq->rxq_fi = 0; 1171 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr); 1172 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr); 1173 } 1174 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 1175 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 1176 rxq->rxq_fi = 0; 1177 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr); 1178 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr); 1179 } 1180 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 1181 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 1182 rxq->rxq_fi = 0; 1183 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr); 1184 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr); 1185 } 1186 sc->sc_idlemask = 0; 1187 } 1188 if (intrmask != sc->sc_intrmask) { 1189 sc->sc_intrmask = intrmask; 1190 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1191 } 1192 gfe_intr(sc); 1193 splx(s); 1194 1195 GE_FUNC_EXIT(sc, ""); 1196 } 1197 1198 int 1199 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1200 { 1201 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1202 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1203 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1204 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1205 uint32_t intrmask = sc->sc_intrmask; 1206 size_t buflen; 1207 struct mbuf *m; 1208 1209 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1210 1211 /* 1212 * Anything in the pending queue to enqueue? if not, punt. Likewise 1213 * if the txq is not yet created. 1214 * otherwise grab its dmamap. 1215 */ 1216 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1217 GE_FUNC_EXIT(sc, "-"); 1218 return 0; 1219 } 1220 1221 /* 1222 * Have we [over]consumed our limit of descriptors? 1223 * Do we have enough free descriptors? 1224 */ 1225 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1226 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1227 uint32_t cmdsts; 1228 size_t pktlen; 1229 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1230 cmdsts = gt32toh(txd2->ed_cmdsts); 1231 if (cmdsts & TX_CMD_O) { 1232 int nextin; 1233 /* 1234 * Sometime the Discovery forgets to update the 1235 * last descriptor. See if we own the descriptor 1236 * after it (since we know we've turned that to 1237 * the discovery and if we owned it, the Discovery 1238 * gave it back). If we do, we know the Discovery 1239 * gave back this one but forgot to mark it as ours. 1240 */ 1241 nextin = txq->txq_fi + 1; 1242 if (nextin == GE_TXDESC_MAX) 1243 nextin = 0; 1244 GE_TXDPOSTSYNC(sc, txq, nextin); 1245 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1246 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1247 GE_TXDPRESYNC(sc, txq, nextin); 1248 GE_FUNC_EXIT(sc, "@"); 1249 return 0; 1250 } 1251 #ifdef DEBUG 1252 printf("%s: txenqueue: transmitter resynced at %d\n", 1253 device_xname(sc->sc_dev), txq->txq_fi); 1254 #endif 1255 } 1256 if (++txq->txq_fi == GE_TXDESC_MAX) 1257 txq->txq_fi = 0; 1258 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1259 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1260 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1261 txq->txq_nactive--; 1262 1263 /* statistics */ 1264 ifp->if_opackets++; 1265 if (cmdsts & TX_STS_ES) 1266 ifp->if_oerrors++; 1267 GE_DPRINTF(sc, ("%%")); 1268 } 1269 1270 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1271 1272 /* 1273 * If this packet would wrap around the end of the buffer, reset back 1274 * to the beginning. 1275 */ 1276 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1277 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1278 txq->txq_outptr = 0; 1279 } 1280 1281 /* 1282 * Make sure the output packet doesn't run over the beginning of 1283 * what we've already given the GT. 1284 */ 1285 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1286 txq->txq_outptr + buflen > txq->txq_inptr) { 1287 intrmask |= txq->txq_intrbits & 1288 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1289 if (sc->sc_intrmask != intrmask) { 1290 sc->sc_intrmask = intrmask; 1291 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1292 } 1293 GE_FUNC_EXIT(sc, "#"); 1294 return 0; 1295 } 1296 1297 /* 1298 * The end-of-list descriptor we put on last time is the starting point 1299 * for this packet. The GT is supposed to terminate list processing on 1300 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1301 * must terminate the list. 1302 */ 1303 intrmask = sc->sc_intrmask; 1304 1305 m_copydata(m, 0, m->m_pkthdr.len, 1306 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1307 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1308 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1309 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1310 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1311 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1312 1313 /* 1314 * Request a buffer interrupt every 2/3 of the way thru the transmit 1315 * buffer. 1316 */ 1317 txq->txq_ei_gapcount += buflen; 1318 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1319 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1320 txq->txq_ei_gapcount = 0; 1321 } else { 1322 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1323 } 1324 #if 0 1325 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1326 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1327 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1328 #endif 1329 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1330 1331 txq->txq_outptr += buflen; 1332 /* 1333 * Tell the SDMA engine to "Fetch!" 1334 */ 1335 GE_WRITE(sc, ETH_ESDCMR, 1336 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1337 1338 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1339 1340 /* 1341 * Update the last out appropriately. 1342 */ 1343 txq->txq_nactive++; 1344 if (++txq->txq_lo == GE_TXDESC_MAX) 1345 txq->txq_lo = 0; 1346 1347 /* 1348 * Move mbuf from the pending queue to the snd queue. 1349 */ 1350 IF_DEQUEUE(&txq->txq_pendq, m); 1351 bpf_mtap(ifp, m); 1352 m_freem(m); 1353 ifp->if_flags &= ~IFF_OACTIVE; 1354 1355 /* 1356 * Since we have put an item into the packet queue, we now want 1357 * an interrupt when the transmit queue finishes processing the 1358 * list. But only update the mask if needs changing. 1359 */ 1360 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1361 if (sc->sc_intrmask != intrmask) { 1362 sc->sc_intrmask = intrmask; 1363 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1364 } 1365 if (ifp->if_timer == 0) 1366 ifp->if_timer = 5; 1367 GE_FUNC_EXIT(sc, "*"); 1368 return 1; 1369 } 1370 1371 uint32_t 1372 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1373 { 1374 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1375 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1376 1377 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1378 1379 if (txq == NULL) { 1380 GE_FUNC_EXIT(sc, ""); 1381 return intrmask; 1382 } 1383 1384 while (txq->txq_nactive > 0) { 1385 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1386 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1387 uint32_t cmdsts; 1388 size_t pktlen; 1389 1390 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1391 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1392 int nextin; 1393 1394 if (txq->txq_nactive == 1) { 1395 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1396 GE_FUNC_EXIT(sc, ""); 1397 return intrmask; 1398 } 1399 /* 1400 * Sometimes the Discovery forgets to update the 1401 * ownership bit in the descriptor. See if we own the 1402 * descriptor after it (since we know we've turned 1403 * that to the Discovery and if we own it now then the 1404 * Discovery gave it back). If we do, we know the 1405 * Discovery gave back this one but forgot to mark it 1406 * as ours. 1407 */ 1408 nextin = txq->txq_fi + 1; 1409 if (nextin == GE_TXDESC_MAX) 1410 nextin = 0; 1411 GE_TXDPOSTSYNC(sc, txq, nextin); 1412 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1413 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1414 GE_TXDPRESYNC(sc, txq, nextin); 1415 GE_FUNC_EXIT(sc, ""); 1416 return intrmask; 1417 } 1418 #ifdef DEBUG 1419 printf("%s: txdone: transmitter resynced at %d\n", 1420 device_xname(sc->sc_dev), txq->txq_fi); 1421 #endif 1422 } 1423 #if 0 1424 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1425 txq->txq_lo, 1426 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1427 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1428 #endif 1429 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1430 if (++txq->txq_fi == GE_TXDESC_MAX) 1431 txq->txq_fi = 0; 1432 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1433 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1434 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1435 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1436 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1437 1438 /* statistics */ 1439 ifp->if_opackets++; 1440 if (cmdsts & TX_STS_ES) 1441 ifp->if_oerrors++; 1442 1443 /* txd->ed_bufptr = 0; */ 1444 1445 ifp->if_timer = 5; 1446 --txq->txq_nactive; 1447 } 1448 if (txq->txq_nactive != 0) 1449 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1450 device_xname(sc->sc_dev), txprio, txq->txq_nactive); 1451 ifp->if_timer = 0; 1452 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1453 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1454 GE_FUNC_EXIT(sc, ""); 1455 return intrmask; 1456 } 1457 1458 int 1459 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1460 { 1461 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1462 int error; 1463 1464 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1465 1466 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1467 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1468 if (error) { 1469 GE_FUNC_EXIT(sc, ""); 1470 return error; 1471 } 1472 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1473 if (error) { 1474 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1475 GE_FUNC_EXIT(sc, ""); 1476 return error; 1477 } 1478 GE_FUNC_EXIT(sc, ""); 1479 return 0; 1480 } 1481 1482 int 1483 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1484 { 1485 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1486 volatile struct gt_eth_desc *txd; 1487 unsigned int i; 1488 bus_addr_t addr; 1489 1490 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1491 1492 sc->sc_intrmask &= 1493 ~(ETH_IR_TxEndHigh | 1494 ETH_IR_TxBufferHigh | 1495 ETH_IR_TxEndLow | 1496 ETH_IR_TxBufferLow); 1497 1498 if (sc->sc_flags & GE_NOFREE) { 1499 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1500 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1501 } else { 1502 int error = gfe_tx_txqalloc(sc, txprio); 1503 if (error) { 1504 GE_FUNC_EXIT(sc, "!"); 1505 return error; 1506 } 1507 } 1508 1509 txq->txq_descs = 1510 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1511 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1512 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1513 1514 txq->txq_pendq.ifq_maxlen = 10; 1515 txq->txq_ei_gapcount = 0; 1516 txq->txq_nactive = 0; 1517 txq->txq_fi = 0; 1518 txq->txq_lo = 0; 1519 txq->txq_inptr = GE_TXBUF_SIZE; 1520 txq->txq_outptr = 0; 1521 for (i = 0, txd = txq->txq_descs, 1522 addr = txq->txq_desc_busaddr + sizeof(*txd); 1523 i < GE_TXDESC_MAX - 1; i++, txd++, addr += sizeof(*txd)) { 1524 /* 1525 * update the nxtptr to point to the next txd. 1526 */ 1527 txd->ed_cmdsts = 0; 1528 txd->ed_nxtptr = htogt32(addr); 1529 } 1530 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1531 htogt32(txq->txq_desc_busaddr); 1532 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1533 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1534 1535 switch (txprio) { 1536 case GE_TXPRIO_HI: 1537 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1538 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1539 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1540 txq->txq_ectdp = ETH_ECTDP1; 1541 GE_WRITE(sc, ETH_ECTDP1, txq->txq_desc_busaddr); 1542 break; 1543 1544 case GE_TXPRIO_LO: 1545 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1546 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1547 txq->txq_epsrbits = ETH_EPSR_TxLow; 1548 txq->txq_ectdp = ETH_ECTDP0; 1549 GE_WRITE(sc, ETH_ECTDP0, txq->txq_desc_busaddr); 1550 break; 1551 1552 case GE_TXPRIO_NONE: 1553 break; 1554 } 1555 #if 0 1556 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1557 GE_WRITE(sc->sc_dev, txq->txq_ectdp, txq->txq_desc_busaddr); 1558 GE_DPRINTF(sc, (")")); 1559 #endif 1560 1561 /* 1562 * If we are restarting, there may be packets in the pending queue 1563 * waiting to be enqueued. Try enqueuing packets from both priority 1564 * queues until the pending queue is empty or there no room for them 1565 * on the device. 1566 */ 1567 while (gfe_tx_enqueue(sc, txprio)) 1568 continue; 1569 1570 GE_FUNC_EXIT(sc, ""); 1571 return 0; 1572 } 1573 1574 void 1575 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1576 { 1577 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1578 1579 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1580 if (txq == NULL) { 1581 GE_FUNC_EXIT(sc, ""); 1582 return; 1583 } 1584 1585 if (!flush) { 1586 GE_FUNC_EXIT(sc, ""); 1587 return; 1588 } 1589 1590 if ((sc->sc_flags & GE_NOFREE) == 0) { 1591 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1592 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1593 } 1594 GE_FUNC_EXIT(sc, "-F"); 1595 } 1596 1597 void 1598 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1599 { 1600 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1601 1602 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1603 1604 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1605 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1606 sc->sc_intrmask &= 1607 ~(ETH_IR_TxEndHigh | 1608 ETH_IR_TxBufferHigh | 1609 ETH_IR_TxEndLow | 1610 ETH_IR_TxBufferLow); 1611 1612 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1613 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1614 1615 sc->sc_ec.ec_if.if_timer = 0; 1616 GE_FUNC_EXIT(sc, ""); 1617 } 1618 1619 int 1620 gfe_intr(void *arg) 1621 { 1622 struct gfe_softc * const sc = arg; 1623 uint32_t cause; 1624 uint32_t intrmask = sc->sc_intrmask; 1625 int claim = 0; 1626 int cnt; 1627 1628 GE_FUNC_ENTER(sc, "gfe_intr"); 1629 1630 for (cnt = 0; cnt < 4; cnt++) { 1631 if (sc->sc_intrmask != intrmask) { 1632 sc->sc_intrmask = intrmask; 1633 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1634 } 1635 cause = GE_READ(sc, ETH_EICR); 1636 cause &= sc->sc_intrmask; 1637 GE_DPRINTF(sc, (".%#x", cause)); 1638 if (cause == 0) 1639 break; 1640 1641 claim = 1; 1642 1643 GE_WRITE(sc, ETH_EICR, ~cause); 1644 #ifndef GE_NORX 1645 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1646 intrmask = gfe_rx_process(sc, cause, intrmask); 1647 #endif 1648 1649 #ifndef GE_NOTX 1650 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1651 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1652 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1653 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1654 #endif 1655 if (cause & ETH_IR_MIIPhySTC) { 1656 sc->sc_flags |= GE_PHYSTSCHG; 1657 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1658 } 1659 } 1660 1661 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1662 continue; 1663 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1664 continue; 1665 1666 GE_FUNC_EXIT(sc, ""); 1667 return claim; 1668 } 1669 1670 int 1671 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1672 { 1673 int error = 0; 1674 GE_FUNC_ENTER(sc, "gfe_whack"); 1675 1676 switch (op) { 1677 case GE_WHACK_RESTART: 1678 #ifndef GE_NOTX 1679 gfe_tx_stop(sc, op); 1680 #endif 1681 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1682 /* FALLTHROUGH */ 1683 case GE_WHACK_START: 1684 #ifndef GE_NOHASH 1685 if (error == 0 && sc->sc_hashtable == NULL) { 1686 error = gfe_hash_alloc(sc); 1687 if (error) 1688 break; 1689 } 1690 if (op != GE_WHACK_RESTART) 1691 gfe_hash_fill(sc); 1692 #endif 1693 #ifndef GE_NORX 1694 if (op != GE_WHACK_RESTART) { 1695 error = gfe_rx_prime(sc); 1696 if (error) 1697 break; 1698 } 1699 #endif 1700 #ifndef GE_NOTX 1701 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1702 if (error) 1703 break; 1704 #endif 1705 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1706 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1707 GE_WRITE(sc, ETH_EPCXR, sc->sc_pcxr); 1708 GE_WRITE(sc, ETH_EICR, 0); 1709 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1710 #ifndef GE_NOHASH 1711 GE_WRITE(sc, ETH_EHTPR, 1712 sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1713 #endif 1714 #ifndef GE_NORX 1715 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_ERD); 1716 sc->sc_flags |= GE_RXACTIVE; 1717 #endif 1718 /* FALLTHROUGH */ 1719 case GE_WHACK_CHANGE: 1720 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1721 GE_READ(sc, ETH_EPCR), GE_READ(sc, ETH_EIMR))); 1722 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN); 1723 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask); 1724 gfe_ifstart(&sc->sc_ec.ec_if); 1725 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1726 GE_READ(sc, ETH_ECTDP0), GE_READ(sc, ETH_ECTDP1))); 1727 GE_FUNC_EXIT(sc, ""); 1728 return error; 1729 case GE_WHACK_STOP: 1730 break; 1731 } 1732 1733 #ifdef GE_DEBUG 1734 if (error) 1735 GE_DPRINTF(sc, (" failed: %d\n", error)); 1736 #endif 1737 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1738 GE_WRITE(sc, ETH_EIMR, 0); 1739 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1740 #ifndef GE_NOTX 1741 gfe_tx_stop(sc, GE_WHACK_STOP); 1742 #endif 1743 #ifndef GE_NORX 1744 gfe_rx_stop(sc, GE_WHACK_STOP); 1745 #endif 1746 #ifndef GE_NOHASH 1747 if ((sc->sc_flags & GE_NOFREE) == 0) { 1748 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1749 sc->sc_hashtable = NULL; 1750 } 1751 #endif 1752 1753 GE_FUNC_EXIT(sc, ""); 1754 return error; 1755 } 1756 1757 int 1758 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1759 { 1760 uint32_t w0, add0, add1; 1761 uint32_t result; 1762 1763 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1764 add0 = ((uint32_t) eaddr[5] << 0) | 1765 ((uint32_t) eaddr[4] << 8) | 1766 ((uint32_t) eaddr[3] << 16); 1767 1768 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1769 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1770 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1771 1772 add1 = ((uint32_t) eaddr[2] << 0) | 1773 ((uint32_t) eaddr[1] << 8) | 1774 ((uint32_t) eaddr[0] << 16); 1775 1776 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1777 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1778 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1779 1780 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1781 /* 1782 * hashResult is the 15 bits Hash entry address. 1783 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1784 * MAC address, by nibble swapping in every byte (i.e MAC address 1785 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1786 */ 1787 1788 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1789 /* 1790 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1791 * 1792 * hashFunc0 calculates the hashResult in the following manner: 1793 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1794 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1795 */ 1796 result = (add0 & 3) | ((add0 >> 6) & ~3); 1797 result ^= (add0 >> 15) ^ (add1 >> 0); 1798 result &= 0x1ff; 1799 /* 1800 * hashResult[14:9] = ethernetADD[7:2] 1801 */ 1802 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1803 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1804 } else { 1805 #define TRIBITFLIP 073516240 /* yes its in octal */ 1806 /* 1807 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1808 * 1809 * hashFunc1 calculates the hashResult in the following manner: 1810 * hashResult[08:00] = ethernetADD[06:14] 1811 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1812 */ 1813 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1814 /* 1815 * Now bitswap those 9 bits 1816 */ 1817 result = 0; 1818 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1819 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1820 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1821 1822 /* 1823 * hashResult[14:09] = ethernetADD[00:05] 1824 */ 1825 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1826 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1827 GE_DPRINTF(sc, ("1(%#x)", result)); 1828 } 1829 GE_FUNC_EXIT(sc, ""); 1830 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1831 } 1832 1833 int 1834 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1835 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1836 { 1837 uint64_t he; 1838 uint64_t *maybe_he_p = NULL; 1839 int limit; 1840 int hash; 1841 int maybe_hash = 0; 1842 1843 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1844 1845 hash = gfe_hash_compute(sc, eaddr); 1846 1847 if (sc->sc_hashtable == NULL) { 1848 panic("%s:%d: hashtable == NULL!", device_xname(sc->sc_dev), 1849 __LINE__); 1850 } 1851 1852 /* 1853 * Assume we are going to insert so create the hash entry we 1854 * are going to insert. We also use it to match entries we 1855 * will be removing. 1856 */ 1857 he = ((uint64_t) eaddr[5] << 43) | 1858 ((uint64_t) eaddr[4] << 35) | 1859 ((uint64_t) eaddr[3] << 27) | 1860 ((uint64_t) eaddr[2] << 19) | 1861 ((uint64_t) eaddr[1] << 11) | 1862 ((uint64_t) eaddr[0] << 3) | 1863 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1864 1865 /* 1866 * The GT will search upto 12 entries for a hit, so we must mimic that. 1867 */ 1868 hash &= sc->sc_hashmask / sizeof(he); 1869 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1870 /* 1871 * Does the GT wrap at the end, stop at the, or overrun the 1872 * end? Assume it wraps for now. Stash a copy of the 1873 * current hash entry. 1874 */ 1875 uint64_t *he_p = &sc->sc_hashtable[hash]; 1876 uint64_t thishe = *he_p; 1877 1878 /* 1879 * If the hash entry isn't valid, that break the chain. And 1880 * this entry a good candidate for reuse. 1881 */ 1882 if ((thishe & HSH_V) == 0) { 1883 maybe_he_p = he_p; 1884 break; 1885 } 1886 1887 /* 1888 * If the hash entry has the same address we are looking for 1889 * then ... if we are removing and the skip bit is set, its 1890 * already been removed. if are adding and the skip bit is 1891 * clear, then its already added. In either return EBUSY 1892 * indicating the op has already been done. Otherwise flip 1893 * the skip bit and return 0. 1894 */ 1895 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1896 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1897 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1898 return EBUSY; 1899 *he_p = thishe ^ HSH_S; 1900 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1901 hash * sizeof(he), sizeof(he), 1902 BUS_DMASYNC_PREWRITE); 1903 GE_FUNC_EXIT(sc, "^"); 1904 return 0; 1905 } 1906 1907 /* 1908 * If we haven't found a slot for the entry and this entry 1909 * is currently being skipped, return this entry. 1910 */ 1911 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1912 maybe_he_p = he_p; 1913 maybe_hash = hash; 1914 } 1915 1916 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1917 } 1918 1919 /* 1920 * If we got here, then there was no entry to remove. 1921 */ 1922 if (op == GE_HASH_REMOVE) { 1923 GE_FUNC_EXIT(sc, "?"); 1924 return ENOENT; 1925 } 1926 1927 /* 1928 * If we couldn't find a slot, return an error. 1929 */ 1930 if (maybe_he_p == NULL) { 1931 GE_FUNC_EXIT(sc, "!"); 1932 return ENOSPC; 1933 } 1934 1935 /* Update the entry. 1936 */ 1937 *maybe_he_p = he; 1938 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1939 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1940 GE_FUNC_EXIT(sc, "+"); 1941 return 0; 1942 } 1943 1944 int 1945 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, 1946 u_long cmd) 1947 { 1948 struct gfe_softc *sc = ec->ec_if.if_softc; 1949 int error; 1950 enum gfe_hash_op op; 1951 enum gfe_rxprio prio; 1952 1953 GE_FUNC_ENTER(sc, "hash_multichg"); 1954 /* 1955 * Is this a wildcard entry? If so and its being removed, recompute. 1956 */ 1957 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1958 if (cmd == SIOCDELMULTI) { 1959 GE_FUNC_EXIT(sc, ""); 1960 return ENETRESET; 1961 } 1962 1963 /* 1964 * Switch in 1965 */ 1966 sc->sc_flags |= GE_ALLMULTI; 1967 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1968 sc->sc_pcr |= ETH_EPCR_PM; 1969 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr); 1970 GE_FUNC_EXIT(sc, ""); 1971 return 0; 1972 } 1973 GE_FUNC_EXIT(sc, ""); 1974 return ENETRESET; 1975 } 1976 1977 prio = GE_RXPRIO_MEDLO; 1978 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1979 1980 if (sc->sc_hashtable == NULL) { 1981 GE_FUNC_EXIT(sc, ""); 1982 return 0; 1983 } 1984 1985 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1986 if (error == EBUSY) { 1987 aprint_error_dev(sc->sc_dev, "multichg: tried to %s %s again\n", 1988 cmd == SIOCDELMULTI ? "remove" : "add", 1989 ether_sprintf(enm->enm_addrlo)); 1990 GE_FUNC_EXIT(sc, ""); 1991 return 0; 1992 } 1993 1994 if (error == ENOENT) { 1995 aprint_error_dev(sc->sc_dev, 1996 "multichg: failed to remove %s: not in table\n", 1997 ether_sprintf(enm->enm_addrlo)); 1998 GE_FUNC_EXIT(sc, ""); 1999 return 0; 2000 } 2001 2002 if (error == ENOSPC) { 2003 aprint_error_dev(sc->sc_dev, "multichg:" 2004 " failed to add %s: no space; regenerating table\n", 2005 ether_sprintf(enm->enm_addrlo)); 2006 GE_FUNC_EXIT(sc, ""); 2007 return ENETRESET; 2008 } 2009 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 2010 device_xname(sc->sc_dev), 2011 cmd == SIOCDELMULTI ? "remove" : "add", 2012 ether_sprintf(enm->enm_addrlo))); 2013 GE_FUNC_EXIT(sc, ""); 2014 return 0; 2015 } 2016 2017 int 2018 gfe_hash_fill(struct gfe_softc *sc) 2019 { 2020 struct ether_multistep step; 2021 struct ether_multi *enm; 2022 int error; 2023 2024 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 2025 2026 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 2027 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 2028 if (error) 2029 GE_FUNC_EXIT(sc, "!"); 2030 return error; 2031 2032 sc->sc_flags &= ~GE_ALLMULTI; 2033 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 2034 sc->sc_pcr &= ~ETH_EPCR_PM; 2035 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 2036 while (enm != NULL) { 2037 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2038 sc->sc_flags |= GE_ALLMULTI; 2039 sc->sc_pcr |= ETH_EPCR_PM; 2040 } else { 2041 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 2042 GE_RXPRIO_MEDLO, enm->enm_addrlo); 2043 if (error == ENOSPC) 2044 break; 2045 } 2046 ETHER_NEXT_MULTI(step, enm); 2047 } 2048 2049 GE_FUNC_EXIT(sc, ""); 2050 return error; 2051 } 2052 2053 int 2054 gfe_hash_alloc(struct gfe_softc *sc) 2055 { 2056 int error; 2057 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 2058 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 2059 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 2060 BUS_DMA_NOCACHE); 2061 if (error) { 2062 aprint_error_dev(sc->sc_dev, 2063 "failed to allocate %d bytes for hash table: %d\n", 2064 sc->sc_hashmask + 1, error); 2065 GE_FUNC_EXIT(sc, ""); 2066 return error; 2067 } 2068 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 2069 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 2070 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 2071 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 2072 GE_FUNC_EXIT(sc, ""); 2073 return 0; 2074 } 2075
Indexes created Sat Oct 18 08:10:09 GMT 2025