if_gfe.c revision 1.3
1 /* $NetBSD: if_gfe.c,v 1.3 2003/03/17 16:41:15 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #define PKT_DUMP 0 45 46 #include "opt_inet.h" 47 #include "bpfilter.h" 48 49 #include <sys/param.h> 50 #include <sys/types.h> 51 #include <sys/inttypes.h> 52 #include <sys/queue.h> 53 54 #include <sys/callout.h> 55 #include <sys/device.h> 56 #include <sys/errno.h> 57 #include <sys/ioctl.h> 58 #include <sys/mbuf.h> 59 #include <sys/socket.h> 60 61 #include <machine/bus.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <dev/mii/miivar.h> 77 78 #include <dev/marvell/gtintrreg.h> 79 #include <dev/marvell/gtethreg.h> 80 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/if_gfevar.h> 83 84 #define GE_READ(sc, reg) \ 85 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 86 #define GE_WRITE(sc, reg, v) \ 87 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 88 89 #define GE_DEBUG 90 #if 0 91 #define GE_NOHASH 92 #define GE_NORX 93 #endif 94 95 #ifdef GE_DEBUG 96 #define GE_DPRINTF(sc, a) do \ 97 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 98 printf a; \ 99 while (0) 100 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 101 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 102 #else 103 #define GE_DPRINTF(sc, a) do { } while (0) 104 #define GE_FUNC_ENTER(sc, func) do { } while (0) 105 #define GE_FUNC_EXIT(sc, str) do { } while (0) 106 #endif 107 enum gfe_whack_op { 108 GE_WHACK_START, GE_WHACK_RESTART, 109 GE_WHACK_CHANGE, GE_WHACK_STOP 110 }; 111 112 enum gfe_hash_op { 113 GE_HASH_ADD, GE_HASH_REMOVE, 114 }; 115 116 #if 1 117 #define htogt32(a) htobe32(a) 118 #define gt32toh(a) be32toh(a) 119 #else 120 #define htogt32(a) htole32(a) 121 #define gt32toh(a) le32toh(a) 122 #endif 123 124 #define STATIC 125 126 STATIC int gfe_match (struct device *, struct cfdata *, void *); 127 STATIC void gfe_attach (struct device *, struct device *, void *); 128 129 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 130 size_t, int); 131 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 132 133 STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); 134 STATIC void gfe_ifstart (struct ifnet *); 135 STATIC void gfe_ifwatchdog (struct ifnet *); 136 137 STATIC int gfe_mii_mediachange (struct ifnet *); 138 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 139 STATIC int gfe_mii_read (struct device *, int, int); 140 STATIC void gfe_mii_write (struct device *, int, int, int); 141 STATIC void gfe_mii_statchg (struct device *); 142 143 STATIC void gfe_tick(void *arg); 144 145 STATIC void gfe_tx_restart(void *); 146 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 147 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 148 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 149 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 150 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 151 152 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 153 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 154 STATIC int gfe_rx_prime(struct gfe_softc *); 155 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 156 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 157 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 158 159 STATIC int gfe_intr(void *); 160 161 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 162 163 STATIC int gfe_hash_compute(struct gfe_softc *, const u_int8_t [ETHER_ADDR_LEN]); 164 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 165 enum gfe_rxprio, const u_int8_t [ETHER_ADDR_LEN]); 166 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 167 u_long); 168 STATIC int gfe_hash_fill(struct gfe_softc *); 169 STATIC int gfe_hash_alloc(struct gfe_softc *); 170 171 /* Linkup to the rest of the kernel */ 172 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 173 gfe_match, gfe_attach, NULL, NULL); 174 175 extern struct cfdriver gfe_cd; 176 177 int 178 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 179 { 180 struct gt_softc *gt = (struct gt_softc *) parent; 181 struct gt_attach_args *ga = aux; 182 uint8_t enaddr[6]; 183 184 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 185 return 0; 186 187 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 188 return 0; 189 190 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 191 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 192 return 0; 193 194 return 1; 195 } 196 197 /* 198 * Attach this instance, and then all the sub-devices 199 */ 200 void 201 gfe_attach(struct device *parent, struct device *self, void *aux) 202 { 203 struct gt_attach_args *ga = aux; 204 struct gt_softc *gt = (struct gt_softc *) parent; 205 struct gfe_softc *sc = (struct gfe_softc *) self; 206 struct ifnet *ifp; 207 uint32_t data; 208 uint8_t enaddr[6]; 209 int phyaddr; 210 uint32_t sdcr; 211 212 GT_ETHERFOUND(gt, ga); 213 214 sc->sc_gt_memt = ga->ga_memt; 215 sc->sc_gt_memh = ga->ga_memh; 216 sc->sc_dmat = ga->ga_dmat; 217 sc->sc_macno = ga->ga_unit; 218 219 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 220 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 221 aprint_error(": failed to map registers\n"); 222 } 223 224 callout_init(&sc->sc_co); 225 226 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 227 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 228 229 gtget_macaddr(gt, sc->sc_macno, enaddr); 230 231 sc->sc_pcr = GE_READ(sc, EPCR); 232 sc->sc_pcxr = GE_READ(sc, EPCXR); 233 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 234 235 aprint_normal(": address %s", ether_sprintf(enaddr)); 236 237 #if defined(DEBUG) 238 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 239 #endif 240 241 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 242 if (sc->sc_dev.dv_cfdata->cf_flags & 1) { 243 aprint_normal(", phy %d (rmii)", phyaddr); 244 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 245 } else { 246 aprint_normal(", phy %d (mii)", phyaddr); 247 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 248 } 249 sc->sc_pcxr &= ~(3 << 14); 250 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 251 252 if (sc->sc_pcr & ETH_EPCR_EN) { 253 int tries = 1000; 254 /* 255 * Abort transmitter and receiver and wait for them to quiese 256 */ 257 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 258 do { 259 delay(100); 260 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 261 } 262 263 sc->sc_pcr &= ~ETH_EPCR_EN; 264 265 #if defined(DEBUG) 266 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 267 #endif 268 269 /* 270 * Now turn off the GT. If it didn't quiese, too ***ing bad. 271 */ 272 GE_WRITE(sc, EPCR, sc->sc_pcr); 273 GE_WRITE(sc, EIMR, sc->sc_intrmask); 274 sdcr = GE_READ(sc, ESDCR); 275 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 276 sdcr |= ETH_ESDCR_RIFB; 277 GE_WRITE(sc, ESDCR, sdcr); 278 sc->sc_max_frame_length = 1536; 279 280 aprint_normal("\n"); 281 sc->sc_mii.mii_ifp = &sc->sc_ec.ec_if; 282 sc->sc_mii.mii_readreg = gfe_mii_read; 283 sc->sc_mii.mii_writereg = gfe_mii_write; 284 sc->sc_mii.mii_statchg = gfe_mii_statchg; 285 286 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 287 gfe_mii_mediastatus); 288 289 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 290 MII_OFFSET_ANY, MIIF_NOISOLATE); 291 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 292 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 293 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 294 } else { 295 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 296 } 297 298 ifp = &sc->sc_ec.ec_if; 299 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 300 ifp->if_softc = sc; 301 /* ifp->if_mowner = &sc->sc_mowner; */ 302 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 303 #if 0 304 ifp->if_flags |= IFF_DEBUG; 305 #endif 306 ifp->if_ioctl = gfe_ifioctl; 307 ifp->if_start = gfe_ifstart; 308 ifp->if_watchdog = gfe_ifwatchdog; 309 310 if_attach(ifp); 311 ether_ifattach(ifp, enaddr); 312 #if NBPFILTER > 0 313 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 314 #endif 315 #if NRND > 0 316 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 317 #endif 318 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 319 gfe_intr, sc); 320 } 321 322 int 323 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 324 size_t size, int flags) 325 { 326 int error = 0; 327 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 328 gdm->gdm_size = size; 329 gdm->gdm_maxsegs = maxsegs; 330 331 #if 1 332 flags |= BUS_DMA_NOCACHE; 333 #endif 334 335 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, NBPG, 336 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 337 BUS_DMA_NOWAIT); 338 if (error) 339 goto fail; 340 341 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 342 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 343 if (error) 344 goto fail; 345 346 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 347 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 348 if (error) 349 goto fail; 350 351 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 352 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 353 if (error) 354 goto fail; 355 356 /* invalidate from cache */ 357 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 358 BUS_DMASYNC_PREREAD); 359 fail: 360 if (error) { 361 gfe_dmamem_free(sc, gdm); 362 GE_DPRINTF(sc, (":err=%d", error)); 363 } 364 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 365 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 366 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 367 GE_FUNC_EXIT(sc, ""); 368 return error; 369 } 370 371 void 372 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 373 { 374 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 375 if (gdm->gdm_map) 376 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 377 if (gdm->gdm_kva) 378 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 379 if (gdm->gdm_nsegs > 0) 380 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 381 gdm->gdm_map = NULL; 382 gdm->gdm_kva = NULL; 383 gdm->gdm_nsegs = 0; 384 GE_FUNC_EXIT(sc, ""); 385 } 386 387 int 388 gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 389 { 390 struct gfe_softc * const sc = ifp->if_softc; 391 struct ifreq *ifr = (struct ifreq *) data; 392 struct ifaddr *ifa = (struct ifaddr *) data; 393 int s, error = 0; 394 395 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 396 s = splnet(); 397 398 switch (cmd) { 399 case SIOCSIFADDR: 400 ifp->if_flags |= IFF_UP; 401 switch (ifa->ifa_addr->sa_family) { 402 #ifdef INET 403 case AF_INET: 404 error = gfe_whack(sc, GE_WHACK_START); 405 if (error == 0) 406 arp_ifinit(ifp, ifa); 407 break; 408 #endif 409 default: 410 error = gfe_whack(sc, GE_WHACK_START); 411 break; 412 } 413 break; 414 415 case SIOCSIFFLAGS: 416 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 417 case IFF_UP|IFF_RUNNING:/* active->active, update */ 418 error = gfe_whack(sc, GE_WHACK_CHANGE); 419 break; 420 case IFF_RUNNING: /* not up, so we stop */ 421 error = gfe_whack(sc, GE_WHACK_STOP); 422 break; 423 case IFF_UP: /* not running, so we start */ 424 error = gfe_whack(sc, GE_WHACK_START); 425 break; 426 case 0: /* idle->idle: do nothing */ 427 break; 428 } 429 break; 430 431 case SIOCADDMULTI: 432 case SIOCDELMULTI: 433 error = (cmd == SIOCADDMULTI) 434 ? ether_addmulti(ifr, &sc->sc_ec) 435 : ether_delmulti(ifr, &sc->sc_ec); 436 if (error == ENETRESET) { 437 if (ifp->if_flags & IFF_RUNNING) 438 error = gfe_whack(sc, GE_WHACK_CHANGE); 439 else 440 error = 0; 441 } 442 break; 443 444 case SIOCSIFMTU: 445 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 446 error = EINVAL; 447 break; 448 } 449 ifp->if_mtu = ifr->ifr_mtu; 450 break; 451 452 case SIOCSIFMEDIA: 453 case SIOCGIFMEDIA: 454 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 455 break; 456 457 default: 458 error = EINVAL; 459 break; 460 } 461 splx(s); 462 GE_FUNC_EXIT(sc, ""); 463 return error; 464 } 465 466 void 467 gfe_ifstart(struct ifnet *ifp) 468 { 469 struct gfe_softc * const sc = ifp->if_softc; 470 struct mbuf *m; 471 472 GE_FUNC_ENTER(sc, "gfe_ifstart"); 473 474 if ((ifp->if_flags & IFF_RUNNING) == 0) { 475 GE_FUNC_EXIT(sc, "$"); 476 return; 477 } 478 479 if (sc->sc_txq[GE_TXPRIO_HI] == NULL) { 480 ifp->if_flags |= IFF_OACTIVE; 481 #if defined(DEBUG) || defined(DIAGNOSTIC) 482 printf("%s: ifstart: txq not yet created\n", ifp->if_xname); 483 #endif 484 GE_FUNC_EXIT(sc, ""); 485 return; 486 } 487 488 for (;;) { 489 IF_DEQUEUE(&ifp->if_snd, m); 490 if (m == NULL) { 491 ifp->if_flags &= ~IFF_OACTIVE; 492 GE_FUNC_EXIT(sc, ""); 493 return; 494 } 495 496 /* 497 * No space in the pending queue? try later. 498 */ 499 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq)) 500 break; 501 502 /* 503 * Try to enqueue a mbuf to the device. If that fails, we 504 * can always try to map the next mbuf. 505 */ 506 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq, m); 507 GE_DPRINTF(sc, (">")); 508 #ifndef GE_NOTX 509 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 510 #endif 511 } 512 513 /* 514 * Attempt to queue the mbuf for send failed. 515 */ 516 IF_PREPEND(&ifp->if_snd, m); 517 ifp->if_flags |= IFF_OACTIVE; 518 GE_FUNC_EXIT(sc, "%%"); 519 } 520 521 void 522 gfe_ifwatchdog(struct ifnet *ifp) 523 { 524 struct gfe_softc * const sc = ifp->if_softc; 525 struct gfe_txqueue *txq; 526 527 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 528 printf("%s: device timeout", 529 sc->sc_dev.dv_xname); 530 if ((txq = sc->sc_txq[GE_TXPRIO_HI]) != NULL) { 531 unsigned int curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / 16; 532 printf(" (fi=%d,lo=%d,cur=%d(%#x),icm=%#x) ", 533 txq->txq_fi, txq->txq_lo, curtxdnum, 534 txq->txq_descs[curtxdnum].ed_cmdsts, 535 GE_READ(sc, EICR)); 536 } 537 printf("\n"); 538 ifp->if_oerrors++; 539 (void) gfe_whack(sc, GE_WHACK_RESTART); 540 GE_FUNC_EXIT(sc, ""); 541 } 542 543 int 545 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 546 { 547 struct gfe_rxqueue *rxq; 548 volatile struct gt_eth_desc *rxd; 549 const bus_dma_segment_t *ds; 550 int error; 551 int idx; 552 bus_addr_t nxtaddr; 553 bus_size_t boff; 554 555 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 556 GE_DPRINTF(sc, ("(%d)", rxprio)); 557 if (sc->sc_rxq[rxprio] != NULL) { 558 GE_FUNC_EXIT(sc, ""); 559 return 0; 560 } 561 562 rxq = (struct gfe_rxqueue *) malloc(sizeof(*rxq), M_DEVBUF, M_NOWAIT); 563 if (rxq == NULL) { 564 GE_FUNC_EXIT(sc, "!"); 565 return ENOMEM; 566 } 567 568 memset(rxq, 0, sizeof(*rxq)); 569 570 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 571 GE_RXDESC_MEMSIZE, 0); 572 if (error) { 573 free(rxq, M_DEVBUF); 574 GE_FUNC_EXIT(sc, "!!"); 575 return error; 576 } 577 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 578 GE_RXBUF_MEMSIZE, 0); 579 if (error) { 580 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 581 free(rxq, M_DEVBUF); 582 GE_FUNC_EXIT(sc, "!!!"); 583 return error; 584 } 585 586 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_TXMEM_SIZE); 587 588 sc->sc_rxq[rxprio] = rxq; 589 rxq->rxq_descs = 590 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 591 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 592 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 593 rxq->rxq_fi = 0; 594 rxq->rxq_active = GE_RXDESC_MAX; 595 for (idx = 0, rxd = rxq->rxq_descs, 596 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 597 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 598 idx < GE_RXDESC_MAX; 599 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 600 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 601 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 602 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 603 /* 604 * update the nxtptr to point to the next txd. 605 */ 606 if (idx == GE_RXDESC_MAX - 1) 607 nxtaddr = rxq->rxq_desc_busaddr; 608 rxd->ed_nxtptr = htogt32(nxtaddr); 609 boff += GE_RXBUF_SIZE; 610 if (boff == ds->ds_len) { 611 ds++; 612 boff = 0; 613 } 614 } 615 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 616 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 617 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 618 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 619 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 620 BUS_DMASYNC_PREREAD); 621 622 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 623 switch (rxprio) { 624 case GE_RXPRIO_HI: 625 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 626 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 627 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 628 break; 629 case GE_RXPRIO_MEDHI: 630 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 631 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 632 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 633 break; 634 case GE_RXPRIO_MEDLO: 635 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 636 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 637 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 638 break; 639 case GE_RXPRIO_LO: 640 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 641 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 642 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 643 break; 644 } 645 GE_FUNC_EXIT(sc, ""); 646 return error; 647 } 648 649 #if PKT_DUMP 650 static void pkt_dump(struct gfe_softc *sc, unsigned char *p, int l); 651 static void 652 pkt_dump(struct gfe_softc *sc, unsigned char *p, int l) 653 { 654 char str[17]; 655 int j; 656 657 str[16] = '\0'; 658 while (l) { 659 printf("%08lx:", (unsigned long) p); 660 for (j=0;j<16 && l;j++, l--, p++) { 661 printf(" %02x", (unsigned) *p); 662 str[j] = (*p < ' ' || *p > '~') ? '.' : *p; 663 } 664 while (j < 16) { printf(" "); str[j++] = ' '; } 665 printf(" %s\n", str); 666 } 667 } 668 #endif 669 670 void 671 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 672 { 673 struct ifnet * const ifp = &sc->sc_ec.ec_if; 674 struct gfe_rxqueue * const rxq = sc->sc_rxq[rxprio]; 675 struct mbuf *m = rxq->rxq_curpkt; 676 677 GE_FUNC_ENTER(sc, "gfe_rx_get"); 678 GE_DPRINTF(sc, ("(%d)", rxprio)); 679 680 while (rxq->rxq_active > 0) { 681 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 682 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 683 const struct ether_header *eh; 684 unsigned int cmdsts; 685 size_t buflen; 686 687 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 688 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 689 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 690 cmdsts = gt32toh(rxd->ed_cmdsts); 691 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 692 rxq->rxq_cmdsts = cmdsts; 693 /* 694 * Sometimes the GE "forgets" to reset the ownership bit. 695 * But if the length has been rewritten, the packet is ours 696 * so pretend the O bit is set. 697 */ 698 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 699 if ((cmdsts & RX_CMD_O) && buflen == 0) { 700 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 701 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 702 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 703 break; 704 } 705 706 /* 707 * If this is not a single buffer packet with no errors 708 * or for some reason it's bigger than our frame size, 709 * ignore it and go to the next packet. 710 */ 711 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 712 (RX_CMD_F|RX_CMD_L) || 713 buflen > sc->sc_max_frame_length) { 714 GE_DPRINTF(sc, ("!")); 715 --rxq->rxq_active; 716 ifp->if_ipackets++; 717 ifp->if_ierrors++; 718 goto give_it_back; 719 } 720 721 if (m == NULL) { 722 MGETHDR(m, M_DONTWAIT, MT_DATA); 723 if (m == NULL) { 724 GE_DPRINTF(sc, ("?")); 725 break; 726 } 727 m->m_data += 2; 728 } 729 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 730 MCLGET(m, M_DONTWAIT); 731 if ((m->m_flags & M_EXT) == 0) { 732 GE_DPRINTF(sc, ("?")); 733 break; 734 } 735 m->m_data += 2; 736 } 737 m->m_len = 0; 738 m->m_pkthdr.len = 0; 739 m->m_pkthdr.rcvif = &sc->sc_ec.ec_if; 740 rxq->rxq_cmdsts = cmdsts; 741 --rxq->rxq_active; 742 743 ifp->if_ibytes += buflen; 744 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 745 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 746 747 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 748 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 749 #if PKT_DUMP 750 printf("[%d]\n", buflen); 751 pkt_dump(sc,m->m_data+m->m_len,buflen); 752 #endif 753 m->m_len = buflen; 754 m->m_pkthdr.len = buflen; 755 756 ifp->if_ipackets++; 757 #ifdef M_HASFCS 758 m->m_flags |= M_HASFCS; 759 #else 760 m->m_len -= 4; 761 m->m_pkthdr.len -= 4; 762 #endif 763 #if NBPFILTER > 0 764 if (ifp->if_bpf != NULL) 765 bpf_mtap(ifp->if_bpf, m); 766 #endif 767 768 eh = (const struct ether_header *) m->m_data; 769 if ((ifp->if_flags & IFF_PROMISC) || 770 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 771 (rxq->rxq_cmdsts & RX_STS_HE) || 772 (eh->ether_dhost[0] & 1) != 0 || 773 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 774 ETHER_ADDR_LEN) == 0) { 775 (*ifp->if_input)(ifp, m); 776 m = NULL; 777 GE_DPRINTF(sc, (">")); 778 } else { 779 m->m_len = 0; 780 m->m_pkthdr.len = 0; 781 GE_DPRINTF(sc, ("+")); 782 } 783 rxq->rxq_cmdsts = 0; 784 785 give_it_back: 786 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 787 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 788 #if 0 789 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 790 rxq->rxq_fi, 791 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 792 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 793 #endif 794 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 795 rxq->rxq_fi * sizeof(*rxd), sizeof(*rxd), 796 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 797 rxq->rxq_fi = (rxd->ed_nxtptr - rxq->rxq_desc_busaddr) / 798 sizeof(*rxd); 799 #if 0 800 if (++rxq->rxq_fi == GE_RXDESC_MAX) 801 rxq->rxq_fi = 0; 802 #endif 803 rxq->rxq_active++; 804 } 805 rxq->rxq_curpkt = m; 806 GE_FUNC_EXIT(sc, ""); 807 } 808 809 uint32_t 810 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 811 { 812 struct gfe_rxqueue *rxq; 813 uint32_t rxbits; 814 #define RXPRIO_DECODER 0xffffaa50 815 GE_FUNC_ENTER(sc, "gfe_rx_process"); 816 817 rxbits = ETH_IR_RxBuffer_GET(cause); 818 while (rxbits) { 819 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 820 GE_DPRINTF(sc, ("%1x", rxbits)); 821 rxbits &= ~(1 << rxprio); 822 gfe_rx_get(sc, rxprio); 823 } 824 825 rxbits = ETH_IR_RxError_GET(cause); 826 while (rxbits) { 827 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 828 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 829 int idx; 830 rxbits &= ~(1 << rxprio); 831 rxq = sc->sc_rxq[rxprio]; 832 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 833 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 834 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 835 sc->sc_tickflags |= GE_TICK_RX_RESTART; 836 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 837 } 838 sc->sc_ec.ec_if.if_ierrors++; 839 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 840 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 841 memset(masks, 0, sizeof(masks)); 842 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 843 0, rxq->rxq_desc_mem.gdm_size, 844 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 845 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 846 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 847 848 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 849 masks[idx/32] |= 1 << (idx & 31); 850 } 851 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 852 0, rxq->rxq_desc_mem.gdm_size, 853 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 854 #if defined(DEBUG) 855 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 856 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 857 rxq->rxq_cmdsts, masks[0], masks[1]); 858 #endif 859 } 860 if ((intrmask & ETH_IR_RxBits) == 0) 861 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 862 863 GE_FUNC_EXIT(sc, ""); 864 return intrmask; 865 } 866 867 int 868 gfe_rx_prime(struct gfe_softc *sc) 869 { 870 struct gfe_rxqueue *rxq; 871 int error; 872 873 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 874 875 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 876 if (error) 877 goto bail; 878 rxq = sc->sc_rxq[GE_RXPRIO_HI]; 879 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 880 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 881 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 882 } 883 sc->sc_intrmask |= rxq->rxq_intrbits; 884 885 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 886 if (error) 887 goto bail; 888 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 889 rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 890 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 891 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 892 sc->sc_intrmask |= rxq->rxq_intrbits; 893 } 894 895 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 896 if (error) 897 goto bail; 898 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 899 rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 900 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 901 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 902 sc->sc_intrmask |= rxq->rxq_intrbits; 903 } 904 905 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 906 if (error) 907 goto bail; 908 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 909 rxq = sc->sc_rxq[GE_RXPRIO_LO]; 910 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 911 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 912 sc->sc_intrmask |= rxq->rxq_intrbits; 913 } 914 915 bail: 916 GE_FUNC_EXIT(sc, ""); 917 return error; 918 } 919 920 void 921 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 922 { 923 struct gfe_rxqueue *rxq = sc->sc_rxq[rxprio]; 924 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 925 if (rxq == NULL) { 926 GE_FUNC_EXIT(sc, ""); 927 return; 928 } 929 930 if (rxq->rxq_curpkt) 931 m_freem(rxq->rxq_curpkt); 932 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 933 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 934 free(rxq, M_DEVBUF); 935 sc->sc_rxq[rxprio] = NULL; 936 GE_FUNC_EXIT(sc, ""); 937 } 938 939 void 940 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 941 { 942 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 943 sc->sc_flags &= ~GE_RXACTIVE; 944 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 945 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 946 GE_WRITE(sc, EIMR, sc->sc_intrmask); 947 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 948 do { 949 delay(10); 950 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 951 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 952 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 953 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 954 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 955 GE_FUNC_EXIT(sc, ""); 956 } 957 958 void 960 gfe_tick(void *arg) 961 { 962 struct gfe_softc * const sc = arg; 963 uint32_t intrmask; 964 unsigned int tickflags; 965 int s; 966 967 GE_FUNC_ENTER(sc, "gfe_tick"); 968 969 s = splnet(); 970 971 tickflags = sc->sc_tickflags; 972 sc->sc_tickflags = 0; 973 intrmask = sc->sc_intrmask; 974 if (tickflags & GE_TICK_TX_IFSTART) 975 gfe_ifstart(&sc->sc_ec.ec_if); 976 if (tickflags & GE_TICK_RX_RESTART) { 977 intrmask |= sc->sc_idlemask; 978 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 979 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_HI]; 980 rxq->rxq_fi = 0; 981 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 982 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 983 } 984 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 985 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 986 rxq->rxq_fi = 0; 987 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 988 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 989 } 990 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 991 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 992 rxq->rxq_fi = 0; 993 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 994 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 995 } 996 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 997 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_LO]; 998 rxq->rxq_fi = 0; 999 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 1000 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 1001 } 1002 sc->sc_idlemask = 0; 1003 } 1004 if (intrmask != sc->sc_intrmask) { 1005 sc->sc_intrmask = intrmask; 1006 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1007 } 1008 gfe_intr(sc); 1009 splx(s); 1010 1011 GE_FUNC_EXIT(sc, ""); 1012 } 1013 1014 int 1015 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1016 { 1017 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1018 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1019 uint32_t intrmask = sc->sc_intrmask; 1020 struct mbuf *m; 1021 1022 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1023 1024 /* 1025 * Anything in the pending queue to enqueue? if not, punt. 1026 * otherwise grab its dmamap. 1027 */ 1028 if ((m = txq->txq_pendq.ifq_head) == NULL) { 1029 GE_FUNC_EXIT(sc, "-"); 1030 return 0; 1031 } 1032 1033 /* 1034 * Have we [over]consumed our limit of descriptors? 1035 * Do we have enough free descriptors? 1036 */ 1037 if (GE_TXDESC_MAX == txq->txq_nactive + 1) { 1038 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1039 uint32_t cmdsts; 1040 size_t pktlen; 1041 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1042 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1043 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1044 cmdsts = gt32toh(txd2->ed_cmdsts); 1045 if (cmdsts & TX_CMD_O) { 1046 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1047 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1048 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1049 GE_FUNC_EXIT(sc, "@"); 1050 return 0; 1051 } 1052 if (++txq->txq_fi == GE_TXDESC_MAX) 1053 txq->txq_fi = 0; 1054 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1055 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1056 txq->txq_inptr += (pktlen + 7) & ~7; 1057 txq->txq_nactive--; 1058 1059 /* statistics */ 1060 sc->sc_ec.ec_if.if_opackets++; 1061 sc->sc_ec.ec_if.if_obytes += pktlen; 1062 if (cmdsts & TX_STS_ES) 1063 sc->sc_ec.ec_if.if_oerrors++; 1064 GE_DPRINTF(sc, ("%%")); 1065 } 1066 1067 /* 1068 * If this packet would wrap around the end of the buffer, reset back 1069 * to the beginning. 1070 */ 1071 if (txq->txq_outptr + m->m_pkthdr.len > GE_TXBUF_SIZE) { 1072 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1073 txq->txq_outptr = 0; 1074 } 1075 1076 /* 1077 * Make sure the output packet doesn't run over the beginning of 1078 * what we've already given the GT. 1079 */ 1080 if (txq->txq_outptr <= txq->txq_inptr && 1081 txq->txq_outptr + m->m_pkthdr.len > txq->txq_inptr) { 1082 intrmask |= txq->txq_intrbits & 1083 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1084 if (sc->sc_intrmask != intrmask) { 1085 sc->sc_intrmask = intrmask; 1086 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1087 } 1088 GE_FUNC_EXIT(sc, "#"); 1089 return 0; 1090 } 1091 1092 /* 1093 * The end-of-list descriptor we put on last time is the starting point 1094 * for this packet. The GT is supposed to terminate list processing on 1095 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1096 * must terminate the list. 1097 */ 1098 intrmask = sc->sc_intrmask; 1099 1100 m_copydata(m, 0, m->m_pkthdr.len, 1101 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1102 #if PKT_DUMP 1103 GE_DPRINTF(sc,("\n")); 1104 pkt_dump(sc, txq->txq_buf_mem.gdm_kva + txq->txq_outptr, m->m_pkthdr.len); 1105 #endif 1106 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1107 txq->txq_outptr, m->m_pkthdr.len, BUS_DMASYNC_PREWRITE); 1108 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1109 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1110 #if 0 1111 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1112 txq->txq_lo * sizeof(*txd), sizeof(*txd), 1113 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1114 #endif 1115 1116 /* 1117 * Request a buffer interrupt every 2/3 of the way thru the transmit 1118 * buffer. 1119 */ 1120 txq->txq_ei_gapcount += m->m_pkthdr.len + 7; 1121 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1122 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1123 txq->txq_ei_gapcount = 0; 1124 } else { 1125 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1126 } 1127 #if 0 1128 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1129 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1130 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1131 #endif 1132 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1133 txq->txq_lo * sizeof(*txd), sizeof(*txd), 1134 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1135 1136 txq->txq_outptr += (m->m_pkthdr.len + 31) & ~31; 1137 /* 1138 * Tell the SDMA engine to "Fetch!" 1139 */ 1140 GE_WRITE(sc, ESDCMR, 1141 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1142 1143 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1144 1145 /* 1146 * Update the last out appropriately. 1147 */ 1148 if (++txq->txq_lo == GE_TXDESC_MAX) 1149 txq->txq_lo = 0; 1150 1151 /* 1152 * Move mbuf from the pending queue to the snd queue. 1153 */ 1154 IF_DEQUEUE(&txq->txq_pendq, m); 1155 #if NBPFILTER > 0 1156 if (sc->sc_ec.ec_if.if_bpf != NULL) 1157 bpf_mtap(sc->sc_ec.ec_if.if_bpf, m); 1158 #endif 1159 m_freem(m); 1160 sc->sc_ec.ec_if.if_flags &= ~IFF_OACTIVE; 1161 1162 /* 1163 * Since we have put an item into the packet queue, we now want 1164 * an interrupt when the transmit queue finishes processing the 1165 * list. But only update the mask if needs changing. 1166 */ 1167 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1168 if (sc->sc_intrmask != intrmask) { 1169 sc->sc_intrmask = intrmask; 1170 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1171 } 1172 if (sc->sc_ec.ec_if.if_timer == 0) 1173 sc->sc_ec.ec_if.if_timer = 5; 1174 GE_FUNC_EXIT(sc, "*"); 1175 return 1; 1176 } 1177 1178 uint32_t 1179 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1180 { 1181 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1182 1183 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1184 1185 if (txq == NULL) { 1186 GE_FUNC_EXIT(sc, ""); 1187 return intrmask; 1188 } 1189 1190 while (txq->txq_nactive > 0) { 1191 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1192 uint32_t cmdsts; 1193 size_t pktlen; 1194 1195 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1196 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1197 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1198 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1199 /* 1200 * If the GT owns this descriptor and according 1201 * to the status register, the transmit engine 1202 * is not running, restart it. 1203 */ 1204 #if 0 1205 if ((GE_READ(sc, EPSR) & txq->txq_epsrbits & 1206 (ETH_EPSR_TxHigh|ETH_EPSR_TxLow)) == 0) { 1207 /* 1208 * If the current transmit descriptor isn't 1209 * pointing at this descriptor, then we've 1210 * lost synch, reset it to this one before 1211 * restarting. 1212 */ 1213 unsigned int curtxdnum = ( 1214 gt_read(sc->sc_dev.dv_parent, 1215 txq->txq_ectdp) - 1216 txq->txq_desc_busaddr) / 16; 1217 if (curtxdnum != txq->txq_fi) { 1218 gt_write(sc->sc_dev.dv_parent, 1219 txq->txq_ectdp, 1220 txq->txq_desc_busaddr + 1221 sizeof(*ed) * txq->txq_fi); 1222 GE_DPRINTF(sc, 1223 ("(oldcur=%d,newcur=fi(%d))", 1224 curtxdnum, txq->txq_fi)); 1225 printf("%s: transmitter synchronization" 1226 " lost at %d; repositioning" 1227 " to %d\n", 1228 sc->sc_dev.dv_xname, 1229 curtxdnum, txq->txq_fi); 1230 } 1231 /* 1232 * [Re-] Kick the transmit engine. 1233 */ 1234 GE_WRITE(sc, ESDCMR, 1235 txq->txq_esdcmrbits & 1236 (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1237 GE_DPRINTF(sc, ("*")); 1238 } 1239 #endif 1240 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 1241 txq->txq_fi * sizeof(*txd), sizeof(*txd), 1242 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1243 GE_FUNC_EXIT(sc, ""); 1244 return intrmask; 1245 } 1246 #if 0 1247 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1248 txq->txq_lo, 1249 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1250 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1251 #endif 1252 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1253 if (++txq->txq_fi == GE_TXDESC_MAX) 1254 txq->txq_fi = 0; 1255 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1256 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1257 txq->txq_inptr += (pktlen + 31) & ~31; 1258 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1259 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1260 1261 /* statistics */ 1262 sc->sc_ec.ec_if.if_opackets++; 1263 sc->sc_ec.ec_if.if_obytes += pktlen; 1264 if (cmdsts & TX_STS_ES) 1265 sc->sc_ec.ec_if.if_oerrors++; 1266 1267 txd->ed_bufptr = 0; 1268 1269 sc->sc_ec.ec_if.if_timer = 5; 1270 --txq->txq_nactive; 1271 } 1272 if (txq->txq_nactive != 0) 1273 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1274 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1275 sc->sc_ec.ec_if.if_timer = 0; 1276 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1277 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1278 GE_FUNC_EXIT(sc, ""); 1279 return intrmask; 1280 } 1281 1282 int 1283 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1284 { 1285 struct gfe_txqueue *txq; 1286 volatile struct gt_eth_desc *txd; 1287 unsigned int i; 1288 bus_addr_t addr; 1289 1290 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1291 1292 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1293 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1294 1295 if ((txq = sc->sc_txq[txprio]) == NULL) { 1296 int error; 1297 txq = (struct gfe_txqueue *) malloc(sizeof(*txq), 1298 M_DEVBUF, M_NOWAIT); 1299 if (txq == NULL) { 1300 GE_FUNC_EXIT(sc, ""); 1301 return ENOMEM; 1302 } 1303 memset(txq, 0, sizeof(*txq)); 1304 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1305 GE_TXMEM_SIZE, 0); 1306 if (error) { 1307 free(txq, M_DEVBUF); 1308 GE_FUNC_EXIT(sc, ""); 1309 return error; 1310 } 1311 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, 1312 GE_TXBUF_SIZE, 0); 1313 if (error) { 1314 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1315 free(txq, M_DEVBUF); 1316 GE_FUNC_EXIT(sc, ""); 1317 return error; 1318 } 1319 sc->sc_txq[txprio] = txq; 1320 } 1321 1322 txq->txq_descs = 1323 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1324 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1325 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1326 1327 txq->txq_pendq.ifq_maxlen = 10; 1328 txq->txq_ei_gapcount = 0; 1329 txq->txq_nactive = 0; 1330 txq->txq_fi = 0; 1331 txq->txq_lo = 0; 1332 txq->txq_inptr = GE_TXBUF_SIZE; 1333 txq->txq_outptr = 0; 1334 for (i = 0, txd = txq->txq_descs, 1335 addr = txq->txq_desc_busaddr + sizeof(*txd); 1336 i < GE_TXDESC_MAX - 1; 1337 i++, txd++, addr += sizeof(*txd)) { 1338 /* 1339 * update the nxtptr to point to the next txd. 1340 */ 1341 txd->ed_cmdsts = 0; 1342 txd->ed_nxtptr = htogt32(addr); 1343 } 1344 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1345 htogt32(txq->txq_desc_busaddr); 1346 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1347 GE_TXMEM_SIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1348 1349 switch (txprio) { 1350 case GE_TXPRIO_HI: 1351 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1352 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1353 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1354 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1355 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1356 break; 1357 1358 case GE_TXPRIO_LO: 1359 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1360 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1361 txq->txq_epsrbits = ETH_EPSR_TxLow; 1362 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1363 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1364 break; 1365 1366 case GE_TXPRIO_NONE: 1367 break; 1368 } 1369 #if 0 1370 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1371 gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); 1372 GE_DPRINTF(sc, (")")); 1373 #endif 1374 1375 /* 1376 * If we are restarting, there may be packets in the pending queue 1377 * waiting to be enqueued. Try enqueuing packets from both priority 1378 * queues until the pending queue is empty or there no room for them 1379 * on the device. 1380 */ 1381 while (gfe_tx_enqueue(sc, txprio)) 1382 continue; 1383 1384 GE_FUNC_EXIT(sc, ""); 1385 return 0; 1386 } 1387 1388 void 1389 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1390 { 1391 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1392 1393 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1394 if (txq == NULL) { 1395 GE_FUNC_EXIT(sc, ""); 1396 return; 1397 } 1398 1399 if (!flush) { 1400 GE_FUNC_EXIT(sc, ""); 1401 return; 1402 } 1403 1404 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1405 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1406 free(txq, M_DEVBUF); 1407 sc->sc_txq[txprio] = NULL; 1408 GE_FUNC_EXIT(sc, "-F"); 1409 } 1410 1411 void 1412 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1413 { 1414 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1415 1416 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1417 1418 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1419 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1420 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1421 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1422 1423 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1424 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1425 1426 sc->sc_ec.ec_if.if_timer = 0; 1427 GE_FUNC_EXIT(sc, ""); 1428 } 1429 1430 int 1432 gfe_intr(void *arg) 1433 { 1434 struct gfe_softc * const sc = arg; 1435 uint32_t cause; 1436 uint32_t intrmask = sc->sc_intrmask; 1437 int claim = 0; 1438 int cnt; 1439 1440 GE_FUNC_ENTER(sc, "gfe_intr"); 1441 1442 for (cnt = 0; cnt < 4; cnt++) { 1443 if (sc->sc_intrmask != intrmask) { 1444 sc->sc_intrmask = intrmask; 1445 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1446 } 1447 cause = GE_READ(sc, EICR); 1448 cause &= sc->sc_intrmask; 1449 GE_DPRINTF(sc, (".%#x", cause)); 1450 if (cause == 0) 1451 break; 1452 1453 claim = 1; 1454 1455 GE_WRITE(sc, EICR, ~cause); 1456 #ifndef GE_NORX 1457 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1458 intrmask = gfe_rx_process(sc, cause, intrmask); 1459 #endif 1460 1461 #ifndef GE_NOTX 1462 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1463 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1464 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1465 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1466 #endif 1467 if (cause & ETH_IR_MIIPhySTC) { 1468 sc->sc_flags |= GE_PHYSTSCHG; 1469 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1470 } 1471 } 1472 1473 GE_FUNC_EXIT(sc, ""); 1474 return claim; 1475 } 1476 1477 int 1479 gfe_mii_mediachange (struct ifnet *ifp) 1480 { 1481 struct gfe_softc *sc = ifp->if_softc; 1482 1483 if (ifp->if_flags & IFF_UP) 1484 mii_mediachg(&sc->sc_mii); 1485 1486 return (0); 1487 } 1488 void 1489 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1490 { 1491 struct gfe_softc *sc = ifp->if_softc; 1492 1493 if (sc->sc_flags & GE_PHYSTSCHG) { 1494 sc->sc_flags &= ~GE_PHYSTSCHG; 1495 mii_pollstat(&sc->sc_mii); 1496 } 1497 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1498 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1499 } 1500 1501 int 1502 gfe_mii_read (struct device *self, int phy, int reg) 1503 { 1504 return gt_mii_read(self, self->dv_parent, phy, reg); 1505 } 1506 1507 void 1508 gfe_mii_write (struct device *self, int phy, int reg, int value) 1509 { 1510 gt_mii_write(self, self->dv_parent, phy, reg, value); 1511 } 1512 1513 void 1514 gfe_mii_statchg (struct device *self) 1515 { 1516 /* struct gfe_softc *sc = (struct gfe_softc *) self; */ 1517 /* do nothing? */ 1518 } 1519 1520 int 1522 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1523 { 1524 int error = 0; 1525 GE_FUNC_ENTER(sc, "gfe_whack"); 1526 1527 switch (op) { 1528 case GE_WHACK_RESTART: 1529 #ifndef GE_NOTX 1530 gfe_tx_stop(sc, op); 1531 #endif 1532 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1533 /* FALLTHROUGH */ 1534 case GE_WHACK_START: 1535 #ifndef GE_NOHASH 1536 if (error == 0 && sc->sc_hashtable == NULL) { 1537 error = gfe_hash_alloc(sc); 1538 if (error) 1539 break; 1540 } 1541 if (op != GE_WHACK_RESTART) 1542 gfe_hash_fill(sc); 1543 #endif 1544 #ifndef GE_NORX 1545 if (op != GE_WHACK_RESTART) { 1546 error = gfe_rx_prime(sc); 1547 if (error) 1548 break; 1549 } 1550 #endif 1551 #ifndef GE_NOTX 1552 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1553 if (error) 1554 break; 1555 #endif 1556 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1557 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1558 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1559 GE_WRITE(sc, EICR, 0); 1560 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1561 #ifndef GE_NOHASH 1562 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1563 #endif 1564 #ifndef GE_NORX 1565 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1566 sc->sc_flags |= GE_RXACTIVE; 1567 #endif 1568 /* FALLTHROUGH */ 1569 case GE_WHACK_CHANGE: 1570 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1571 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1572 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1573 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1574 gfe_ifstart(&sc->sc_ec.ec_if); 1575 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1576 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1577 GE_FUNC_EXIT(sc, ""); 1578 return error; 1579 case GE_WHACK_STOP: 1580 break; 1581 } 1582 1583 #ifdef GE_DEBUG 1584 if (error) 1585 GE_DPRINTF(sc, (" failed: %d\n", error)); 1586 #endif 1587 GE_WRITE(sc, EPCR, sc->sc_pcr); 1588 GE_WRITE(sc, EIMR, 0); 1589 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1590 #ifndef GE_NOTX 1591 gfe_tx_stop(sc, GE_WHACK_STOP); 1592 #endif 1593 #ifndef GE_NORX 1594 gfe_rx_stop(sc, GE_WHACK_STOP); 1595 #endif 1596 #ifndef GE_NOHASH 1597 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1598 sc->sc_hashtable = NULL; 1599 #endif 1600 1601 GE_FUNC_EXIT(sc, ""); 1602 return error; 1603 } 1604 1605 int 1607 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1608 { 1609 uint32_t w0, add0, add1; 1610 uint32_t result; 1611 1612 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1613 add0 = ((uint32_t) eaddr[5] << 0) | 1614 ((uint32_t) eaddr[4] << 8) | 1615 ((uint32_t) eaddr[3] << 16); 1616 1617 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1618 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1619 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1620 1621 add1 = ((uint32_t) eaddr[2] << 0) | 1622 ((uint32_t) eaddr[1] << 8) | 1623 ((uint32_t) eaddr[0] << 16); 1624 1625 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1626 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1627 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1628 1629 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1630 /* 1631 * hashResult is the 15 bits Hash entry address. 1632 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1633 * MAC address, by nibble swapping in every byte (i.e MAC address 1634 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1635 */ 1636 1637 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1638 /* 1639 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1640 * 1641 * hashFunc0 calculates the hashResult in the following manner: 1642 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1643 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1644 */ 1645 result = (add0 & 3) | ((add0 >> 6) & ~3); 1646 result ^= (add0 >> 15) ^ (add1 >> 0); 1647 result &= 0x1ff; 1648 /* 1649 * hashResult[14:9] = ethernetADD[7:2] 1650 */ 1651 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1652 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1653 } else { 1654 #define TRIBITFLIP 073516240 /* yes its in octal */ 1655 /* 1656 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1657 * 1658 * hashFunc1 calculates the hashResult in the following manner: 1659 * hashResult[08:00] = ethernetADD[06:14] 1660 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1661 */ 1662 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1663 /* 1664 * Now bitswap those 9 bits 1665 */ 1666 result = 0; 1667 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1668 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1669 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1670 1671 /* 1672 * hashResult[14:09] = ethernetADD[00:05] 1673 */ 1674 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1675 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1676 GE_DPRINTF(sc, ("1(%#x)", result)); 1677 } 1678 GE_FUNC_EXIT(sc, ""); 1679 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1680 } 1681 1682 int 1683 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1684 enum gfe_rxprio prio, const u_int8_t eaddr[ETHER_ADDR_LEN]) 1685 { 1686 uint64_t he; 1687 uint64_t *maybe_he_p = NULL; 1688 int limit; 1689 int hash; 1690 int maybe_hash = 0; 1691 1692 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1693 1694 hash = gfe_hash_compute(sc, eaddr); 1695 1696 if (sc->sc_hashtable == NULL) { 1697 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1698 __LINE__); 1699 } 1700 1701 /* 1702 * Assume we are going to insert so create the hash entry we 1703 * are going to insert. We also use it to match entries we 1704 * will be removing. 1705 */ 1706 he = ((uint64_t) eaddr[5] << 43) | 1707 ((uint64_t) eaddr[4] << 35) | 1708 ((uint64_t) eaddr[3] << 27) | 1709 ((uint64_t) eaddr[2] << 19) | 1710 ((uint64_t) eaddr[1] << 11) | 1711 ((uint64_t) eaddr[0] << 3) | 1712 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1713 1714 /* 1715 * The GT will search upto 12 entries for a hit, so we must mimic that. 1716 */ 1717 hash &= sc->sc_hashmask / sizeof(he); 1718 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1719 /* 1720 * Does the GT wrap at the end, stop at the, or overrun the 1721 * end? Assume it wraps for now. Stash a copy of the 1722 * current hash entry. 1723 */ 1724 uint64_t *he_p = &sc->sc_hashtable[hash]; 1725 uint64_t thishe = *he_p; 1726 1727 /* 1728 * If the hash entry isn't valid, that break the chain. And 1729 * this entry a good candidate for reuse. 1730 */ 1731 if ((thishe & HSH_V) == 0) { 1732 maybe_he_p = he_p; 1733 break; 1734 } 1735 1736 /* 1737 * If the hash entry has the same address we are looking for 1738 * then ... if we are removing and the skip bit is set, its 1739 * already been removed. if are adding and the skip bit is 1740 * clear, then its already added. In either return EBUSY 1741 * indicating the op has already been done. Otherwise flip 1742 * the skip bit and return 0. 1743 */ 1744 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1745 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1746 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1747 return EBUSY; 1748 *he_p = thishe ^ HSH_S; 1749 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1750 hash * sizeof(he), sizeof(he), 1751 BUS_DMASYNC_PREWRITE); 1752 GE_FUNC_EXIT(sc, "^"); 1753 return 0; 1754 } 1755 1756 /* 1757 * If we haven't found a slot for the entry and this entry 1758 * is currently being skipped, return this entry. 1759 */ 1760 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1761 maybe_he_p = he_p; 1762 maybe_hash = hash; 1763 } 1764 1765 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1766 } 1767 1768 /* 1769 * If we got here, then there was no entry to remove. 1770 */ 1771 if (op == GE_HASH_REMOVE) { 1772 GE_FUNC_EXIT(sc, "?"); 1773 return ENOENT; 1774 } 1775 1776 /* 1777 * If we couldn't find a slot, return an error. 1778 */ 1779 if (maybe_he_p == NULL) { 1780 GE_FUNC_EXIT(sc, "!"); 1781 return ENOSPC; 1782 } 1783 1784 /* Update the entry. 1785 */ 1786 *maybe_he_p = he; 1787 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1788 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1789 GE_FUNC_EXIT(sc, "+"); 1790 return 0; 1791 } 1792 1793 int 1794 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1795 { 1796 struct gfe_softc * const sc = ec->ec_if.if_softc; 1797 int error; 1798 enum gfe_hash_op op; 1799 enum gfe_rxprio prio; 1800 1801 GE_FUNC_ENTER(sc, "hash_multichg"); 1802 /* 1803 * Is this a wildcard entry? If so and its being removed, recompute. 1804 */ 1805 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1806 if (cmd == SIOCDELMULTI) { 1807 GE_FUNC_EXIT(sc, ""); 1808 return ENETRESET; 1809 } 1810 1811 /* 1812 * Switch in 1813 */ 1814 sc->sc_flags |= GE_ALLMULTI; 1815 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1816 sc->sc_pcr |= ETH_EPCR_PM; 1817 GE_WRITE(sc, EPCR, sc->sc_pcr); 1818 GE_FUNC_EXIT(sc, ""); 1819 return 0; 1820 } 1821 GE_FUNC_EXIT(sc, ""); 1822 return ENETRESET; 1823 } 1824 1825 prio = GE_RXPRIO_MEDLO; 1826 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1827 1828 if (sc->sc_hashtable == NULL) { 1829 GE_FUNC_EXIT(sc, ""); 1830 return 0; 1831 } 1832 1833 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1834 if (error == EBUSY) { 1835 printf("%s: multichg: tried to %s %s again\n", 1836 sc->sc_dev.dv_xname, 1837 cmd == SIOCDELMULTI ? "remove" : "add", 1838 ether_sprintf(enm->enm_addrlo)); 1839 GE_FUNC_EXIT(sc, ""); 1840 return 0; 1841 } 1842 1843 if (error == ENOENT) { 1844 printf("%s: multichg: failed to remove %s: not in table\n", 1845 sc->sc_dev.dv_xname, 1846 ether_sprintf(enm->enm_addrlo)); 1847 GE_FUNC_EXIT(sc, ""); 1848 return 0; 1849 } 1850 1851 if (error == ENOSPC) { 1852 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1853 sc->sc_dev.dv_xname, 1854 ether_sprintf(enm->enm_addrlo)); 1855 GE_FUNC_EXIT(sc, ""); 1856 return ENETRESET; 1857 } 1858 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1859 sc->sc_dev.dv_xname, 1860 cmd == SIOCDELMULTI ? "remove" : "add", 1861 ether_sprintf(enm->enm_addrlo))); 1862 GE_FUNC_EXIT(sc, ""); 1863 return 0; 1864 } 1865 1866 int 1867 gfe_hash_fill(struct gfe_softc *sc) 1868 { 1869 struct ether_multistep step; 1870 struct ether_multi *enm; 1871 int error; 1872 1873 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1874 1875 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1876 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1877 if (error) 1878 GE_FUNC_EXIT(sc, "!"); 1879 return error; 1880 1881 sc->sc_flags &= ~GE_ALLMULTI; 1882 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1883 sc->sc_pcr &= ~ETH_EPCR_PM; 1884 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1885 while (enm != NULL) { 1886 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1887 sc->sc_flags |= GE_ALLMULTI; 1888 sc->sc_pcr |= ETH_EPCR_PM; 1889 } else { 1890 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1891 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1892 if (error == ENOSPC) 1893 break; 1894 } 1895 ETHER_NEXT_MULTI(step, enm); 1896 } 1897 1898 GE_FUNC_EXIT(sc, ""); 1899 return error; 1900 } 1901 1902 int 1903 gfe_hash_alloc(struct gfe_softc *sc) 1904 { 1905 int error; 1906 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1907 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1908 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1909 BUS_DMA_NOCACHE); 1910 if (error) { 1911 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1912 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1913 GE_FUNC_EXIT(sc, ""); 1914 return error; 1915 } 1916 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1917 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1918 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1919 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1920 GE_FUNC_EXIT(sc, ""); 1921 return 0; 1922 } 1923
Indexes created Tue Sep 30 10:09:55 GMT 2025