if_gfe.c revision 1.33
1 /* $NetBSD: if_gfe.c,v 1.33 2009/05/12 14:30:25 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.33 2009/05/12 14:30:25 cegger Exp $"); 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/types.h> 52 #include <sys/inttypes.h> 53 #include <sys/queue.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <sys/callout.h> 58 #include <sys/device.h> 59 #include <sys/errno.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/socket.h> 63 64 #include <sys/bus.h> 65 66 #include <net/if.h> 67 #include <net/if_dl.h> 68 #include <net/if_ether.h> 69 #include <net/if_media.h> 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <dev/mii/miivar.h> 80 81 #include <dev/marvell/gtintrreg.h> 82 #include <dev/marvell/gtethreg.h> 83 84 #include <dev/marvell/gtvar.h> 85 #include <dev/marvell/if_gfevar.h> 86 87 #define GE_READ(sc, reg) \ 88 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 89 #define GE_WRITE(sc, reg, v) \ 90 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 91 92 #define GE_DEBUG 93 #if 0 94 #define GE_NOHASH 95 #define GE_NORX 96 #endif 97 98 #ifdef GE_DEBUG 99 #define GE_DPRINTF(sc, a) do \ 100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 101 printf a; \ 102 while (0) 103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 105 #else 106 #define GE_DPRINTF(sc, a) do { } while (0) 107 #define GE_FUNC_ENTER(sc, func) do { } while (0) 108 #define GE_FUNC_EXIT(sc, str) do { } while (0) 109 #endif 110 enum gfe_whack_op { 111 GE_WHACK_START, GE_WHACK_RESTART, 112 GE_WHACK_CHANGE, GE_WHACK_STOP 113 }; 114 115 enum gfe_hash_op { 116 GE_HASH_ADD, GE_HASH_REMOVE, 117 }; 118 119 #if 1 120 #define htogt32(a) htobe32(a) 121 #define gt32toh(a) be32toh(a) 122 #else 123 #define htogt32(a) htole32(a) 124 #define gt32toh(a) le32toh(a) 125 #endif 126 127 #define GE_RXDSYNC(sc, rxq, n, ops) \ 128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 130 (ops)) 131 #define GE_RXDPRESYNC(sc, rxq, n) \ 132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 133 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 135 136 #define GE_TXDSYNC(sc, txq, n, ops) \ 137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 139 (ops)) 140 #define GE_TXDPRESYNC(sc, txq, n) \ 141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 142 #define GE_TXDPOSTSYNC(sc, txq, n) \ 143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 144 145 #define STATIC 146 147 STATIC int gfe_match (device_t, cfdata_t, void *); 148 STATIC void gfe_attach (device_t, device_t, void *); 149 150 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 151 size_t, int); 152 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 153 154 STATIC int gfe_ifioctl (struct ifnet *, u_long, void *); 155 STATIC void gfe_ifstart (struct ifnet *); 156 STATIC void gfe_ifwatchdog (struct ifnet *); 157 158 STATIC int gfe_mii_read (device_t, int, int); 159 STATIC void gfe_mii_write (device_t, int, int, int); 160 STATIC void gfe_mii_statchg (device_t); 161 162 STATIC void gfe_tick(void *arg); 163 164 STATIC void gfe_tx_restart(void *); 165 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 166 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 167 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 168 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 169 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 170 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 171 172 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 173 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 174 STATIC int gfe_rx_prime(struct gfe_softc *); 175 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 176 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 177 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 178 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 179 180 STATIC int gfe_intr(void *); 181 182 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 183 184 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 185 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 186 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 187 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 188 u_long); 189 STATIC int gfe_hash_fill(struct gfe_softc *); 190 STATIC int gfe_hash_alloc(struct gfe_softc *); 191 192 /* Linkup to the rest of the kernel */ 193 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 194 gfe_match, gfe_attach, NULL, NULL); 195 196 extern struct cfdriver gfe_cd; 197 198 int 199 gfe_match(device_t parent, cfdata_t cf, void *aux) 200 { 201 struct gt_softc *gt = (struct gt_softc *) parent; 202 struct gt_attach_args *ga = aux; 203 uint8_t enaddr[6]; 204 205 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 206 return 0; 207 208 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 209 return 0; 210 211 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 212 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 213 return 0; 214 215 return 1; 216 } 217 218 /* 219 * Attach this instance, and then all the sub-devices 220 */ 221 void 222 gfe_attach(device_t parent, device_t self, void *aux) 223 { 224 struct gt_attach_args * const ga = aux; 225 struct gt_softc * const gt = device_private(parent); 226 struct gfe_softc * const sc = device_private(self); 227 struct ifnet * const ifp = &sc->sc_ec.ec_if; 228 uint32_t data; 229 uint8_t enaddr[6]; 230 int phyaddr; 231 uint32_t sdcr; 232 int error; 233 234 GT_ETHERFOUND(gt, ga); 235 236 sc->sc_gt_memt = ga->ga_memt; 237 sc->sc_gt_memh = ga->ga_memh; 238 sc->sc_dmat = ga->ga_dmat; 239 sc->sc_macno = ga->ga_unit; 240 241 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 242 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 243 aprint_error(": failed to map registers\n"); 244 } 245 246 callout_init(&sc->sc_co, 0); 247 248 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 249 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 250 251 gtget_macaddr(gt, sc->sc_macno, enaddr); 252 253 sc->sc_pcr = GE_READ(sc, EPCR); 254 sc->sc_pcxr = GE_READ(sc, EPCXR); 255 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 256 257 aprint_normal(": address %s", ether_sprintf(enaddr)); 258 259 #if defined(DEBUG) 260 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 261 #endif 262 263 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 264 if (device_cfdata(&sc->sc_dev)->cf_flags & 1) { 265 aprint_normal(", phy %d (rmii)", phyaddr); 266 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 267 } else { 268 aprint_normal(", phy %d (mii)", phyaddr); 269 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 270 } 271 if (device_cfdata(&sc->sc_dev)->cf_flags & 2) 272 sc->sc_flags |= GE_NOFREE; 273 sc->sc_pcxr &= ~(3 << 14); 274 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 275 276 if (sc->sc_pcr & ETH_EPCR_EN) { 277 int tries = 1000; 278 /* 279 * Abort transmitter and receiver and wait for them to quiese 280 */ 281 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 282 do { 283 delay(100); 284 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 285 } 286 287 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 288 289 #if defined(DEBUG) 290 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 291 #endif 292 293 /* 294 * Now turn off the GT. If it didn't quiese, too ***ing bad. 295 */ 296 GE_WRITE(sc, EPCR, sc->sc_pcr); 297 GE_WRITE(sc, EIMR, sc->sc_intrmask); 298 sdcr = GE_READ(sc, ESDCR); 299 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 300 sdcr |= ETH_ESDCR_RIFB; 301 GE_WRITE(sc, ESDCR, sdcr); 302 sc->sc_max_frame_length = 1536; 303 304 aprint_normal("\n"); 305 sc->sc_mii.mii_ifp = ifp; 306 sc->sc_mii.mii_readreg = gfe_mii_read; 307 sc->sc_mii.mii_writereg = gfe_mii_write; 308 sc->sc_mii.mii_statchg = gfe_mii_statchg; 309 310 sc->sc_ec.ec_mii = &sc->sc_mii; 311 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 312 ether_mediastatus); 313 314 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 315 MII_OFFSET_ANY, MIIF_NOISOLATE); 316 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 317 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 318 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 319 } else { 320 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 321 } 322 323 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 324 ifp->if_softc = sc; 325 /* ifp->if_mowner = &sc->sc_mowner; */ 326 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 327 #if 0 328 ifp->if_flags |= IFF_DEBUG; 329 #endif 330 ifp->if_ioctl = gfe_ifioctl; 331 ifp->if_start = gfe_ifstart; 332 ifp->if_watchdog = gfe_ifwatchdog; 333 334 if (sc->sc_flags & GE_NOFREE) { 335 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 336 if (!error) 337 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 338 if (!error) 339 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 340 if (!error) 341 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 342 if (!error) 343 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 344 if (!error) 345 error = gfe_hash_alloc(sc); 346 if (error) 347 aprint_error( 348 "%s: failed to allocate resources: %d\n", 349 ifp->if_xname, error); 350 } 351 352 if_attach(ifp); 353 ether_ifattach(ifp, enaddr); 354 #if NBPFILTER > 0 355 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 356 #endif 357 #if NRND > 0 358 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 0); 359 #endif 360 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 361 gfe_intr, sc); 362 } 363 364 int 365 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 366 size_t size, int flags) 367 { 368 int error = 0; 369 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 370 371 KASSERT(gdm->gdm_kva == NULL); 372 gdm->gdm_size = size; 373 gdm->gdm_maxsegs = maxsegs; 374 375 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 376 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 377 BUS_DMA_NOWAIT); 378 if (error) 379 goto fail; 380 381 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 382 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 383 if (error) 384 goto fail; 385 386 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 387 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 388 if (error) 389 goto fail; 390 391 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 392 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 393 if (error) 394 goto fail; 395 396 /* invalidate from cache */ 397 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 398 BUS_DMASYNC_PREREAD); 399 fail: 400 if (error) { 401 gfe_dmamem_free(sc, gdm); 402 GE_DPRINTF(sc, (":err=%d", error)); 403 } 404 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 405 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 406 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 407 GE_FUNC_EXIT(sc, ""); 408 return error; 409 } 410 411 void 412 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 413 { 414 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 415 if (gdm->gdm_map) 416 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 417 if (gdm->gdm_kva) 418 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 419 if (gdm->gdm_nsegs > 0) 420 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 421 gdm->gdm_map = NULL; 422 gdm->gdm_kva = NULL; 423 gdm->gdm_nsegs = 0; 424 GE_FUNC_EXIT(sc, ""); 425 } 426 427 int 428 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 429 { 430 struct gfe_softc * const sc = ifp->if_softc; 431 struct ifreq *ifr = (struct ifreq *) data; 432 struct ifaddr *ifa = (struct ifaddr *) data; 433 int s, error = 0; 434 435 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 436 s = splnet(); 437 438 switch (cmd) { 439 case SIOCINITIFADDR: 440 ifp->if_flags |= IFF_UP; 441 error = gfe_whack(sc, GE_WHACK_START); 442 switch (ifa->ifa_addr->sa_family) { 443 #ifdef INET 444 case AF_INET: 445 if (error == 0) 446 arp_ifinit(ifp, ifa); 447 break; 448 #endif 449 default: 450 break; 451 } 452 break; 453 454 case SIOCSIFFLAGS: 455 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 456 break; 457 /* XXX re-use ether_ioctl() */ 458 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 459 case IFF_UP|IFF_RUNNING:/* active->active, update */ 460 error = gfe_whack(sc, GE_WHACK_CHANGE); 461 break; 462 case IFF_RUNNING: /* not up, so we stop */ 463 error = gfe_whack(sc, GE_WHACK_STOP); 464 break; 465 case IFF_UP: /* not running, so we start */ 466 error = gfe_whack(sc, GE_WHACK_START); 467 break; 468 case 0: /* idle->idle: do nothing */ 469 break; 470 } 471 break; 472 473 case SIOCSIFMEDIA: 474 case SIOCGIFMEDIA: 475 case SIOCADDMULTI: 476 case SIOCDELMULTI: 477 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 478 if (ifp->if_flags & IFF_RUNNING) 479 error = gfe_whack(sc, GE_WHACK_CHANGE); 480 else 481 error = 0; 482 } 483 break; 484 485 case SIOCSIFMTU: 486 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 487 error = EINVAL; 488 break; 489 } 490 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 491 error = 0; 492 break; 493 494 default: 495 error = ether_ioctl(ifp, cmd, data); 496 break; 497 } 498 splx(s); 499 GE_FUNC_EXIT(sc, ""); 500 return error; 501 } 502 503 void 504 gfe_ifstart(struct ifnet *ifp) 505 { 506 struct gfe_softc * const sc = ifp->if_softc; 507 struct mbuf *m; 508 509 GE_FUNC_ENTER(sc, "gfe_ifstart"); 510 511 if ((ifp->if_flags & IFF_RUNNING) == 0) { 512 GE_FUNC_EXIT(sc, "$"); 513 return; 514 } 515 516 for (;;) { 517 IF_DEQUEUE(&ifp->if_snd, m); 518 if (m == NULL) { 519 ifp->if_flags &= ~IFF_OACTIVE; 520 GE_FUNC_EXIT(sc, ""); 521 return; 522 } 523 524 /* 525 * No space in the pending queue? try later. 526 */ 527 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 528 break; 529 530 /* 531 * Try to enqueue a mbuf to the device. If that fails, we 532 * can always try to map the next mbuf. 533 */ 534 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 535 GE_DPRINTF(sc, (">")); 536 #ifndef GE_NOTX 537 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 538 #endif 539 } 540 541 /* 542 * Attempt to queue the mbuf for send failed. 543 */ 544 IF_PREPEND(&ifp->if_snd, m); 545 ifp->if_flags |= IFF_OACTIVE; 546 GE_FUNC_EXIT(sc, "%%"); 547 } 548 549 void 550 gfe_ifwatchdog(struct ifnet *ifp) 551 { 552 struct gfe_softc * const sc = ifp->if_softc; 553 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 554 555 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 556 printf("%s: device timeout", device_xname(&sc->sc_dev)); 557 if (ifp->if_flags & IFF_RUNNING) { 558 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 559 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 560 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 561 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 562 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 563 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 564 GE_READ(sc, EICR)); 565 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 566 GE_TXDPRESYNC(sc, txq, curtxdnum); 567 } 568 printf("\n"); 569 ifp->if_oerrors++; 570 (void) gfe_whack(sc, GE_WHACK_RESTART); 571 GE_FUNC_EXIT(sc, ""); 572 } 573 574 int 576 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 577 { 578 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 579 int error; 580 581 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 582 GE_DPRINTF(sc, ("(%d)", rxprio)); 583 584 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 585 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 586 if (error) { 587 GE_FUNC_EXIT(sc, "!!"); 588 return error; 589 } 590 591 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 592 GE_RXBUF_MEMSIZE, 0); 593 if (error) { 594 GE_FUNC_EXIT(sc, "!!!"); 595 return error; 596 } 597 GE_FUNC_EXIT(sc, ""); 598 return error; 599 } 600 601 int 602 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 603 { 604 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 605 volatile struct gt_eth_desc *rxd; 606 const bus_dma_segment_t *ds; 607 int idx; 608 bus_addr_t nxtaddr; 609 bus_size_t boff; 610 611 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 612 GE_DPRINTF(sc, ("(%d)", rxprio)); 613 614 if ((sc->sc_flags & GE_NOFREE) == 0) { 615 int error = gfe_rx_rxqalloc(sc, rxprio); 616 if (error) { 617 GE_FUNC_EXIT(sc, "!"); 618 return error; 619 } 620 } else { 621 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 622 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 623 } 624 625 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 626 627 rxq->rxq_descs = 628 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 629 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 630 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 631 rxq->rxq_fi = 0; 632 rxq->rxq_active = GE_RXDESC_MAX; 633 for (idx = 0, rxd = rxq->rxq_descs, 634 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 635 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 636 idx < GE_RXDESC_MAX; 637 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 638 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 639 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 640 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 641 /* 642 * update the nxtptr to point to the next txd. 643 */ 644 if (idx == GE_RXDESC_MAX - 1) 645 nxtaddr = rxq->rxq_desc_busaddr; 646 rxd->ed_nxtptr = htogt32(nxtaddr); 647 boff += GE_RXBUF_SIZE; 648 if (boff == ds->ds_len) { 649 ds++; 650 boff = 0; 651 } 652 } 653 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 654 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 655 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 656 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 657 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 658 BUS_DMASYNC_PREREAD); 659 660 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 661 switch (rxprio) { 662 case GE_RXPRIO_HI: 663 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 664 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 665 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 666 break; 667 case GE_RXPRIO_MEDHI: 668 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 669 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 670 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 671 break; 672 case GE_RXPRIO_MEDLO: 673 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 674 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 675 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 676 break; 677 case GE_RXPRIO_LO: 678 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 679 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 680 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 681 break; 682 } 683 GE_FUNC_EXIT(sc, ""); 684 return 0; 685 } 686 687 void 688 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 689 { 690 struct ifnet * const ifp = &sc->sc_ec.ec_if; 691 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 692 struct mbuf *m = rxq->rxq_curpkt; 693 694 GE_FUNC_ENTER(sc, "gfe_rx_get"); 695 GE_DPRINTF(sc, ("(%d)", rxprio)); 696 697 while (rxq->rxq_active > 0) { 698 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 699 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 700 const struct ether_header *eh; 701 unsigned int cmdsts; 702 size_t buflen; 703 704 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 705 cmdsts = gt32toh(rxd->ed_cmdsts); 706 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 707 rxq->rxq_cmdsts = cmdsts; 708 /* 709 * Sometimes the GE "forgets" to reset the ownership bit. 710 * But if the length has been rewritten, the packet is ours 711 * so pretend the O bit is set. 712 */ 713 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 714 if ((cmdsts & RX_CMD_O) && buflen == 0) { 715 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 716 break; 717 } 718 719 /* 720 * If this is not a single buffer packet with no errors 721 * or for some reason it's bigger than our frame size, 722 * ignore it and go to the next packet. 723 */ 724 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 725 (RX_CMD_F|RX_CMD_L) || 726 buflen > sc->sc_max_frame_length) { 727 GE_DPRINTF(sc, ("!")); 728 --rxq->rxq_active; 729 ifp->if_ipackets++; 730 ifp->if_ierrors++; 731 goto give_it_back; 732 } 733 734 /* CRC is included with the packet; trim it off. */ 735 buflen -= ETHER_CRC_LEN; 736 737 if (m == NULL) { 738 MGETHDR(m, M_DONTWAIT, MT_DATA); 739 if (m == NULL) { 740 GE_DPRINTF(sc, ("?")); 741 break; 742 } 743 } 744 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 745 MCLGET(m, M_DONTWAIT); 746 if ((m->m_flags & M_EXT) == 0) { 747 GE_DPRINTF(sc, ("?")); 748 break; 749 } 750 } 751 m->m_data += 2; 752 m->m_len = 0; 753 m->m_pkthdr.len = 0; 754 m->m_pkthdr.rcvif = ifp; 755 rxq->rxq_cmdsts = cmdsts; 756 --rxq->rxq_active; 757 758 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 759 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 760 761 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 762 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 763 m->m_len = buflen; 764 m->m_pkthdr.len = buflen; 765 766 ifp->if_ipackets++; 767 #if NBPFILTER > 0 768 if (ifp->if_bpf != NULL) 769 bpf_mtap(ifp->if_bpf, m); 770 #endif 771 772 eh = (const struct ether_header *) m->m_data; 773 if ((ifp->if_flags & IFF_PROMISC) || 774 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 775 (rxq->rxq_cmdsts & RX_STS_HE) || 776 (eh->ether_dhost[0] & 1) != 0 || 777 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 778 ETHER_ADDR_LEN) == 0) { 779 (*ifp->if_input)(ifp, m); 780 m = NULL; 781 GE_DPRINTF(sc, (">")); 782 } else { 783 m->m_len = 0; 784 m->m_pkthdr.len = 0; 785 GE_DPRINTF(sc, ("+")); 786 } 787 rxq->rxq_cmdsts = 0; 788 789 give_it_back: 790 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 791 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 792 #if 0 793 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 794 rxq->rxq_fi, 795 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 796 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 797 #endif 798 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 799 if (++rxq->rxq_fi == GE_RXDESC_MAX) 800 rxq->rxq_fi = 0; 801 rxq->rxq_active++; 802 } 803 rxq->rxq_curpkt = m; 804 GE_FUNC_EXIT(sc, ""); 805 } 806 807 uint32_t 808 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 809 { 810 struct ifnet * const ifp = &sc->sc_ec.ec_if; 811 struct gfe_rxqueue *rxq; 812 uint32_t rxbits; 813 #define RXPRIO_DECODER 0xffffaa50 814 GE_FUNC_ENTER(sc, "gfe_rx_process"); 815 816 rxbits = ETH_IR_RxBuffer_GET(cause); 817 while (rxbits) { 818 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 819 GE_DPRINTF(sc, ("%1x", rxbits)); 820 rxbits &= ~(1 << rxprio); 821 gfe_rx_get(sc, rxprio); 822 } 823 824 rxbits = ETH_IR_RxError_GET(cause); 825 while (rxbits) { 826 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 827 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 828 int idx; 829 rxbits &= ~(1 << rxprio); 830 rxq = &sc->sc_rxq[rxprio]; 831 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 832 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 833 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 834 sc->sc_tickflags |= GE_TICK_RX_RESTART; 835 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 836 } 837 ifp->if_ierrors++; 838 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 839 device_xname(&sc->sc_dev), rxprio, rxq->rxq_fi)); 840 memset(masks, 0, sizeof(masks)); 841 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 842 0, rxq->rxq_desc_mem.gdm_size, 843 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 844 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 845 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 846 847 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 848 masks[idx/32] |= 1 << (idx & 31); 849 } 850 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 851 0, rxq->rxq_desc_mem.gdm_size, 852 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 853 #if defined(DEBUG) 854 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 855 device_xname(&sc->sc_dev), rxprio, rxq->rxq_fi, 856 rxq->rxq_cmdsts, masks[0], masks[1]); 857 #endif 858 } 859 if ((intrmask & ETH_IR_RxBits) == 0) 860 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 861 862 GE_FUNC_EXIT(sc, ""); 863 return intrmask; 864 } 865 866 int 867 gfe_rx_prime(struct gfe_softc *sc) 868 { 869 struct gfe_rxqueue *rxq; 870 int error; 871 872 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 873 874 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 875 if (error) 876 goto bail; 877 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 878 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 879 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 880 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 881 } 882 sc->sc_intrmask |= rxq->rxq_intrbits; 883 884 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 885 if (error) 886 goto bail; 887 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 888 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 889 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 890 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 891 sc->sc_intrmask |= rxq->rxq_intrbits; 892 } 893 894 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 895 if (error) 896 goto bail; 897 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 898 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 899 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 900 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 901 sc->sc_intrmask |= rxq->rxq_intrbits; 902 } 903 904 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 905 if (error) 906 goto bail; 907 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 908 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 909 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 910 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 911 sc->sc_intrmask |= rxq->rxq_intrbits; 912 } 913 914 bail: 915 GE_FUNC_EXIT(sc, ""); 916 return error; 917 } 918 919 void 920 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 921 { 922 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 923 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 924 if (rxq == NULL) { 925 GE_FUNC_EXIT(sc, ""); 926 return; 927 } 928 929 if (rxq->rxq_curpkt) 930 m_freem(rxq->rxq_curpkt); 931 if ((sc->sc_flags & GE_NOFREE) == 0) { 932 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 933 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 934 } 935 GE_FUNC_EXIT(sc, ""); 936 } 937 938 void 939 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 940 { 941 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 942 sc->sc_flags &= ~GE_RXACTIVE; 943 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 944 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 945 GE_WRITE(sc, EIMR, sc->sc_intrmask); 946 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 947 do { 948 delay(10); 949 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 950 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 951 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 952 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 953 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 954 GE_FUNC_EXIT(sc, ""); 955 } 956 957 void 959 gfe_tick(void *arg) 960 { 961 struct gfe_softc * const sc = arg; 962 uint32_t intrmask; 963 unsigned int tickflags; 964 int s; 965 966 GE_FUNC_ENTER(sc, "gfe_tick"); 967 968 s = splnet(); 969 970 tickflags = sc->sc_tickflags; 971 sc->sc_tickflags = 0; 972 intrmask = sc->sc_intrmask; 973 if (tickflags & GE_TICK_TX_IFSTART) 974 gfe_ifstart(&sc->sc_ec.ec_if); 975 if (tickflags & GE_TICK_RX_RESTART) { 976 intrmask |= sc->sc_idlemask; 977 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 978 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 979 rxq->rxq_fi = 0; 980 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 981 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 982 } 983 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 984 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 985 rxq->rxq_fi = 0; 986 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 987 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 988 } 989 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 990 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 991 rxq->rxq_fi = 0; 992 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 993 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 994 } 995 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 996 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 997 rxq->rxq_fi = 0; 998 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 999 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 1000 } 1001 sc->sc_idlemask = 0; 1002 } 1003 if (intrmask != sc->sc_intrmask) { 1004 sc->sc_intrmask = intrmask; 1005 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1006 } 1007 gfe_intr(sc); 1008 splx(s); 1009 1010 GE_FUNC_EXIT(sc, ""); 1011 } 1012 1013 int 1014 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1015 { 1016 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1017 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1018 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1019 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1020 uint32_t intrmask = sc->sc_intrmask; 1021 size_t buflen; 1022 struct mbuf *m; 1023 1024 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1025 1026 /* 1027 * Anything in the pending queue to enqueue? if not, punt. Likewise 1028 * if the txq is not yet created. 1029 * otherwise grab its dmamap. 1030 */ 1031 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1032 GE_FUNC_EXIT(sc, "-"); 1033 return 0; 1034 } 1035 1036 /* 1037 * Have we [over]consumed our limit of descriptors? 1038 * Do we have enough free descriptors? 1039 */ 1040 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1041 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1042 uint32_t cmdsts; 1043 size_t pktlen; 1044 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1045 cmdsts = gt32toh(txd2->ed_cmdsts); 1046 if (cmdsts & TX_CMD_O) { 1047 int nextin; 1048 /* 1049 * Sometime the Discovery forgets to update the 1050 * last descriptor. See if we own the descriptor 1051 * after it (since we know we've turned that to 1052 * the discovery and if we owned it, the Discovery 1053 * gave it back). If we do, we know the Discovery 1054 * gave back this one but forgot to mark it as ours. 1055 */ 1056 nextin = txq->txq_fi + 1; 1057 if (nextin == GE_TXDESC_MAX) 1058 nextin = 0; 1059 GE_TXDPOSTSYNC(sc, txq, nextin); 1060 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1061 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1062 GE_TXDPRESYNC(sc, txq, nextin); 1063 GE_FUNC_EXIT(sc, "@"); 1064 return 0; 1065 } 1066 #ifdef DEBUG 1067 printf("%s: txenqueue: transmitter resynced at %d\n", 1068 device_xname(&sc->sc_dev), txq->txq_fi); 1069 #endif 1070 } 1071 if (++txq->txq_fi == GE_TXDESC_MAX) 1072 txq->txq_fi = 0; 1073 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1074 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1075 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1076 txq->txq_nactive--; 1077 1078 /* statistics */ 1079 ifp->if_opackets++; 1080 if (cmdsts & TX_STS_ES) 1081 ifp->if_oerrors++; 1082 GE_DPRINTF(sc, ("%%")); 1083 } 1084 1085 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1086 1087 /* 1088 * If this packet would wrap around the end of the buffer, reset back 1089 * to the beginning. 1090 */ 1091 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1092 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1093 txq->txq_outptr = 0; 1094 } 1095 1096 /* 1097 * Make sure the output packet doesn't run over the beginning of 1098 * what we've already given the GT. 1099 */ 1100 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1101 txq->txq_outptr + buflen > txq->txq_inptr) { 1102 intrmask |= txq->txq_intrbits & 1103 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1104 if (sc->sc_intrmask != intrmask) { 1105 sc->sc_intrmask = intrmask; 1106 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1107 } 1108 GE_FUNC_EXIT(sc, "#"); 1109 return 0; 1110 } 1111 1112 /* 1113 * The end-of-list descriptor we put on last time is the starting point 1114 * for this packet. The GT is supposed to terminate list processing on 1115 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1116 * must terminate the list. 1117 */ 1118 intrmask = sc->sc_intrmask; 1119 1120 m_copydata(m, 0, m->m_pkthdr.len, 1121 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1122 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1123 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1124 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1125 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1126 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1127 1128 /* 1129 * Request a buffer interrupt every 2/3 of the way thru the transmit 1130 * buffer. 1131 */ 1132 txq->txq_ei_gapcount += buflen; 1133 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1134 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1135 txq->txq_ei_gapcount = 0; 1136 } else { 1137 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1138 } 1139 #if 0 1140 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1141 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1142 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1143 #endif 1144 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1145 1146 txq->txq_outptr += buflen; 1147 /* 1148 * Tell the SDMA engine to "Fetch!" 1149 */ 1150 GE_WRITE(sc, ESDCMR, 1151 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1152 1153 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1154 1155 /* 1156 * Update the last out appropriately. 1157 */ 1158 txq->txq_nactive++; 1159 if (++txq->txq_lo == GE_TXDESC_MAX) 1160 txq->txq_lo = 0; 1161 1162 /* 1163 * Move mbuf from the pending queue to the snd queue. 1164 */ 1165 IF_DEQUEUE(&txq->txq_pendq, m); 1166 #if NBPFILTER > 0 1167 if (ifp->if_bpf != NULL) 1168 bpf_mtap(ifp->if_bpf, m); 1169 #endif 1170 m_freem(m); 1171 ifp->if_flags &= ~IFF_OACTIVE; 1172 1173 /* 1174 * Since we have put an item into the packet queue, we now want 1175 * an interrupt when the transmit queue finishes processing the 1176 * list. But only update the mask if needs changing. 1177 */ 1178 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1179 if (sc->sc_intrmask != intrmask) { 1180 sc->sc_intrmask = intrmask; 1181 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1182 } 1183 if (ifp->if_timer == 0) 1184 ifp->if_timer = 5; 1185 GE_FUNC_EXIT(sc, "*"); 1186 return 1; 1187 } 1188 1189 uint32_t 1190 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1191 { 1192 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1193 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1194 1195 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1196 1197 if (txq == NULL) { 1198 GE_FUNC_EXIT(sc, ""); 1199 return intrmask; 1200 } 1201 1202 while (txq->txq_nactive > 0) { 1203 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1204 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1205 uint32_t cmdsts; 1206 size_t pktlen; 1207 1208 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1209 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1210 int nextin; 1211 1212 if (txq->txq_nactive == 1) { 1213 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1214 GE_FUNC_EXIT(sc, ""); 1215 return intrmask; 1216 } 1217 /* 1218 * Sometimes the Discovery forgets to update the 1219 * ownership bit in the descriptor. See if we own the 1220 * descriptor after it (since we know we've turned 1221 * that to the Discovery and if we own it now then the 1222 * Discovery gave it back). If we do, we know the 1223 * Discovery gave back this one but forgot to mark it 1224 * as ours. 1225 */ 1226 nextin = txq->txq_fi + 1; 1227 if (nextin == GE_TXDESC_MAX) 1228 nextin = 0; 1229 GE_TXDPOSTSYNC(sc, txq, nextin); 1230 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1231 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1232 GE_TXDPRESYNC(sc, txq, nextin); 1233 GE_FUNC_EXIT(sc, ""); 1234 return intrmask; 1235 } 1236 #ifdef DEBUG 1237 printf("%s: txdone: transmitter resynced at %d\n", 1238 device_xname(&sc->sc_dev), txq->txq_fi); 1239 #endif 1240 } 1241 #if 0 1242 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1243 txq->txq_lo, 1244 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1245 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1246 #endif 1247 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1248 if (++txq->txq_fi == GE_TXDESC_MAX) 1249 txq->txq_fi = 0; 1250 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1251 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1252 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1253 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1254 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1255 1256 /* statistics */ 1257 ifp->if_opackets++; 1258 if (cmdsts & TX_STS_ES) 1259 ifp->if_oerrors++; 1260 1261 /* txd->ed_bufptr = 0; */ 1262 1263 ifp->if_timer = 5; 1264 --txq->txq_nactive; 1265 } 1266 if (txq->txq_nactive != 0) 1267 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1268 device_xname(&sc->sc_dev), txprio, txq->txq_nactive); 1269 ifp->if_timer = 0; 1270 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1271 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1272 GE_FUNC_EXIT(sc, ""); 1273 return intrmask; 1274 } 1275 1276 int 1277 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1278 { 1279 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1280 int error; 1281 1282 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1283 1284 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1285 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1286 if (error) { 1287 GE_FUNC_EXIT(sc, ""); 1288 return error; 1289 } 1290 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1291 if (error) { 1292 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1293 GE_FUNC_EXIT(sc, ""); 1294 return error; 1295 } 1296 GE_FUNC_EXIT(sc, ""); 1297 return 0; 1298 } 1299 1300 int 1301 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1302 { 1303 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1304 volatile struct gt_eth_desc *txd; 1305 unsigned int i; 1306 bus_addr_t addr; 1307 1308 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1309 1310 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1311 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1312 1313 if (sc->sc_flags & GE_NOFREE) { 1314 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1315 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1316 } else { 1317 int error = gfe_tx_txqalloc(sc, txprio); 1318 if (error) { 1319 GE_FUNC_EXIT(sc, "!"); 1320 return error; 1321 } 1322 } 1323 1324 txq->txq_descs = 1325 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1326 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1327 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1328 1329 txq->txq_pendq.ifq_maxlen = 10; 1330 txq->txq_ei_gapcount = 0; 1331 txq->txq_nactive = 0; 1332 txq->txq_fi = 0; 1333 txq->txq_lo = 0; 1334 txq->txq_inptr = GE_TXBUF_SIZE; 1335 txq->txq_outptr = 0; 1336 for (i = 0, txd = txq->txq_descs, 1337 addr = txq->txq_desc_busaddr + sizeof(*txd); 1338 i < GE_TXDESC_MAX - 1; 1339 i++, txd++, addr += sizeof(*txd)) { 1340 /* 1341 * update the nxtptr to point to the next txd. 1342 */ 1343 txd->ed_cmdsts = 0; 1344 txd->ed_nxtptr = htogt32(addr); 1345 } 1346 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1347 htogt32(txq->txq_desc_busaddr); 1348 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1349 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1350 1351 switch (txprio) { 1352 case GE_TXPRIO_HI: 1353 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1354 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1355 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1356 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1357 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1358 break; 1359 1360 case GE_TXPRIO_LO: 1361 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1362 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1363 txq->txq_epsrbits = ETH_EPSR_TxLow; 1364 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1365 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1366 break; 1367 1368 case GE_TXPRIO_NONE: 1369 break; 1370 } 1371 #if 0 1372 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1373 gt_write(device_parent(&sc->sc_dev), txq->txq_ectdp, 1374 txq->txq_desc_busaddr); 1375 GE_DPRINTF(sc, (")")); 1376 #endif 1377 1378 /* 1379 * If we are restarting, there may be packets in the pending queue 1380 * waiting to be enqueued. Try enqueuing packets from both priority 1381 * queues until the pending queue is empty or there no room for them 1382 * on the device. 1383 */ 1384 while (gfe_tx_enqueue(sc, txprio)) 1385 continue; 1386 1387 GE_FUNC_EXIT(sc, ""); 1388 return 0; 1389 } 1390 1391 void 1392 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1393 { 1394 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1395 1396 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1397 if (txq == NULL) { 1398 GE_FUNC_EXIT(sc, ""); 1399 return; 1400 } 1401 1402 if (!flush) { 1403 GE_FUNC_EXIT(sc, ""); 1404 return; 1405 } 1406 1407 if ((sc->sc_flags & GE_NOFREE) == 0) { 1408 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1409 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1410 } 1411 GE_FUNC_EXIT(sc, "-F"); 1412 } 1413 1414 void 1415 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1416 { 1417 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1418 1419 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1420 1421 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1422 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1423 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1424 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1425 1426 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1427 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1428 1429 sc->sc_ec.ec_if.if_timer = 0; 1430 GE_FUNC_EXIT(sc, ""); 1431 } 1432 1433 int 1435 gfe_intr(void *arg) 1436 { 1437 struct gfe_softc * const sc = arg; 1438 uint32_t cause; 1439 uint32_t intrmask = sc->sc_intrmask; 1440 int claim = 0; 1441 int cnt; 1442 1443 GE_FUNC_ENTER(sc, "gfe_intr"); 1444 1445 for (cnt = 0; cnt < 4; cnt++) { 1446 if (sc->sc_intrmask != intrmask) { 1447 sc->sc_intrmask = intrmask; 1448 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1449 } 1450 cause = GE_READ(sc, EICR); 1451 cause &= sc->sc_intrmask; 1452 GE_DPRINTF(sc, (".%#x", cause)); 1453 if (cause == 0) 1454 break; 1455 1456 claim = 1; 1457 1458 GE_WRITE(sc, EICR, ~cause); 1459 #ifndef GE_NORX 1460 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1461 intrmask = gfe_rx_process(sc, cause, intrmask); 1462 #endif 1463 1464 #ifndef GE_NOTX 1465 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1466 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1467 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1468 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1469 #endif 1470 if (cause & ETH_IR_MIIPhySTC) { 1471 sc->sc_flags |= GE_PHYSTSCHG; 1472 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1473 } 1474 } 1475 1476 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1477 continue; 1478 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1479 continue; 1480 1481 GE_FUNC_EXIT(sc, ""); 1482 return claim; 1483 } 1484 1485 int 1487 gfe_mii_read (device_t self, int phy, int reg) 1488 { 1489 return gt_mii_read(self, device_parent(self), phy, reg); 1490 } 1491 1492 void 1493 gfe_mii_write (device_t self, int phy, int reg, int value) 1494 { 1495 gt_mii_write(self, device_parent(self), phy, reg, value); 1496 } 1497 1498 void 1499 gfe_mii_statchg (device_t self) 1500 { 1501 /* struct gfe_softc *sc = device_private(self); */ 1502 /* do nothing? */ 1503 } 1504 1505 int 1507 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1508 { 1509 int error = 0; 1510 GE_FUNC_ENTER(sc, "gfe_whack"); 1511 1512 switch (op) { 1513 case GE_WHACK_RESTART: 1514 #ifndef GE_NOTX 1515 gfe_tx_stop(sc, op); 1516 #endif 1517 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1518 /* FALLTHROUGH */ 1519 case GE_WHACK_START: 1520 #ifndef GE_NOHASH 1521 if (error == 0 && sc->sc_hashtable == NULL) { 1522 error = gfe_hash_alloc(sc); 1523 if (error) 1524 break; 1525 } 1526 if (op != GE_WHACK_RESTART) 1527 gfe_hash_fill(sc); 1528 #endif 1529 #ifndef GE_NORX 1530 if (op != GE_WHACK_RESTART) { 1531 error = gfe_rx_prime(sc); 1532 if (error) 1533 break; 1534 } 1535 #endif 1536 #ifndef GE_NOTX 1537 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1538 if (error) 1539 break; 1540 #endif 1541 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1542 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1543 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1544 GE_WRITE(sc, EICR, 0); 1545 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1546 #ifndef GE_NOHASH 1547 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1548 #endif 1549 #ifndef GE_NORX 1550 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1551 sc->sc_flags |= GE_RXACTIVE; 1552 #endif 1553 /* FALLTHROUGH */ 1554 case GE_WHACK_CHANGE: 1555 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1556 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1557 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1558 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1559 gfe_ifstart(&sc->sc_ec.ec_if); 1560 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1561 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1562 GE_FUNC_EXIT(sc, ""); 1563 return error; 1564 case GE_WHACK_STOP: 1565 break; 1566 } 1567 1568 #ifdef GE_DEBUG 1569 if (error) 1570 GE_DPRINTF(sc, (" failed: %d\n", error)); 1571 #endif 1572 GE_WRITE(sc, EPCR, sc->sc_pcr); 1573 GE_WRITE(sc, EIMR, 0); 1574 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1575 #ifndef GE_NOTX 1576 gfe_tx_stop(sc, GE_WHACK_STOP); 1577 #endif 1578 #ifndef GE_NORX 1579 gfe_rx_stop(sc, GE_WHACK_STOP); 1580 #endif 1581 #ifndef GE_NOHASH 1582 if ((sc->sc_flags & GE_NOFREE) == 0) { 1583 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1584 sc->sc_hashtable = NULL; 1585 } 1586 #endif 1587 1588 GE_FUNC_EXIT(sc, ""); 1589 return error; 1590 } 1591 1592 int 1594 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1595 { 1596 uint32_t w0, add0, add1; 1597 uint32_t result; 1598 1599 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1600 add0 = ((uint32_t) eaddr[5] << 0) | 1601 ((uint32_t) eaddr[4] << 8) | 1602 ((uint32_t) eaddr[3] << 16); 1603 1604 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1605 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1606 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1607 1608 add1 = ((uint32_t) eaddr[2] << 0) | 1609 ((uint32_t) eaddr[1] << 8) | 1610 ((uint32_t) eaddr[0] << 16); 1611 1612 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1613 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1614 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1615 1616 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1617 /* 1618 * hashResult is the 15 bits Hash entry address. 1619 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1620 * MAC address, by nibble swapping in every byte (i.e MAC address 1621 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1622 */ 1623 1624 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1625 /* 1626 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1627 * 1628 * hashFunc0 calculates the hashResult in the following manner: 1629 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1630 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1631 */ 1632 result = (add0 & 3) | ((add0 >> 6) & ~3); 1633 result ^= (add0 >> 15) ^ (add1 >> 0); 1634 result &= 0x1ff; 1635 /* 1636 * hashResult[14:9] = ethernetADD[7:2] 1637 */ 1638 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1639 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1640 } else { 1641 #define TRIBITFLIP 073516240 /* yes its in octal */ 1642 /* 1643 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1644 * 1645 * hashFunc1 calculates the hashResult in the following manner: 1646 * hashResult[08:00] = ethernetADD[06:14] 1647 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1648 */ 1649 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1650 /* 1651 * Now bitswap those 9 bits 1652 */ 1653 result = 0; 1654 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1655 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1656 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1657 1658 /* 1659 * hashResult[14:09] = ethernetADD[00:05] 1660 */ 1661 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1662 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1663 GE_DPRINTF(sc, ("1(%#x)", result)); 1664 } 1665 GE_FUNC_EXIT(sc, ""); 1666 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1667 } 1668 1669 int 1670 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1671 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1672 { 1673 uint64_t he; 1674 uint64_t *maybe_he_p = NULL; 1675 int limit; 1676 int hash; 1677 int maybe_hash = 0; 1678 1679 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1680 1681 hash = gfe_hash_compute(sc, eaddr); 1682 1683 if (sc->sc_hashtable == NULL) { 1684 panic("%s:%d: hashtable == NULL!", device_xname(&sc->sc_dev), 1685 __LINE__); 1686 } 1687 1688 /* 1689 * Assume we are going to insert so create the hash entry we 1690 * are going to insert. We also use it to match entries we 1691 * will be removing. 1692 */ 1693 he = ((uint64_t) eaddr[5] << 43) | 1694 ((uint64_t) eaddr[4] << 35) | 1695 ((uint64_t) eaddr[3] << 27) | 1696 ((uint64_t) eaddr[2] << 19) | 1697 ((uint64_t) eaddr[1] << 11) | 1698 ((uint64_t) eaddr[0] << 3) | 1699 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1700 1701 /* 1702 * The GT will search upto 12 entries for a hit, so we must mimic that. 1703 */ 1704 hash &= sc->sc_hashmask / sizeof(he); 1705 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1706 /* 1707 * Does the GT wrap at the end, stop at the, or overrun the 1708 * end? Assume it wraps for now. Stash a copy of the 1709 * current hash entry. 1710 */ 1711 uint64_t *he_p = &sc->sc_hashtable[hash]; 1712 uint64_t thishe = *he_p; 1713 1714 /* 1715 * If the hash entry isn't valid, that break the chain. And 1716 * this entry a good candidate for reuse. 1717 */ 1718 if ((thishe & HSH_V) == 0) { 1719 maybe_he_p = he_p; 1720 break; 1721 } 1722 1723 /* 1724 * If the hash entry has the same address we are looking for 1725 * then ... if we are removing and the skip bit is set, its 1726 * already been removed. if are adding and the skip bit is 1727 * clear, then its already added. In either return EBUSY 1728 * indicating the op has already been done. Otherwise flip 1729 * the skip bit and return 0. 1730 */ 1731 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1732 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1733 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1734 return EBUSY; 1735 *he_p = thishe ^ HSH_S; 1736 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1737 hash * sizeof(he), sizeof(he), 1738 BUS_DMASYNC_PREWRITE); 1739 GE_FUNC_EXIT(sc, "^"); 1740 return 0; 1741 } 1742 1743 /* 1744 * If we haven't found a slot for the entry and this entry 1745 * is currently being skipped, return this entry. 1746 */ 1747 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1748 maybe_he_p = he_p; 1749 maybe_hash = hash; 1750 } 1751 1752 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1753 } 1754 1755 /* 1756 * If we got here, then there was no entry to remove. 1757 */ 1758 if (op == GE_HASH_REMOVE) { 1759 GE_FUNC_EXIT(sc, "?"); 1760 return ENOENT; 1761 } 1762 1763 /* 1764 * If we couldn't find a slot, return an error. 1765 */ 1766 if (maybe_he_p == NULL) { 1767 GE_FUNC_EXIT(sc, "!"); 1768 return ENOSPC; 1769 } 1770 1771 /* Update the entry. 1772 */ 1773 *maybe_he_p = he; 1774 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1775 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1776 GE_FUNC_EXIT(sc, "+"); 1777 return 0; 1778 } 1779 1780 int 1781 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1782 { 1783 struct gfe_softc * const sc = ec->ec_if.if_softc; 1784 int error; 1785 enum gfe_hash_op op; 1786 enum gfe_rxprio prio; 1787 1788 GE_FUNC_ENTER(sc, "hash_multichg"); 1789 /* 1790 * Is this a wildcard entry? If so and its being removed, recompute. 1791 */ 1792 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1793 if (cmd == SIOCDELMULTI) { 1794 GE_FUNC_EXIT(sc, ""); 1795 return ENETRESET; 1796 } 1797 1798 /* 1799 * Switch in 1800 */ 1801 sc->sc_flags |= GE_ALLMULTI; 1802 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1803 sc->sc_pcr |= ETH_EPCR_PM; 1804 GE_WRITE(sc, EPCR, sc->sc_pcr); 1805 GE_FUNC_EXIT(sc, ""); 1806 return 0; 1807 } 1808 GE_FUNC_EXIT(sc, ""); 1809 return ENETRESET; 1810 } 1811 1812 prio = GE_RXPRIO_MEDLO; 1813 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1814 1815 if (sc->sc_hashtable == NULL) { 1816 GE_FUNC_EXIT(sc, ""); 1817 return 0; 1818 } 1819 1820 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1821 if (error == EBUSY) { 1822 printf("%s: multichg: tried to %s %s again\n", 1823 device_xname(&sc->sc_dev), 1824 cmd == SIOCDELMULTI ? "remove" : "add", 1825 ether_sprintf(enm->enm_addrlo)); 1826 GE_FUNC_EXIT(sc, ""); 1827 return 0; 1828 } 1829 1830 if (error == ENOENT) { 1831 printf("%s: multichg: failed to remove %s: not in table\n", 1832 device_xname(&sc->sc_dev), 1833 ether_sprintf(enm->enm_addrlo)); 1834 GE_FUNC_EXIT(sc, ""); 1835 return 0; 1836 } 1837 1838 if (error == ENOSPC) { 1839 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1840 device_xname(&sc->sc_dev), 1841 ether_sprintf(enm->enm_addrlo)); 1842 GE_FUNC_EXIT(sc, ""); 1843 return ENETRESET; 1844 } 1845 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1846 device_xname(&sc->sc_dev), 1847 cmd == SIOCDELMULTI ? "remove" : "add", 1848 ether_sprintf(enm->enm_addrlo))); 1849 GE_FUNC_EXIT(sc, ""); 1850 return 0; 1851 } 1852 1853 int 1854 gfe_hash_fill(struct gfe_softc *sc) 1855 { 1856 struct ether_multistep step; 1857 struct ether_multi *enm; 1858 int error; 1859 1860 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1861 1862 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1863 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 1864 if (error) 1865 GE_FUNC_EXIT(sc, "!"); 1866 return error; 1867 1868 sc->sc_flags &= ~GE_ALLMULTI; 1869 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1870 sc->sc_pcr &= ~ETH_EPCR_PM; 1871 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1872 while (enm != NULL) { 1873 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1874 sc->sc_flags |= GE_ALLMULTI; 1875 sc->sc_pcr |= ETH_EPCR_PM; 1876 } else { 1877 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1878 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1879 if (error == ENOSPC) 1880 break; 1881 } 1882 ETHER_NEXT_MULTI(step, enm); 1883 } 1884 1885 GE_FUNC_EXIT(sc, ""); 1886 return error; 1887 } 1888 1889 int 1890 gfe_hash_alloc(struct gfe_softc *sc) 1891 { 1892 int error; 1893 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1894 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1895 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1896 BUS_DMA_NOCACHE); 1897 if (error) { 1898 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1899 device_xname(&sc->sc_dev), sc->sc_hashmask + 1, error); 1900 GE_FUNC_EXIT(sc, ""); 1901 return error; 1902 } 1903 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1904 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1905 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1906 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1907 GE_FUNC_EXIT(sc, ""); 1908 return 0; 1909 } 1910
Indexes created Tue Sep 30 07:10:03 GMT 2025