if_gfe.c revision 1.35
1 /* $NetBSD: if_gfe.c,v 1.35 2010/04/05 07:20:24 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.35 2010/04/05 07:20:24 joerg Exp $"); 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/types.h> 51 #include <sys/inttypes.h> 52 #include <sys/queue.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <sys/callout.h> 57 #include <sys/device.h> 58 #include <sys/errno.h> 59 #include <sys/ioctl.h> 60 #include <sys/mbuf.h> 61 #include <sys/socket.h> 62 63 #include <sys/bus.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_ether.h> 68 #include <net/if_media.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/if_inarp.h> 73 #endif 74 #include <net/bpf.h> 75 76 #include <dev/mii/miivar.h> 77 78 #include <dev/marvell/gtintrreg.h> 79 #include <dev/marvell/gtethreg.h> 80 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/if_gfevar.h> 83 84 #define GE_READ(sc, reg) \ 85 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 86 #define GE_WRITE(sc, reg, v) \ 87 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 88 89 #define GE_DEBUG 90 #if 0 91 #define GE_NOHASH 92 #define GE_NORX 93 #endif 94 95 #ifdef GE_DEBUG 96 #define GE_DPRINTF(sc, a) do \ 97 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 98 printf a; \ 99 while (0) 100 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 101 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 102 #else 103 #define GE_DPRINTF(sc, a) do { } while (0) 104 #define GE_FUNC_ENTER(sc, func) do { } while (0) 105 #define GE_FUNC_EXIT(sc, str) do { } while (0) 106 #endif 107 enum gfe_whack_op { 108 GE_WHACK_START, GE_WHACK_RESTART, 109 GE_WHACK_CHANGE, GE_WHACK_STOP 110 }; 111 112 enum gfe_hash_op { 113 GE_HASH_ADD, GE_HASH_REMOVE, 114 }; 115 116 #if 1 117 #define htogt32(a) htobe32(a) 118 #define gt32toh(a) be32toh(a) 119 #else 120 #define htogt32(a) htole32(a) 121 #define gt32toh(a) le32toh(a) 122 #endif 123 124 #define GE_RXDSYNC(sc, rxq, n, ops) \ 125 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 126 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 127 (ops)) 128 #define GE_RXDPRESYNC(sc, rxq, n) \ 129 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 130 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 131 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 132 133 #define GE_TXDSYNC(sc, txq, n, ops) \ 134 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 135 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 136 (ops)) 137 #define GE_TXDPRESYNC(sc, txq, n) \ 138 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 139 #define GE_TXDPOSTSYNC(sc, txq, n) \ 140 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 141 142 #define STATIC 143 144 STATIC int gfe_match (device_t, cfdata_t, void *); 145 STATIC void gfe_attach (device_t, device_t, void *); 146 147 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 148 size_t, int); 149 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 150 151 STATIC int gfe_ifioctl (struct ifnet *, u_long, void *); 152 STATIC void gfe_ifstart (struct ifnet *); 153 STATIC void gfe_ifwatchdog (struct ifnet *); 154 155 STATIC int gfe_mii_read (device_t, int, int); 156 STATIC void gfe_mii_write (device_t, int, int, int); 157 STATIC void gfe_mii_statchg (device_t); 158 159 STATIC void gfe_tick(void *arg); 160 161 STATIC void gfe_tx_restart(void *); 162 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 163 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 164 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 165 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio); 166 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 167 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 168 169 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 170 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 171 STATIC int gfe_rx_prime(struct gfe_softc *); 172 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 173 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 174 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio); 175 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 176 177 STATIC int gfe_intr(void *); 178 179 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 180 181 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 182 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 183 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 184 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 185 u_long); 186 STATIC int gfe_hash_fill(struct gfe_softc *); 187 STATIC int gfe_hash_alloc(struct gfe_softc *); 188 189 /* Linkup to the rest of the kernel */ 190 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 191 gfe_match, gfe_attach, NULL, NULL); 192 193 extern struct cfdriver gfe_cd; 194 195 int 196 gfe_match(device_t parent, cfdata_t cf, void *aux) 197 { 198 struct gt_softc *gt = (struct gt_softc *) parent; 199 struct gt_attach_args *ga = aux; 200 uint8_t enaddr[6]; 201 202 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 203 return 0; 204 205 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 206 return 0; 207 208 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 209 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 210 return 0; 211 212 return 1; 213 } 214 215 /* 216 * Attach this instance, and then all the sub-devices 217 */ 218 void 219 gfe_attach(device_t parent, device_t self, void *aux) 220 { 221 struct gt_attach_args * const ga = aux; 222 struct gt_softc * const gt = device_private(parent); 223 struct gfe_softc * const sc = device_private(self); 224 struct ifnet * const ifp = &sc->sc_ec.ec_if; 225 uint32_t data; 226 uint8_t enaddr[6]; 227 int phyaddr; 228 uint32_t sdcr; 229 int error; 230 231 GT_ETHERFOUND(gt, ga); 232 233 sc->sc_gt_memt = ga->ga_memt; 234 sc->sc_gt_memh = ga->ga_memh; 235 sc->sc_dmat = ga->ga_dmat; 236 sc->sc_macno = ga->ga_unit; 237 238 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 239 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 240 aprint_error(": failed to map registers\n"); 241 } 242 243 callout_init(&sc->sc_co, 0); 244 245 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 246 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 247 248 gtget_macaddr(gt, sc->sc_macno, enaddr); 249 250 sc->sc_pcr = GE_READ(sc, EPCR); 251 sc->sc_pcxr = GE_READ(sc, EPCXR); 252 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 253 254 aprint_normal(": address %s", ether_sprintf(enaddr)); 255 256 #if defined(DEBUG) 257 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 258 #endif 259 260 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 261 if (device_cfdata(&sc->sc_dev)->cf_flags & 1) { 262 aprint_normal(", phy %d (rmii)", phyaddr); 263 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 264 } else { 265 aprint_normal(", phy %d (mii)", phyaddr); 266 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 267 } 268 if (device_cfdata(&sc->sc_dev)->cf_flags & 2) 269 sc->sc_flags |= GE_NOFREE; 270 sc->sc_pcxr &= ~(3 << 14); 271 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 272 273 if (sc->sc_pcr & ETH_EPCR_EN) { 274 int tries = 1000; 275 /* 276 * Abort transmitter and receiver and wait for them to quiese 277 */ 278 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 279 do { 280 delay(100); 281 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 282 } 283 284 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 285 286 #if defined(DEBUG) 287 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 288 #endif 289 290 /* 291 * Now turn off the GT. If it didn't quiese, too ***ing bad. 292 */ 293 GE_WRITE(sc, EPCR, sc->sc_pcr); 294 GE_WRITE(sc, EIMR, sc->sc_intrmask); 295 sdcr = GE_READ(sc, ESDCR); 296 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 297 sdcr |= ETH_ESDCR_RIFB; 298 GE_WRITE(sc, ESDCR, sdcr); 299 sc->sc_max_frame_length = 1536; 300 301 aprint_normal("\n"); 302 sc->sc_mii.mii_ifp = ifp; 303 sc->sc_mii.mii_readreg = gfe_mii_read; 304 sc->sc_mii.mii_writereg = gfe_mii_write; 305 sc->sc_mii.mii_statchg = gfe_mii_statchg; 306 307 sc->sc_ec.ec_mii = &sc->sc_mii; 308 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 309 ether_mediastatus); 310 311 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 312 MII_OFFSET_ANY, MIIF_NOISOLATE); 313 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 314 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 315 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 316 } else { 317 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 318 } 319 320 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 321 ifp->if_softc = sc; 322 /* ifp->if_mowner = &sc->sc_mowner; */ 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 #if 0 325 ifp->if_flags |= IFF_DEBUG; 326 #endif 327 ifp->if_ioctl = gfe_ifioctl; 328 ifp->if_start = gfe_ifstart; 329 ifp->if_watchdog = gfe_ifwatchdog; 330 331 if (sc->sc_flags & GE_NOFREE) { 332 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 333 if (!error) 334 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 335 if (!error) 336 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 337 if (!error) 338 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 339 if (!error) 340 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI); 341 if (!error) 342 error = gfe_hash_alloc(sc); 343 if (error) 344 aprint_error( 345 "%s: failed to allocate resources: %d\n", 346 ifp->if_xname, error); 347 } 348 349 if_attach(ifp); 350 ether_ifattach(ifp, enaddr); 351 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 352 #if NRND > 0 353 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET, 0); 354 #endif 355 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 356 gfe_intr, sc); 357 } 358 359 int 360 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 361 size_t size, int flags) 362 { 363 int error = 0; 364 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 365 366 KASSERT(gdm->gdm_kva == NULL); 367 gdm->gdm_size = size; 368 gdm->gdm_maxsegs = maxsegs; 369 370 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 371 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 372 BUS_DMA_NOWAIT); 373 if (error) 374 goto fail; 375 376 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 377 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 378 if (error) 379 goto fail; 380 381 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 382 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 383 if (error) 384 goto fail; 385 386 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 387 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 388 if (error) 389 goto fail; 390 391 /* invalidate from cache */ 392 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 393 BUS_DMASYNC_PREREAD); 394 fail: 395 if (error) { 396 gfe_dmamem_free(sc, gdm); 397 GE_DPRINTF(sc, (":err=%d", error)); 398 } 399 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 400 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 401 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 402 GE_FUNC_EXIT(sc, ""); 403 return error; 404 } 405 406 void 407 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 408 { 409 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 410 if (gdm->gdm_map) 411 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 412 if (gdm->gdm_kva) 413 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 414 if (gdm->gdm_nsegs > 0) 415 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 416 gdm->gdm_map = NULL; 417 gdm->gdm_kva = NULL; 418 gdm->gdm_nsegs = 0; 419 GE_FUNC_EXIT(sc, ""); 420 } 421 422 int 423 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 424 { 425 struct gfe_softc * const sc = ifp->if_softc; 426 struct ifreq *ifr = (struct ifreq *) data; 427 struct ifaddr *ifa = (struct ifaddr *) data; 428 int s, error = 0; 429 430 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 431 s = splnet(); 432 433 switch (cmd) { 434 case SIOCINITIFADDR: 435 ifp->if_flags |= IFF_UP; 436 error = gfe_whack(sc, GE_WHACK_START); 437 switch (ifa->ifa_addr->sa_family) { 438 #ifdef INET 439 case AF_INET: 440 if (error == 0) 441 arp_ifinit(ifp, ifa); 442 break; 443 #endif 444 default: 445 break; 446 } 447 break; 448 449 case SIOCSIFFLAGS: 450 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 451 break; 452 /* XXX re-use ether_ioctl() */ 453 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 454 case IFF_UP|IFF_RUNNING:/* active->active, update */ 455 error = gfe_whack(sc, GE_WHACK_CHANGE); 456 break; 457 case IFF_RUNNING: /* not up, so we stop */ 458 error = gfe_whack(sc, GE_WHACK_STOP); 459 break; 460 case IFF_UP: /* not running, so we start */ 461 error = gfe_whack(sc, GE_WHACK_START); 462 break; 463 case 0: /* idle->idle: do nothing */ 464 break; 465 } 466 break; 467 468 case SIOCSIFMEDIA: 469 case SIOCGIFMEDIA: 470 case SIOCADDMULTI: 471 case SIOCDELMULTI: 472 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 473 if (ifp->if_flags & IFF_RUNNING) 474 error = gfe_whack(sc, GE_WHACK_CHANGE); 475 else 476 error = 0; 477 } 478 break; 479 480 case SIOCSIFMTU: 481 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 482 error = EINVAL; 483 break; 484 } 485 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET) 486 error = 0; 487 break; 488 489 default: 490 error = ether_ioctl(ifp, cmd, data); 491 break; 492 } 493 splx(s); 494 GE_FUNC_EXIT(sc, ""); 495 return error; 496 } 497 498 void 499 gfe_ifstart(struct ifnet *ifp) 500 { 501 struct gfe_softc * const sc = ifp->if_softc; 502 struct mbuf *m; 503 504 GE_FUNC_ENTER(sc, "gfe_ifstart"); 505 506 if ((ifp->if_flags & IFF_RUNNING) == 0) { 507 GE_FUNC_EXIT(sc, "$"); 508 return; 509 } 510 511 for (;;) { 512 IF_DEQUEUE(&ifp->if_snd, m); 513 if (m == NULL) { 514 ifp->if_flags &= ~IFF_OACTIVE; 515 GE_FUNC_EXIT(sc, ""); 516 return; 517 } 518 519 /* 520 * No space in the pending queue? try later. 521 */ 522 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq)) 523 break; 524 525 /* 526 * Try to enqueue a mbuf to the device. If that fails, we 527 * can always try to map the next mbuf. 528 */ 529 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m); 530 GE_DPRINTF(sc, (">")); 531 #ifndef GE_NOTX 532 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 533 #endif 534 } 535 536 /* 537 * Attempt to queue the mbuf for send failed. 538 */ 539 IF_PREPEND(&ifp->if_snd, m); 540 ifp->if_flags |= IFF_OACTIVE; 541 GE_FUNC_EXIT(sc, "%%"); 542 } 543 544 void 545 gfe_ifwatchdog(struct ifnet *ifp) 546 { 547 struct gfe_softc * const sc = ifp->if_softc; 548 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI]; 549 550 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 551 printf("%s: device timeout", device_xname(&sc->sc_dev)); 552 if (ifp->if_flags & IFF_RUNNING) { 553 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 554 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 555 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 556 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 557 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 558 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 559 GE_READ(sc, EICR)); 560 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 561 GE_TXDPRESYNC(sc, txq, curtxdnum); 562 } 563 printf("\n"); 564 ifp->if_oerrors++; 565 (void) gfe_whack(sc, GE_WHACK_RESTART); 566 GE_FUNC_EXIT(sc, ""); 567 } 568 569 int 571 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 572 { 573 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 574 int error; 575 576 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 577 GE_DPRINTF(sc, ("(%d)", rxprio)); 578 579 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 580 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 581 if (error) { 582 GE_FUNC_EXIT(sc, "!!"); 583 return error; 584 } 585 586 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 587 GE_RXBUF_MEMSIZE, 0); 588 if (error) { 589 GE_FUNC_EXIT(sc, "!!!"); 590 return error; 591 } 592 GE_FUNC_EXIT(sc, ""); 593 return error; 594 } 595 596 int 597 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio) 598 { 599 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 600 volatile struct gt_eth_desc *rxd; 601 const bus_dma_segment_t *ds; 602 int idx; 603 bus_addr_t nxtaddr; 604 bus_size_t boff; 605 606 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit"); 607 GE_DPRINTF(sc, ("(%d)", rxprio)); 608 609 if ((sc->sc_flags & GE_NOFREE) == 0) { 610 int error = gfe_rx_rxqalloc(sc, rxprio); 611 if (error) { 612 GE_FUNC_EXIT(sc, "!"); 613 return error; 614 } 615 } else { 616 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL); 617 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL); 618 } 619 620 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE); 621 622 rxq->rxq_descs = 623 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 624 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 625 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 626 rxq->rxq_fi = 0; 627 rxq->rxq_active = GE_RXDESC_MAX; 628 for (idx = 0, rxd = rxq->rxq_descs, 629 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 630 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 631 idx < GE_RXDESC_MAX; 632 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 633 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 634 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 635 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 636 /* 637 * update the nxtptr to point to the next txd. 638 */ 639 if (idx == GE_RXDESC_MAX - 1) 640 nxtaddr = rxq->rxq_desc_busaddr; 641 rxd->ed_nxtptr = htogt32(nxtaddr); 642 boff += GE_RXBUF_SIZE; 643 if (boff == ds->ds_len) { 644 ds++; 645 boff = 0; 646 } 647 } 648 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 649 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 650 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 651 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 652 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 653 BUS_DMASYNC_PREREAD); 654 655 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 656 switch (rxprio) { 657 case GE_RXPRIO_HI: 658 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 659 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 660 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 661 break; 662 case GE_RXPRIO_MEDHI: 663 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 664 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 665 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 666 break; 667 case GE_RXPRIO_MEDLO: 668 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 669 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 670 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 671 break; 672 case GE_RXPRIO_LO: 673 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 674 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 675 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 676 break; 677 } 678 GE_FUNC_EXIT(sc, ""); 679 return 0; 680 } 681 682 void 683 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 684 { 685 struct ifnet * const ifp = &sc->sc_ec.ec_if; 686 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio]; 687 struct mbuf *m = rxq->rxq_curpkt; 688 689 GE_FUNC_ENTER(sc, "gfe_rx_get"); 690 GE_DPRINTF(sc, ("(%d)", rxprio)); 691 692 while (rxq->rxq_active > 0) { 693 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 694 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 695 const struct ether_header *eh; 696 unsigned int cmdsts; 697 size_t buflen; 698 699 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 700 cmdsts = gt32toh(rxd->ed_cmdsts); 701 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 702 rxq->rxq_cmdsts = cmdsts; 703 /* 704 * Sometimes the GE "forgets" to reset the ownership bit. 705 * But if the length has been rewritten, the packet is ours 706 * so pretend the O bit is set. 707 */ 708 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 709 if ((cmdsts & RX_CMD_O) && buflen == 0) { 710 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 711 break; 712 } 713 714 /* 715 * If this is not a single buffer packet with no errors 716 * or for some reason it's bigger than our frame size, 717 * ignore it and go to the next packet. 718 */ 719 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 720 (RX_CMD_F|RX_CMD_L) || 721 buflen > sc->sc_max_frame_length) { 722 GE_DPRINTF(sc, ("!")); 723 --rxq->rxq_active; 724 ifp->if_ipackets++; 725 ifp->if_ierrors++; 726 goto give_it_back; 727 } 728 729 /* CRC is included with the packet; trim it off. */ 730 buflen -= ETHER_CRC_LEN; 731 732 if (m == NULL) { 733 MGETHDR(m, M_DONTWAIT, MT_DATA); 734 if (m == NULL) { 735 GE_DPRINTF(sc, ("?")); 736 break; 737 } 738 } 739 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 740 MCLGET(m, M_DONTWAIT); 741 if ((m->m_flags & M_EXT) == 0) { 742 GE_DPRINTF(sc, ("?")); 743 break; 744 } 745 } 746 m->m_data += 2; 747 m->m_len = 0; 748 m->m_pkthdr.len = 0; 749 m->m_pkthdr.rcvif = ifp; 750 rxq->rxq_cmdsts = cmdsts; 751 --rxq->rxq_active; 752 753 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 754 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 755 756 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 757 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen); 758 m->m_len = buflen; 759 m->m_pkthdr.len = buflen; 760 761 ifp->if_ipackets++; 762 bpf_mtap(ifp, m); 763 764 eh = (const struct ether_header *) m->m_data; 765 if ((ifp->if_flags & IFF_PROMISC) || 766 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 767 (rxq->rxq_cmdsts & RX_STS_HE) || 768 (eh->ether_dhost[0] & 1) != 0 || 769 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl), 770 ETHER_ADDR_LEN) == 0) { 771 (*ifp->if_input)(ifp, m); 772 m = NULL; 773 GE_DPRINTF(sc, (">")); 774 } else { 775 m->m_len = 0; 776 m->m_pkthdr.len = 0; 777 GE_DPRINTF(sc, ("+")); 778 } 779 rxq->rxq_cmdsts = 0; 780 781 give_it_back: 782 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 783 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 784 #if 0 785 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 786 rxq->rxq_fi, 787 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 788 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 789 #endif 790 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 791 if (++rxq->rxq_fi == GE_RXDESC_MAX) 792 rxq->rxq_fi = 0; 793 rxq->rxq_active++; 794 } 795 rxq->rxq_curpkt = m; 796 GE_FUNC_EXIT(sc, ""); 797 } 798 799 uint32_t 800 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 801 { 802 struct ifnet * const ifp = &sc->sc_ec.ec_if; 803 struct gfe_rxqueue *rxq; 804 uint32_t rxbits; 805 #define RXPRIO_DECODER 0xffffaa50 806 GE_FUNC_ENTER(sc, "gfe_rx_process"); 807 808 rxbits = ETH_IR_RxBuffer_GET(cause); 809 while (rxbits) { 810 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 811 GE_DPRINTF(sc, ("%1x", rxbits)); 812 rxbits &= ~(1 << rxprio); 813 gfe_rx_get(sc, rxprio); 814 } 815 816 rxbits = ETH_IR_RxError_GET(cause); 817 while (rxbits) { 818 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 819 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 820 int idx; 821 rxbits &= ~(1 << rxprio); 822 rxq = &sc->sc_rxq[rxprio]; 823 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 824 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 825 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 826 sc->sc_tickflags |= GE_TICK_RX_RESTART; 827 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 828 } 829 ifp->if_ierrors++; 830 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 831 device_xname(&sc->sc_dev), rxprio, rxq->rxq_fi)); 832 memset(masks, 0, sizeof(masks)); 833 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 834 0, rxq->rxq_desc_mem.gdm_size, 835 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 836 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 837 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 838 839 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 840 masks[idx/32] |= 1 << (idx & 31); 841 } 842 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 843 0, rxq->rxq_desc_mem.gdm_size, 844 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 845 #if defined(DEBUG) 846 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 847 device_xname(&sc->sc_dev), rxprio, rxq->rxq_fi, 848 rxq->rxq_cmdsts, masks[0], masks[1]); 849 #endif 850 } 851 if ((intrmask & ETH_IR_RxBits) == 0) 852 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 853 854 GE_FUNC_EXIT(sc, ""); 855 return intrmask; 856 } 857 858 int 859 gfe_rx_prime(struct gfe_softc *sc) 860 { 861 struct gfe_rxqueue *rxq; 862 int error; 863 864 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 865 866 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI); 867 if (error) 868 goto bail; 869 rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 870 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 871 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 872 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 873 } 874 sc->sc_intrmask |= rxq->rxq_intrbits; 875 876 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI); 877 if (error) 878 goto bail; 879 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 880 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 881 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 882 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 883 sc->sc_intrmask |= rxq->rxq_intrbits; 884 } 885 886 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO); 887 if (error) 888 goto bail; 889 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 890 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 891 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 892 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 893 sc->sc_intrmask |= rxq->rxq_intrbits; 894 } 895 896 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO); 897 if (error) 898 goto bail; 899 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 900 rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 901 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 902 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 903 sc->sc_intrmask |= rxq->rxq_intrbits; 904 } 905 906 bail: 907 GE_FUNC_EXIT(sc, ""); 908 return error; 909 } 910 911 void 912 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 913 { 914 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio]; 915 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 916 if (rxq == NULL) { 917 GE_FUNC_EXIT(sc, ""); 918 return; 919 } 920 921 if (rxq->rxq_curpkt) 922 m_freem(rxq->rxq_curpkt); 923 if ((sc->sc_flags & GE_NOFREE) == 0) { 924 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 925 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 926 } 927 GE_FUNC_EXIT(sc, ""); 928 } 929 930 void 931 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 932 { 933 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 934 sc->sc_flags &= ~GE_RXACTIVE; 935 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 936 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 937 GE_WRITE(sc, EIMR, sc->sc_intrmask); 938 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 939 do { 940 delay(10); 941 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 942 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 943 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 944 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 945 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 946 GE_FUNC_EXIT(sc, ""); 947 } 948 949 void 951 gfe_tick(void *arg) 952 { 953 struct gfe_softc * const sc = arg; 954 uint32_t intrmask; 955 unsigned int tickflags; 956 int s; 957 958 GE_FUNC_ENTER(sc, "gfe_tick"); 959 960 s = splnet(); 961 962 tickflags = sc->sc_tickflags; 963 sc->sc_tickflags = 0; 964 intrmask = sc->sc_intrmask; 965 if (tickflags & GE_TICK_TX_IFSTART) 966 gfe_ifstart(&sc->sc_ec.ec_if); 967 if (tickflags & GE_TICK_RX_RESTART) { 968 intrmask |= sc->sc_idlemask; 969 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 970 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI]; 971 rxq->rxq_fi = 0; 972 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 973 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 974 } 975 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 976 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI]; 977 rxq->rxq_fi = 0; 978 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 979 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 980 } 981 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 982 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO]; 983 rxq->rxq_fi = 0; 984 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 985 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 986 } 987 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 988 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO]; 989 rxq->rxq_fi = 0; 990 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 991 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 992 } 993 sc->sc_idlemask = 0; 994 } 995 if (intrmask != sc->sc_intrmask) { 996 sc->sc_intrmask = intrmask; 997 GE_WRITE(sc, EIMR, sc->sc_intrmask); 998 } 999 gfe_intr(sc); 1000 splx(s); 1001 1002 GE_FUNC_EXIT(sc, ""); 1003 } 1004 1005 int 1006 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 1007 { 1008 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1009 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1010 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1011 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1012 uint32_t intrmask = sc->sc_intrmask; 1013 size_t buflen; 1014 struct mbuf *m; 1015 1016 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1017 1018 /* 1019 * Anything in the pending queue to enqueue? if not, punt. Likewise 1020 * if the txq is not yet created. 1021 * otherwise grab its dmamap. 1022 */ 1023 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) { 1024 GE_FUNC_EXIT(sc, "-"); 1025 return 0; 1026 } 1027 1028 /* 1029 * Have we [over]consumed our limit of descriptors? 1030 * Do we have enough free descriptors? 1031 */ 1032 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1033 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1034 uint32_t cmdsts; 1035 size_t pktlen; 1036 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1037 cmdsts = gt32toh(txd2->ed_cmdsts); 1038 if (cmdsts & TX_CMD_O) { 1039 int nextin; 1040 /* 1041 * Sometime the Discovery forgets to update the 1042 * last descriptor. See if we own the descriptor 1043 * after it (since we know we've turned that to 1044 * the discovery and if we owned it, the Discovery 1045 * gave it back). If we do, we know the Discovery 1046 * gave back this one but forgot to mark it as ours. 1047 */ 1048 nextin = txq->txq_fi + 1; 1049 if (nextin == GE_TXDESC_MAX) 1050 nextin = 0; 1051 GE_TXDPOSTSYNC(sc, txq, nextin); 1052 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1053 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1054 GE_TXDPRESYNC(sc, txq, nextin); 1055 GE_FUNC_EXIT(sc, "@"); 1056 return 0; 1057 } 1058 #ifdef DEBUG 1059 printf("%s: txenqueue: transmitter resynced at %d\n", 1060 device_xname(&sc->sc_dev), txq->txq_fi); 1061 #endif 1062 } 1063 if (++txq->txq_fi == GE_TXDESC_MAX) 1064 txq->txq_fi = 0; 1065 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1066 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1067 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1068 txq->txq_nactive--; 1069 1070 /* statistics */ 1071 ifp->if_opackets++; 1072 if (cmdsts & TX_STS_ES) 1073 ifp->if_oerrors++; 1074 GE_DPRINTF(sc, ("%%")); 1075 } 1076 1077 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1078 1079 /* 1080 * If this packet would wrap around the end of the buffer, reset back 1081 * to the beginning. 1082 */ 1083 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1084 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1085 txq->txq_outptr = 0; 1086 } 1087 1088 /* 1089 * Make sure the output packet doesn't run over the beginning of 1090 * what we've already given the GT. 1091 */ 1092 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1093 txq->txq_outptr + buflen > txq->txq_inptr) { 1094 intrmask |= txq->txq_intrbits & 1095 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1096 if (sc->sc_intrmask != intrmask) { 1097 sc->sc_intrmask = intrmask; 1098 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1099 } 1100 GE_FUNC_EXIT(sc, "#"); 1101 return 0; 1102 } 1103 1104 /* 1105 * The end-of-list descriptor we put on last time is the starting point 1106 * for this packet. The GT is supposed to terminate list processing on 1107 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1108 * must terminate the list. 1109 */ 1110 intrmask = sc->sc_intrmask; 1111 1112 m_copydata(m, 0, m->m_pkthdr.len, 1113 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr); 1114 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1115 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1116 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1117 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1118 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1119 1120 /* 1121 * Request a buffer interrupt every 2/3 of the way thru the transmit 1122 * buffer. 1123 */ 1124 txq->txq_ei_gapcount += buflen; 1125 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1126 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1127 txq->txq_ei_gapcount = 0; 1128 } else { 1129 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1130 } 1131 #if 0 1132 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1133 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1134 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1135 #endif 1136 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1137 1138 txq->txq_outptr += buflen; 1139 /* 1140 * Tell the SDMA engine to "Fetch!" 1141 */ 1142 GE_WRITE(sc, ESDCMR, 1143 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1144 1145 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1146 1147 /* 1148 * Update the last out appropriately. 1149 */ 1150 txq->txq_nactive++; 1151 if (++txq->txq_lo == GE_TXDESC_MAX) 1152 txq->txq_lo = 0; 1153 1154 /* 1155 * Move mbuf from the pending queue to the snd queue. 1156 */ 1157 IF_DEQUEUE(&txq->txq_pendq, m); 1158 bpf_mtap(ifp, m); 1159 m_freem(m); 1160 ifp->if_flags &= ~IFF_OACTIVE; 1161 1162 /* 1163 * Since we have put an item into the packet queue, we now want 1164 * an interrupt when the transmit queue finishes processing the 1165 * list. But only update the mask if needs changing. 1166 */ 1167 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1168 if (sc->sc_intrmask != intrmask) { 1169 sc->sc_intrmask = intrmask; 1170 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1171 } 1172 if (ifp->if_timer == 0) 1173 ifp->if_timer = 5; 1174 GE_FUNC_EXIT(sc, "*"); 1175 return 1; 1176 } 1177 1178 uint32_t 1179 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1180 { 1181 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1182 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1183 1184 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1185 1186 if (txq == NULL) { 1187 GE_FUNC_EXIT(sc, ""); 1188 return intrmask; 1189 } 1190 1191 while (txq->txq_nactive > 0) { 1192 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1193 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1194 uint32_t cmdsts; 1195 size_t pktlen; 1196 1197 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1198 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1199 int nextin; 1200 1201 if (txq->txq_nactive == 1) { 1202 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1203 GE_FUNC_EXIT(sc, ""); 1204 return intrmask; 1205 } 1206 /* 1207 * Sometimes the Discovery forgets to update the 1208 * ownership bit in the descriptor. See if we own the 1209 * descriptor after it (since we know we've turned 1210 * that to the Discovery and if we own it now then the 1211 * Discovery gave it back). If we do, we know the 1212 * Discovery gave back this one but forgot to mark it 1213 * as ours. 1214 */ 1215 nextin = txq->txq_fi + 1; 1216 if (nextin == GE_TXDESC_MAX) 1217 nextin = 0; 1218 GE_TXDPOSTSYNC(sc, txq, nextin); 1219 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1220 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1221 GE_TXDPRESYNC(sc, txq, nextin); 1222 GE_FUNC_EXIT(sc, ""); 1223 return intrmask; 1224 } 1225 #ifdef DEBUG 1226 printf("%s: txdone: transmitter resynced at %d\n", 1227 device_xname(&sc->sc_dev), txq->txq_fi); 1228 #endif 1229 } 1230 #if 0 1231 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1232 txq->txq_lo, 1233 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1234 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1235 #endif 1236 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1237 if (++txq->txq_fi == GE_TXDESC_MAX) 1238 txq->txq_fi = 0; 1239 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1240 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1241 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1242 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1243 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1244 1245 /* statistics */ 1246 ifp->if_opackets++; 1247 if (cmdsts & TX_STS_ES) 1248 ifp->if_oerrors++; 1249 1250 /* txd->ed_bufptr = 0; */ 1251 1252 ifp->if_timer = 5; 1253 --txq->txq_nactive; 1254 } 1255 if (txq->txq_nactive != 0) 1256 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1257 device_xname(&sc->sc_dev), txprio, txq->txq_nactive); 1258 ifp->if_timer = 0; 1259 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1260 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1261 GE_FUNC_EXIT(sc, ""); 1262 return intrmask; 1263 } 1264 1265 int 1266 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio) 1267 { 1268 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1269 int error; 1270 1271 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc"); 1272 1273 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1274 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE); 1275 if (error) { 1276 GE_FUNC_EXIT(sc, ""); 1277 return error; 1278 } 1279 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0); 1280 if (error) { 1281 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1282 GE_FUNC_EXIT(sc, ""); 1283 return error; 1284 } 1285 GE_FUNC_EXIT(sc, ""); 1286 return 0; 1287 } 1288 1289 int 1290 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1291 { 1292 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1293 volatile struct gt_eth_desc *txd; 1294 unsigned int i; 1295 bus_addr_t addr; 1296 1297 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1298 1299 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1300 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1301 1302 if (sc->sc_flags & GE_NOFREE) { 1303 KASSERT(txq->txq_desc_mem.gdm_kva != NULL); 1304 KASSERT(txq->txq_buf_mem.gdm_kva != NULL); 1305 } else { 1306 int error = gfe_tx_txqalloc(sc, txprio); 1307 if (error) { 1308 GE_FUNC_EXIT(sc, "!"); 1309 return error; 1310 } 1311 } 1312 1313 txq->txq_descs = 1314 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1315 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1316 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1317 1318 txq->txq_pendq.ifq_maxlen = 10; 1319 txq->txq_ei_gapcount = 0; 1320 txq->txq_nactive = 0; 1321 txq->txq_fi = 0; 1322 txq->txq_lo = 0; 1323 txq->txq_inptr = GE_TXBUF_SIZE; 1324 txq->txq_outptr = 0; 1325 for (i = 0, txd = txq->txq_descs, 1326 addr = txq->txq_desc_busaddr + sizeof(*txd); 1327 i < GE_TXDESC_MAX - 1; 1328 i++, txd++, addr += sizeof(*txd)) { 1329 /* 1330 * update the nxtptr to point to the next txd. 1331 */ 1332 txd->ed_cmdsts = 0; 1333 txd->ed_nxtptr = htogt32(addr); 1334 } 1335 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1336 htogt32(txq->txq_desc_busaddr); 1337 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1338 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1339 1340 switch (txprio) { 1341 case GE_TXPRIO_HI: 1342 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1343 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1344 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1345 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1346 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1347 break; 1348 1349 case GE_TXPRIO_LO: 1350 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1351 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1352 txq->txq_epsrbits = ETH_EPSR_TxLow; 1353 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1354 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1355 break; 1356 1357 case GE_TXPRIO_NONE: 1358 break; 1359 } 1360 #if 0 1361 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1362 gt_write(device_parent(&sc->sc_dev), txq->txq_ectdp, 1363 txq->txq_desc_busaddr); 1364 GE_DPRINTF(sc, (")")); 1365 #endif 1366 1367 /* 1368 * If we are restarting, there may be packets in the pending queue 1369 * waiting to be enqueued. Try enqueuing packets from both priority 1370 * queues until the pending queue is empty or there no room for them 1371 * on the device. 1372 */ 1373 while (gfe_tx_enqueue(sc, txprio)) 1374 continue; 1375 1376 GE_FUNC_EXIT(sc, ""); 1377 return 0; 1378 } 1379 1380 void 1381 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1382 { 1383 struct gfe_txqueue * const txq = &sc->sc_txq[txprio]; 1384 1385 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1386 if (txq == NULL) { 1387 GE_FUNC_EXIT(sc, ""); 1388 return; 1389 } 1390 1391 if (!flush) { 1392 GE_FUNC_EXIT(sc, ""); 1393 return; 1394 } 1395 1396 if ((sc->sc_flags & GE_NOFREE) == 0) { 1397 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1398 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1399 } 1400 GE_FUNC_EXIT(sc, "-F"); 1401 } 1402 1403 void 1404 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1405 { 1406 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1407 1408 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1409 1410 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1411 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1412 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1413 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1414 1415 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1416 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1417 1418 sc->sc_ec.ec_if.if_timer = 0; 1419 GE_FUNC_EXIT(sc, ""); 1420 } 1421 1422 int 1424 gfe_intr(void *arg) 1425 { 1426 struct gfe_softc * const sc = arg; 1427 uint32_t cause; 1428 uint32_t intrmask = sc->sc_intrmask; 1429 int claim = 0; 1430 int cnt; 1431 1432 GE_FUNC_ENTER(sc, "gfe_intr"); 1433 1434 for (cnt = 0; cnt < 4; cnt++) { 1435 if (sc->sc_intrmask != intrmask) { 1436 sc->sc_intrmask = intrmask; 1437 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1438 } 1439 cause = GE_READ(sc, EICR); 1440 cause &= sc->sc_intrmask; 1441 GE_DPRINTF(sc, (".%#x", cause)); 1442 if (cause == 0) 1443 break; 1444 1445 claim = 1; 1446 1447 GE_WRITE(sc, EICR, ~cause); 1448 #ifndef GE_NORX 1449 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1450 intrmask = gfe_rx_process(sc, cause, intrmask); 1451 #endif 1452 1453 #ifndef GE_NOTX 1454 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1455 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1456 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1457 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1458 #endif 1459 if (cause & ETH_IR_MIIPhySTC) { 1460 sc->sc_flags |= GE_PHYSTSCHG; 1461 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1462 } 1463 } 1464 1465 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI)) 1466 continue; 1467 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO)) 1468 continue; 1469 1470 GE_FUNC_EXIT(sc, ""); 1471 return claim; 1472 } 1473 1474 int 1476 gfe_mii_read (device_t self, int phy, int reg) 1477 { 1478 return gt_mii_read(self, device_parent(self), phy, reg); 1479 } 1480 1481 void 1482 gfe_mii_write (device_t self, int phy, int reg, int value) 1483 { 1484 gt_mii_write(self, device_parent(self), phy, reg, value); 1485 } 1486 1487 void 1488 gfe_mii_statchg (device_t self) 1489 { 1490 /* struct gfe_softc *sc = device_private(self); */ 1491 /* do nothing? */ 1492 } 1493 1494 int 1496 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1497 { 1498 int error = 0; 1499 GE_FUNC_ENTER(sc, "gfe_whack"); 1500 1501 switch (op) { 1502 case GE_WHACK_RESTART: 1503 #ifndef GE_NOTX 1504 gfe_tx_stop(sc, op); 1505 #endif 1506 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1507 /* FALLTHROUGH */ 1508 case GE_WHACK_START: 1509 #ifndef GE_NOHASH 1510 if (error == 0 && sc->sc_hashtable == NULL) { 1511 error = gfe_hash_alloc(sc); 1512 if (error) 1513 break; 1514 } 1515 if (op != GE_WHACK_RESTART) 1516 gfe_hash_fill(sc); 1517 #endif 1518 #ifndef GE_NORX 1519 if (op != GE_WHACK_RESTART) { 1520 error = gfe_rx_prime(sc); 1521 if (error) 1522 break; 1523 } 1524 #endif 1525 #ifndef GE_NOTX 1526 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1527 if (error) 1528 break; 1529 #endif 1530 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1531 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1532 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1533 GE_WRITE(sc, EICR, 0); 1534 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1535 #ifndef GE_NOHASH 1536 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1537 #endif 1538 #ifndef GE_NORX 1539 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1540 sc->sc_flags |= GE_RXACTIVE; 1541 #endif 1542 /* FALLTHROUGH */ 1543 case GE_WHACK_CHANGE: 1544 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1545 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1546 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1547 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1548 gfe_ifstart(&sc->sc_ec.ec_if); 1549 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1550 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1551 GE_FUNC_EXIT(sc, ""); 1552 return error; 1553 case GE_WHACK_STOP: 1554 break; 1555 } 1556 1557 #ifdef GE_DEBUG 1558 if (error) 1559 GE_DPRINTF(sc, (" failed: %d\n", error)); 1560 #endif 1561 GE_WRITE(sc, EPCR, sc->sc_pcr); 1562 GE_WRITE(sc, EIMR, 0); 1563 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1564 #ifndef GE_NOTX 1565 gfe_tx_stop(sc, GE_WHACK_STOP); 1566 #endif 1567 #ifndef GE_NORX 1568 gfe_rx_stop(sc, GE_WHACK_STOP); 1569 #endif 1570 #ifndef GE_NOHASH 1571 if ((sc->sc_flags & GE_NOFREE) == 0) { 1572 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1573 sc->sc_hashtable = NULL; 1574 } 1575 #endif 1576 1577 GE_FUNC_EXIT(sc, ""); 1578 return error; 1579 } 1580 1581 int 1583 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1584 { 1585 uint32_t w0, add0, add1; 1586 uint32_t result; 1587 1588 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1589 add0 = ((uint32_t) eaddr[5] << 0) | 1590 ((uint32_t) eaddr[4] << 8) | 1591 ((uint32_t) eaddr[3] << 16); 1592 1593 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1594 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1595 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1596 1597 add1 = ((uint32_t) eaddr[2] << 0) | 1598 ((uint32_t) eaddr[1] << 8) | 1599 ((uint32_t) eaddr[0] << 16); 1600 1601 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1602 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1603 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1604 1605 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1606 /* 1607 * hashResult is the 15 bits Hash entry address. 1608 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1609 * MAC address, by nibble swapping in every byte (i.e MAC address 1610 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1611 */ 1612 1613 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1614 /* 1615 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1616 * 1617 * hashFunc0 calculates the hashResult in the following manner: 1618 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1619 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1620 */ 1621 result = (add0 & 3) | ((add0 >> 6) & ~3); 1622 result ^= (add0 >> 15) ^ (add1 >> 0); 1623 result &= 0x1ff; 1624 /* 1625 * hashResult[14:9] = ethernetADD[7:2] 1626 */ 1627 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1628 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1629 } else { 1630 #define TRIBITFLIP 073516240 /* yes its in octal */ 1631 /* 1632 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1633 * 1634 * hashFunc1 calculates the hashResult in the following manner: 1635 * hashResult[08:00] = ethernetADD[06:14] 1636 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1637 */ 1638 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1639 /* 1640 * Now bitswap those 9 bits 1641 */ 1642 result = 0; 1643 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1644 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1645 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1646 1647 /* 1648 * hashResult[14:09] = ethernetADD[00:05] 1649 */ 1650 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1651 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1652 GE_DPRINTF(sc, ("1(%#x)", result)); 1653 } 1654 GE_FUNC_EXIT(sc, ""); 1655 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1656 } 1657 1658 int 1659 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1660 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1661 { 1662 uint64_t he; 1663 uint64_t *maybe_he_p = NULL; 1664 int limit; 1665 int hash; 1666 int maybe_hash = 0; 1667 1668 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1669 1670 hash = gfe_hash_compute(sc, eaddr); 1671 1672 if (sc->sc_hashtable == NULL) { 1673 panic("%s:%d: hashtable == NULL!", device_xname(&sc->sc_dev), 1674 __LINE__); 1675 } 1676 1677 /* 1678 * Assume we are going to insert so create the hash entry we 1679 * are going to insert. We also use it to match entries we 1680 * will be removing. 1681 */ 1682 he = ((uint64_t) eaddr[5] << 43) | 1683 ((uint64_t) eaddr[4] << 35) | 1684 ((uint64_t) eaddr[3] << 27) | 1685 ((uint64_t) eaddr[2] << 19) | 1686 ((uint64_t) eaddr[1] << 11) | 1687 ((uint64_t) eaddr[0] << 3) | 1688 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1689 1690 /* 1691 * The GT will search upto 12 entries for a hit, so we must mimic that. 1692 */ 1693 hash &= sc->sc_hashmask / sizeof(he); 1694 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1695 /* 1696 * Does the GT wrap at the end, stop at the, or overrun the 1697 * end? Assume it wraps for now. Stash a copy of the 1698 * current hash entry. 1699 */ 1700 uint64_t *he_p = &sc->sc_hashtable[hash]; 1701 uint64_t thishe = *he_p; 1702 1703 /* 1704 * If the hash entry isn't valid, that break the chain. And 1705 * this entry a good candidate for reuse. 1706 */ 1707 if ((thishe & HSH_V) == 0) { 1708 maybe_he_p = he_p; 1709 break; 1710 } 1711 1712 /* 1713 * If the hash entry has the same address we are looking for 1714 * then ... if we are removing and the skip bit is set, its 1715 * already been removed. if are adding and the skip bit is 1716 * clear, then its already added. In either return EBUSY 1717 * indicating the op has already been done. Otherwise flip 1718 * the skip bit and return 0. 1719 */ 1720 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1721 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1722 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1723 return EBUSY; 1724 *he_p = thishe ^ HSH_S; 1725 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1726 hash * sizeof(he), sizeof(he), 1727 BUS_DMASYNC_PREWRITE); 1728 GE_FUNC_EXIT(sc, "^"); 1729 return 0; 1730 } 1731 1732 /* 1733 * If we haven't found a slot for the entry and this entry 1734 * is currently being skipped, return this entry. 1735 */ 1736 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1737 maybe_he_p = he_p; 1738 maybe_hash = hash; 1739 } 1740 1741 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1742 } 1743 1744 /* 1745 * If we got here, then there was no entry to remove. 1746 */ 1747 if (op == GE_HASH_REMOVE) { 1748 GE_FUNC_EXIT(sc, "?"); 1749 return ENOENT; 1750 } 1751 1752 /* 1753 * If we couldn't find a slot, return an error. 1754 */ 1755 if (maybe_he_p == NULL) { 1756 GE_FUNC_EXIT(sc, "!"); 1757 return ENOSPC; 1758 } 1759 1760 /* Update the entry. 1761 */ 1762 *maybe_he_p = he; 1763 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1764 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1765 GE_FUNC_EXIT(sc, "+"); 1766 return 0; 1767 } 1768 1769 int 1770 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1771 { 1772 struct gfe_softc * const sc = ec->ec_if.if_softc; 1773 int error; 1774 enum gfe_hash_op op; 1775 enum gfe_rxprio prio; 1776 1777 GE_FUNC_ENTER(sc, "hash_multichg"); 1778 /* 1779 * Is this a wildcard entry? If so and its being removed, recompute. 1780 */ 1781 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1782 if (cmd == SIOCDELMULTI) { 1783 GE_FUNC_EXIT(sc, ""); 1784 return ENETRESET; 1785 } 1786 1787 /* 1788 * Switch in 1789 */ 1790 sc->sc_flags |= GE_ALLMULTI; 1791 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1792 sc->sc_pcr |= ETH_EPCR_PM; 1793 GE_WRITE(sc, EPCR, sc->sc_pcr); 1794 GE_FUNC_EXIT(sc, ""); 1795 return 0; 1796 } 1797 GE_FUNC_EXIT(sc, ""); 1798 return ENETRESET; 1799 } 1800 1801 prio = GE_RXPRIO_MEDLO; 1802 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1803 1804 if (sc->sc_hashtable == NULL) { 1805 GE_FUNC_EXIT(sc, ""); 1806 return 0; 1807 } 1808 1809 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1810 if (error == EBUSY) { 1811 printf("%s: multichg: tried to %s %s again\n", 1812 device_xname(&sc->sc_dev), 1813 cmd == SIOCDELMULTI ? "remove" : "add", 1814 ether_sprintf(enm->enm_addrlo)); 1815 GE_FUNC_EXIT(sc, ""); 1816 return 0; 1817 } 1818 1819 if (error == ENOENT) { 1820 printf("%s: multichg: failed to remove %s: not in table\n", 1821 device_xname(&sc->sc_dev), 1822 ether_sprintf(enm->enm_addrlo)); 1823 GE_FUNC_EXIT(sc, ""); 1824 return 0; 1825 } 1826 1827 if (error == ENOSPC) { 1828 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1829 device_xname(&sc->sc_dev), 1830 ether_sprintf(enm->enm_addrlo)); 1831 GE_FUNC_EXIT(sc, ""); 1832 return ENETRESET; 1833 } 1834 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1835 device_xname(&sc->sc_dev), 1836 cmd == SIOCDELMULTI ? "remove" : "add", 1837 ether_sprintf(enm->enm_addrlo))); 1838 GE_FUNC_EXIT(sc, ""); 1839 return 0; 1840 } 1841 1842 int 1843 gfe_hash_fill(struct gfe_softc *sc) 1844 { 1845 struct ether_multistep step; 1846 struct ether_multi *enm; 1847 int error; 1848 1849 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1850 1851 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1852 CLLADDR(sc->sc_ec.ec_if.if_sadl)); 1853 if (error) 1854 GE_FUNC_EXIT(sc, "!"); 1855 return error; 1856 1857 sc->sc_flags &= ~GE_ALLMULTI; 1858 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1859 sc->sc_pcr &= ~ETH_EPCR_PM; 1860 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1861 while (enm != NULL) { 1862 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1863 sc->sc_flags |= GE_ALLMULTI; 1864 sc->sc_pcr |= ETH_EPCR_PM; 1865 } else { 1866 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1867 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1868 if (error == ENOSPC) 1869 break; 1870 } 1871 ETHER_NEXT_MULTI(step, enm); 1872 } 1873 1874 GE_FUNC_EXIT(sc, ""); 1875 return error; 1876 } 1877 1878 int 1879 gfe_hash_alloc(struct gfe_softc *sc) 1880 { 1881 int error; 1882 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1883 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1884 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1885 BUS_DMA_NOCACHE); 1886 if (error) { 1887 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1888 device_xname(&sc->sc_dev), sc->sc_hashmask + 1, error); 1889 GE_FUNC_EXIT(sc, ""); 1890 return error; 1891 } 1892 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1893 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1894 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1895 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1896 GE_FUNC_EXIT(sc, ""); 1897 return 0; 1898 } 1899
Indexes created Tue Sep 30 11:09:46 GMT 2025