if_gfe.c revision 1.6
1 /* $NetBSD: if_gfe.c,v 1.6 2003/04/08 19:37:17 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include "opt_inet.h" 45 #include "bpfilter.h" 46 47 #include <sys/param.h> 48 #include <sys/types.h> 49 #include <sys/inttypes.h> 50 #include <sys/queue.h> 51 52 #include <sys/callout.h> 53 #include <sys/device.h> 54 #include <sys/errno.h> 55 #include <sys/ioctl.h> 56 #include <sys/mbuf.h> 57 #include <sys/socket.h> 58 59 #include <machine/bus.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_ether.h> 64 #include <net/if_media.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <dev/mii/miivar.h> 75 76 #include <dev/marvell/gtintrreg.h> 77 #include <dev/marvell/gtethreg.h> 78 79 #include <dev/marvell/gtvar.h> 80 #include <dev/marvell/if_gfevar.h> 81 82 #define GE_READ(sc, reg) \ 83 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 84 #define GE_WRITE(sc, reg, v) \ 85 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 86 87 #define GE_DEBUG 88 #if 0 89 #define GE_NOHASH 90 #define GE_NORX 91 #endif 92 93 #ifdef GE_DEBUG 94 #define GE_DPRINTF(sc, a) do \ 95 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 96 printf a; \ 97 while (0) 98 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 99 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 100 #else 101 #define GE_DPRINTF(sc, a) do { } while (0) 102 #define GE_FUNC_ENTER(sc, func) do { } while (0) 103 #define GE_FUNC_EXIT(sc, str) do { } while (0) 104 #endif 105 enum gfe_whack_op { 106 GE_WHACK_START, GE_WHACK_RESTART, 107 GE_WHACK_CHANGE, GE_WHACK_STOP 108 }; 109 110 enum gfe_hash_op { 111 GE_HASH_ADD, GE_HASH_REMOVE, 112 }; 113 114 #if 1 115 #define htogt32(a) htobe32(a) 116 #define gt32toh(a) be32toh(a) 117 #else 118 #define htogt32(a) htole32(a) 119 #define gt32toh(a) le32toh(a) 120 #endif 121 122 #define GE_RXDSYNC(sc, rxq, n, ops) \ 123 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 124 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 125 (ops)) 126 #define GE_RXDPRESYNC(sc, rxq, n) \ 127 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 128 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 129 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 130 131 #define GE_TXDSYNC(sc, txq, n, ops) \ 132 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 133 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 134 (ops)) 135 #define GE_TXDPRESYNC(sc, txq, n) \ 136 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 137 #define GE_TXDPOSTSYNC(sc, txq, n) \ 138 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 139 140 #define STATIC 141 142 STATIC int gfe_match (struct device *, struct cfdata *, void *); 143 STATIC void gfe_attach (struct device *, struct device *, void *); 144 145 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 146 size_t, int); 147 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 148 149 STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); 150 STATIC void gfe_ifstart (struct ifnet *); 151 STATIC void gfe_ifwatchdog (struct ifnet *); 152 153 STATIC int gfe_mii_mediachange (struct ifnet *); 154 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 155 STATIC int gfe_mii_read (struct device *, int, int); 156 STATIC void gfe_mii_write (struct device *, int, int, int); 157 STATIC void gfe_mii_statchg (struct device *); 158 159 STATIC void gfe_tick(void *arg); 160 161 STATIC void gfe_tx_restart(void *); 162 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 163 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 164 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 165 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 166 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 167 168 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 169 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 170 STATIC int gfe_rx_prime(struct gfe_softc *); 171 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 172 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 173 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 174 175 STATIC int gfe_intr(void *); 176 177 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 178 179 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 180 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 181 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 182 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 183 u_long); 184 STATIC int gfe_hash_fill(struct gfe_softc *); 185 STATIC int gfe_hash_alloc(struct gfe_softc *); 186 187 /* Linkup to the rest of the kernel */ 188 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 189 gfe_match, gfe_attach, NULL, NULL); 190 191 extern struct cfdriver gfe_cd; 192 193 int 194 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 195 { 196 struct gt_softc *gt = (struct gt_softc *) parent; 197 struct gt_attach_args *ga = aux; 198 uint8_t enaddr[6]; 199 200 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 201 return 0; 202 203 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 204 return 0; 205 206 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 207 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 208 return 0; 209 210 return 1; 211 } 212 213 /* 214 * Attach this instance, and then all the sub-devices 215 */ 216 void 217 gfe_attach(struct device *parent, struct device *self, void *aux) 218 { 219 struct gt_attach_args * const ga = aux; 220 struct gt_softc * const gt = (struct gt_softc *) parent; 221 struct gfe_softc * const sc = (struct gfe_softc *) self; 222 struct ifnet * const ifp = &sc->sc_ec.ec_if; 223 uint32_t data; 224 uint8_t enaddr[6]; 225 int phyaddr; 226 uint32_t sdcr; 227 228 GT_ETHERFOUND(gt, ga); 229 230 sc->sc_gt_memt = ga->ga_memt; 231 sc->sc_gt_memh = ga->ga_memh; 232 sc->sc_dmat = ga->ga_dmat; 233 sc->sc_macno = ga->ga_unit; 234 235 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 236 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 237 aprint_error(": failed to map registers\n"); 238 } 239 240 callout_init(&sc->sc_co); 241 242 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 243 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 244 245 gtget_macaddr(gt, sc->sc_macno, enaddr); 246 247 sc->sc_pcr = GE_READ(sc, EPCR); 248 sc->sc_pcxr = GE_READ(sc, EPCXR); 249 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 250 251 aprint_normal(": address %s", ether_sprintf(enaddr)); 252 253 #if defined(DEBUG) 254 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 255 #endif 256 257 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 258 if (sc->sc_dev.dv_cfdata->cf_flags & 1) { 259 aprint_normal(", phy %d (rmii)", phyaddr); 260 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 261 } else { 262 aprint_normal(", phy %d (mii)", phyaddr); 263 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 264 } 265 sc->sc_pcxr &= ~(3 << 14); 266 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 267 268 if (sc->sc_pcr & ETH_EPCR_EN) { 269 int tries = 1000; 270 /* 271 * Abort transmitter and receiver and wait for them to quiese 272 */ 273 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 274 do { 275 delay(100); 276 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 277 } 278 279 sc->sc_pcr &= ~ETH_EPCR_EN; 280 281 #if defined(DEBUG) 282 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 283 #endif 284 285 /* 286 * Now turn off the GT. If it didn't quiese, too ***ing bad. 287 */ 288 GE_WRITE(sc, EPCR, sc->sc_pcr); 289 GE_WRITE(sc, EIMR, sc->sc_intrmask); 290 sdcr = GE_READ(sc, ESDCR); 291 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 292 sdcr |= ETH_ESDCR_RIFB; 293 GE_WRITE(sc, ESDCR, sdcr); 294 sc->sc_max_frame_length = 1536; 295 296 aprint_normal("\n"); 297 sc->sc_mii.mii_ifp = ifp; 298 sc->sc_mii.mii_readreg = gfe_mii_read; 299 sc->sc_mii.mii_writereg = gfe_mii_write; 300 sc->sc_mii.mii_statchg = gfe_mii_statchg; 301 302 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 303 gfe_mii_mediastatus); 304 305 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 306 MII_OFFSET_ANY, MIIF_NOISOLATE); 307 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 308 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 309 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 310 } else { 311 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 312 } 313 314 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 315 ifp->if_softc = sc; 316 /* ifp->if_mowner = &sc->sc_mowner; */ 317 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 318 #if 0 319 ifp->if_flags |= IFF_DEBUG; 320 #endif 321 ifp->if_ioctl = gfe_ifioctl; 322 ifp->if_start = gfe_ifstart; 323 ifp->if_watchdog = gfe_ifwatchdog; 324 325 if_attach(ifp); 326 ether_ifattach(ifp, enaddr); 327 #if NBPFILTER > 0 328 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 329 #endif 330 #if NRND > 0 331 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 332 #endif 333 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 334 gfe_intr, sc); 335 } 336 337 int 338 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 339 size_t size, int flags) 340 { 341 int error = 0; 342 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 343 gdm->gdm_size = size; 344 gdm->gdm_maxsegs = maxsegs; 345 346 #if 0 347 flags |= BUS_DMA_NOCACHE; 348 #endif 349 350 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, NBPG, 351 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 352 BUS_DMA_NOWAIT); 353 if (error) 354 goto fail; 355 356 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 357 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 358 if (error) 359 goto fail; 360 361 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 362 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 363 if (error) 364 goto fail; 365 366 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 367 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 368 if (error) 369 goto fail; 370 371 /* invalidate from cache */ 372 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 373 BUS_DMASYNC_PREREAD); 374 fail: 375 if (error) { 376 gfe_dmamem_free(sc, gdm); 377 GE_DPRINTF(sc, (":err=%d", error)); 378 } 379 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 380 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 381 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 382 GE_FUNC_EXIT(sc, ""); 383 return error; 384 } 385 386 void 387 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 388 { 389 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 390 if (gdm->gdm_map) 391 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 392 if (gdm->gdm_kva) 393 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 394 if (gdm->gdm_nsegs > 0) 395 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 396 gdm->gdm_map = NULL; 397 gdm->gdm_kva = NULL; 398 gdm->gdm_nsegs = 0; 399 GE_FUNC_EXIT(sc, ""); 400 } 401 402 int 403 gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 404 { 405 struct gfe_softc * const sc = ifp->if_softc; 406 struct ifreq *ifr = (struct ifreq *) data; 407 struct ifaddr *ifa = (struct ifaddr *) data; 408 int s, error = 0; 409 410 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 411 s = splnet(); 412 413 switch (cmd) { 414 case SIOCSIFADDR: 415 ifp->if_flags |= IFF_UP; 416 switch (ifa->ifa_addr->sa_family) { 417 #ifdef INET 418 case AF_INET: 419 error = gfe_whack(sc, GE_WHACK_START); 420 if (error == 0) 421 arp_ifinit(ifp, ifa); 422 break; 423 #endif 424 default: 425 error = gfe_whack(sc, GE_WHACK_START); 426 break; 427 } 428 break; 429 430 case SIOCSIFFLAGS: 431 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 432 case IFF_UP|IFF_RUNNING:/* active->active, update */ 433 error = gfe_whack(sc, GE_WHACK_CHANGE); 434 break; 435 case IFF_RUNNING: /* not up, so we stop */ 436 error = gfe_whack(sc, GE_WHACK_STOP); 437 break; 438 case IFF_UP: /* not running, so we start */ 439 error = gfe_whack(sc, GE_WHACK_START); 440 break; 441 case 0: /* idle->idle: do nothing */ 442 break; 443 } 444 break; 445 446 case SIOCADDMULTI: 447 case SIOCDELMULTI: 448 error = (cmd == SIOCADDMULTI) 449 ? ether_addmulti(ifr, &sc->sc_ec) 450 : ether_delmulti(ifr, &sc->sc_ec); 451 if (error == ENETRESET) { 452 if (ifp->if_flags & IFF_RUNNING) 453 error = gfe_whack(sc, GE_WHACK_CHANGE); 454 else 455 error = 0; 456 } 457 break; 458 459 case SIOCSIFMTU: 460 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 461 error = EINVAL; 462 break; 463 } 464 ifp->if_mtu = ifr->ifr_mtu; 465 break; 466 467 case SIOCSIFMEDIA: 468 case SIOCGIFMEDIA: 469 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 470 break; 471 472 default: 473 error = EINVAL; 474 break; 475 } 476 splx(s); 477 GE_FUNC_EXIT(sc, ""); 478 return error; 479 } 480 481 void 482 gfe_ifstart(struct ifnet *ifp) 483 { 484 struct gfe_softc * const sc = ifp->if_softc; 485 struct mbuf *m; 486 487 GE_FUNC_ENTER(sc, "gfe_ifstart"); 488 489 if ((ifp->if_flags & IFF_RUNNING) == 0) { 490 GE_FUNC_EXIT(sc, "$"); 491 return; 492 } 493 494 if (sc->sc_txq[GE_TXPRIO_HI] == NULL) { 495 ifp->if_flags |= IFF_OACTIVE; 496 #if defined(DEBUG) || defined(DIAGNOSTIC) 497 printf("%s: ifstart: txq not yet created\n", ifp->if_xname); 498 #endif 499 GE_FUNC_EXIT(sc, ""); 500 return; 501 } 502 503 for (;;) { 504 IF_DEQUEUE(&ifp->if_snd, m); 505 if (m == NULL) { 506 ifp->if_flags &= ~IFF_OACTIVE; 507 GE_FUNC_EXIT(sc, ""); 508 return; 509 } 510 511 /* 512 * No space in the pending queue? try later. 513 */ 514 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq)) 515 break; 516 517 /* 518 * Try to enqueue a mbuf to the device. If that fails, we 519 * can always try to map the next mbuf. 520 */ 521 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq, m); 522 GE_DPRINTF(sc, (">")); 523 #ifndef GE_NOTX 524 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 525 #endif 526 } 527 528 /* 529 * Attempt to queue the mbuf for send failed. 530 */ 531 IF_PREPEND(&ifp->if_snd, m); 532 ifp->if_flags |= IFF_OACTIVE; 533 GE_FUNC_EXIT(sc, "%%"); 534 } 535 536 void 537 gfe_ifwatchdog(struct ifnet *ifp) 538 { 539 struct gfe_softc * const sc = ifp->if_softc; 540 struct gfe_txqueue *txq; 541 542 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 543 printf("%s: device timeout", sc->sc_dev.dv_xname); 544 if ((txq = sc->sc_txq[GE_TXPRIO_HI]) != NULL) { 545 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 546 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 547 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 548 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 549 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 550 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 551 GE_READ(sc, EICR)); 552 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 553 GE_TXDPRESYNC(sc, txq, curtxdnum); 554 } 555 printf("\n"); 556 ifp->if_oerrors++; 557 (void) gfe_whack(sc, GE_WHACK_RESTART); 558 GE_FUNC_EXIT(sc, ""); 559 } 560 561 int 563 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 564 { 565 struct gfe_rxqueue *rxq; 566 volatile struct gt_eth_desc *rxd; 567 const bus_dma_segment_t *ds; 568 int error; 569 int idx; 570 bus_addr_t nxtaddr; 571 bus_size_t boff; 572 573 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 574 GE_DPRINTF(sc, ("(%d)", rxprio)); 575 if (sc->sc_rxq[rxprio] != NULL) { 576 GE_FUNC_EXIT(sc, ""); 577 return 0; 578 } 579 580 rxq = (struct gfe_rxqueue *) malloc(sizeof(*rxq), M_DEVBUF, M_NOWAIT); 581 if (rxq == NULL) { 582 GE_FUNC_EXIT(sc, "!"); 583 return ENOMEM; 584 } 585 586 memset(rxq, 0, sizeof(*rxq)); 587 588 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 589 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 590 if (error) { 591 free(rxq, M_DEVBUF); 592 GE_FUNC_EXIT(sc, "!!"); 593 return error; 594 } 595 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 596 GE_RXBUF_MEMSIZE, 0); 597 if (error) { 598 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 599 free(rxq, M_DEVBUF); 600 GE_FUNC_EXIT(sc, "!!!"); 601 return error; 602 } 603 604 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_TXMEM_SIZE); 605 606 sc->sc_rxq[rxprio] = rxq; 607 rxq->rxq_descs = 608 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 609 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 610 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 611 rxq->rxq_fi = 0; 612 rxq->rxq_active = GE_RXDESC_MAX; 613 for (idx = 0, rxd = rxq->rxq_descs, 614 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 615 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 616 idx < GE_RXDESC_MAX; 617 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 618 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 619 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 620 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 621 /* 622 * update the nxtptr to point to the next txd. 623 */ 624 if (idx == GE_RXDESC_MAX - 1) 625 nxtaddr = rxq->rxq_desc_busaddr; 626 rxd->ed_nxtptr = htogt32(nxtaddr); 627 boff += GE_RXBUF_SIZE; 628 if (boff == ds->ds_len) { 629 ds++; 630 boff = 0; 631 } 632 } 633 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 634 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 635 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 636 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 637 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 638 BUS_DMASYNC_PREREAD); 639 640 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 641 switch (rxprio) { 642 case GE_RXPRIO_HI: 643 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 644 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 645 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 646 break; 647 case GE_RXPRIO_MEDHI: 648 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 649 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 650 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 651 break; 652 case GE_RXPRIO_MEDLO: 653 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 654 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 655 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 656 break; 657 case GE_RXPRIO_LO: 658 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 659 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 660 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 661 break; 662 } 663 GE_FUNC_EXIT(sc, ""); 664 return error; 665 } 666 667 void 668 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 669 { 670 struct ifnet * const ifp = &sc->sc_ec.ec_if; 671 struct gfe_rxqueue * const rxq = sc->sc_rxq[rxprio]; 672 struct mbuf *m = rxq->rxq_curpkt; 673 674 GE_FUNC_ENTER(sc, "gfe_rx_get"); 675 GE_DPRINTF(sc, ("(%d)", rxprio)); 676 677 while (rxq->rxq_active > 0) { 678 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 679 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 680 const struct ether_header *eh; 681 unsigned int cmdsts; 682 size_t buflen; 683 684 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 685 cmdsts = gt32toh(rxd->ed_cmdsts); 686 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 687 rxq->rxq_cmdsts = cmdsts; 688 /* 689 * Sometimes the GE "forgets" to reset the ownership bit. 690 * But if the length has been rewritten, the packet is ours 691 * so pretend the O bit is set. 692 */ 693 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 694 if ((cmdsts & RX_CMD_O) && buflen == 0) { 695 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 696 break; 697 } 698 699 /* 700 * If this is not a single buffer packet with no errors 701 * or for some reason it's bigger than our frame size, 702 * ignore it and go to the next packet. 703 */ 704 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 705 (RX_CMD_F|RX_CMD_L) || 706 buflen > sc->sc_max_frame_length) { 707 GE_DPRINTF(sc, ("!")); 708 --rxq->rxq_active; 709 ifp->if_ipackets++; 710 ifp->if_ierrors++; 711 goto give_it_back; 712 } 713 714 if (m == NULL) { 715 MGETHDR(m, M_DONTWAIT, MT_DATA); 716 if (m == NULL) { 717 GE_DPRINTF(sc, ("?")); 718 break; 719 } 720 } 721 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 722 MCLGET(m, M_DONTWAIT); 723 if ((m->m_flags & M_EXT) == 0) { 724 GE_DPRINTF(sc, ("?")); 725 break; 726 } 727 } 728 m->m_data += 2; 729 m->m_len = 0; 730 m->m_pkthdr.len = 0; 731 m->m_pkthdr.rcvif = ifp; 732 rxq->rxq_cmdsts = cmdsts; 733 --rxq->rxq_active; 734 735 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 736 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 737 738 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 739 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 740 m->m_len = buflen; 741 m->m_pkthdr.len = buflen; 742 m->m_flags |= M_HASFCS; 743 744 ifp->if_ipackets++; 745 #if NBPFILTER > 0 746 if (ifp->if_bpf != NULL) 747 bpf_mtap(ifp->if_bpf, m); 748 #endif 749 750 eh = (const struct ether_header *) m->m_data; 751 if ((ifp->if_flags & IFF_PROMISC) || 752 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 753 (rxq->rxq_cmdsts & RX_STS_HE) || 754 (eh->ether_dhost[0] & 1) != 0 || 755 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 756 ETHER_ADDR_LEN) == 0) { 757 (*ifp->if_input)(ifp, m); 758 m = NULL; 759 GE_DPRINTF(sc, (">")); 760 } else { 761 m->m_len = 0; 762 m->m_pkthdr.len = 0; 763 GE_DPRINTF(sc, ("+")); 764 } 765 rxq->rxq_cmdsts = 0; 766 767 give_it_back: 768 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 769 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 770 #if 0 771 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 772 rxq->rxq_fi, 773 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 774 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 775 #endif 776 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 777 if (++rxq->rxq_fi == GE_RXDESC_MAX) 778 rxq->rxq_fi = 0; 779 rxq->rxq_active++; 780 } 781 rxq->rxq_curpkt = m; 782 GE_FUNC_EXIT(sc, ""); 783 } 784 785 uint32_t 786 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 787 { 788 struct ifnet * const ifp = &sc->sc_ec.ec_if; 789 struct gfe_rxqueue *rxq; 790 uint32_t rxbits; 791 #define RXPRIO_DECODER 0xffffaa50 792 GE_FUNC_ENTER(sc, "gfe_rx_process"); 793 794 rxbits = ETH_IR_RxBuffer_GET(cause); 795 while (rxbits) { 796 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 797 GE_DPRINTF(sc, ("%1x", rxbits)); 798 rxbits &= ~(1 << rxprio); 799 gfe_rx_get(sc, rxprio); 800 } 801 802 rxbits = ETH_IR_RxError_GET(cause); 803 while (rxbits) { 804 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 805 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 806 int idx; 807 rxbits &= ~(1 << rxprio); 808 rxq = sc->sc_rxq[rxprio]; 809 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 810 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 811 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 812 sc->sc_tickflags |= GE_TICK_RX_RESTART; 813 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 814 } 815 ifp->if_ierrors++; 816 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 817 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 818 memset(masks, 0, sizeof(masks)); 819 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 820 0, rxq->rxq_desc_mem.gdm_size, 821 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 822 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 823 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 824 825 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 826 masks[idx/32] |= 1 << (idx & 31); 827 } 828 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 829 0, rxq->rxq_desc_mem.gdm_size, 830 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 831 #if defined(DEBUG) 832 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 833 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 834 rxq->rxq_cmdsts, masks[0], masks[1]); 835 #endif 836 } 837 if ((intrmask & ETH_IR_RxBits) == 0) 838 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 839 840 GE_FUNC_EXIT(sc, ""); 841 return intrmask; 842 } 843 844 int 845 gfe_rx_prime(struct gfe_softc *sc) 846 { 847 struct gfe_rxqueue *rxq; 848 int error; 849 850 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 851 852 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 853 if (error) 854 goto bail; 855 rxq = sc->sc_rxq[GE_RXPRIO_HI]; 856 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 857 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 858 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 859 } 860 sc->sc_intrmask |= rxq->rxq_intrbits; 861 862 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 863 if (error) 864 goto bail; 865 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 866 rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 867 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 868 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 869 sc->sc_intrmask |= rxq->rxq_intrbits; 870 } 871 872 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 873 if (error) 874 goto bail; 875 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 876 rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 877 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 878 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 879 sc->sc_intrmask |= rxq->rxq_intrbits; 880 } 881 882 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 883 if (error) 884 goto bail; 885 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 886 rxq = sc->sc_rxq[GE_RXPRIO_LO]; 887 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 888 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 889 sc->sc_intrmask |= rxq->rxq_intrbits; 890 } 891 892 bail: 893 GE_FUNC_EXIT(sc, ""); 894 return error; 895 } 896 897 void 898 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 899 { 900 struct gfe_rxqueue *rxq = sc->sc_rxq[rxprio]; 901 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 902 if (rxq == NULL) { 903 GE_FUNC_EXIT(sc, ""); 904 return; 905 } 906 907 if (rxq->rxq_curpkt) 908 m_freem(rxq->rxq_curpkt); 909 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 910 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 911 free(rxq, M_DEVBUF); 912 sc->sc_rxq[rxprio] = NULL; 913 GE_FUNC_EXIT(sc, ""); 914 } 915 916 void 917 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 918 { 919 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 920 sc->sc_flags &= ~GE_RXACTIVE; 921 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 922 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 923 GE_WRITE(sc, EIMR, sc->sc_intrmask); 924 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 925 do { 926 delay(10); 927 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 928 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 929 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 930 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 931 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 932 GE_FUNC_EXIT(sc, ""); 933 } 934 935 void 937 gfe_tick(void *arg) 938 { 939 struct gfe_softc * const sc = arg; 940 uint32_t intrmask; 941 unsigned int tickflags; 942 int s; 943 944 GE_FUNC_ENTER(sc, "gfe_tick"); 945 946 s = splnet(); 947 948 tickflags = sc->sc_tickflags; 949 sc->sc_tickflags = 0; 950 intrmask = sc->sc_intrmask; 951 if (tickflags & GE_TICK_TX_IFSTART) 952 gfe_ifstart(&sc->sc_ec.ec_if); 953 if (tickflags & GE_TICK_RX_RESTART) { 954 intrmask |= sc->sc_idlemask; 955 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 956 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_HI]; 957 rxq->rxq_fi = 0; 958 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 959 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 960 } 961 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 962 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 963 rxq->rxq_fi = 0; 964 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 965 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 966 } 967 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 968 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 969 rxq->rxq_fi = 0; 970 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 971 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 972 } 973 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 974 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_LO]; 975 rxq->rxq_fi = 0; 976 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 977 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 978 } 979 sc->sc_idlemask = 0; 980 } 981 if (intrmask != sc->sc_intrmask) { 982 sc->sc_intrmask = intrmask; 983 GE_WRITE(sc, EIMR, sc->sc_intrmask); 984 } 985 gfe_intr(sc); 986 splx(s); 987 988 GE_FUNC_EXIT(sc, ""); 989 } 990 991 int 992 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 993 { 994 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 995 struct ifnet * const ifp = &sc->sc_ec.ec_if; 996 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 997 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 998 uint32_t intrmask = sc->sc_intrmask; 999 struct mbuf *m; 1000 1001 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1002 1003 /* 1004 * Anything in the pending queue to enqueue? if not, punt. 1005 * otherwise grab its dmamap. 1006 */ 1007 if ((m = txq->txq_pendq.ifq_head) == NULL) { 1008 GE_FUNC_EXIT(sc, "-"); 1009 return 0; 1010 } 1011 1012 /* 1013 * Have we [over]consumed our limit of descriptors? 1014 * Do we have enough free descriptors? 1015 */ 1016 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1017 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1018 uint32_t cmdsts; 1019 size_t pktlen; 1020 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1021 cmdsts = gt32toh(txd2->ed_cmdsts); 1022 if (cmdsts & TX_CMD_O) { 1023 int nextin; 1024 /* 1025 * Sometime the Discovery forgets to update the 1026 * last descriptor. See if we own the descriptor 1027 * after it (since we know we've turned that to 1028 * the discovery and if we owned it, the Discovery 1029 * gave it back). If we do, we know the Discovery 1030 * gave back this one but forgot to mark it as ours. 1031 */ 1032 nextin = txq->txq_fi + 1; 1033 if (nextin == GE_TXDESC_MAX) 1034 nextin = 0; 1035 GE_TXDPOSTSYNC(sc, txq, nextin); 1036 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1037 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1038 GE_TXDPRESYNC(sc, txq, nextin); 1039 GE_FUNC_EXIT(sc, "@"); 1040 return 0; 1041 } 1042 #ifdef DEBUG 1043 printf("%s: txenqueue: transmitter resynced at %d\n", 1044 sc->sc_dev.dv_xname, txq->txq_fi); 1045 #endif 1046 } 1047 if (++txq->txq_fi == GE_TXDESC_MAX) 1048 txq->txq_fi = 0; 1049 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1050 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1051 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1052 txq->txq_nactive--; 1053 1054 /* statistics */ 1055 ifp->if_opackets++; 1056 if (cmdsts & TX_STS_ES) 1057 ifp->if_oerrors++; 1058 GE_DPRINTF(sc, ("%%")); 1059 } 1060 1061 /* 1062 * If this packet would wrap around the end of the buffer, reset back 1063 * to the beginning. 1064 */ 1065 if (txq->txq_outptr + m->m_pkthdr.len > GE_TXBUF_SIZE) { 1066 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1067 txq->txq_outptr = 0; 1068 } 1069 1070 /* 1071 * Make sure the output packet doesn't run over the beginning of 1072 * what we've already given the GT. 1073 */ 1074 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1075 txq->txq_outptr + m->m_pkthdr.len > txq->txq_inptr) { 1076 intrmask |= txq->txq_intrbits & 1077 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1078 if (sc->sc_intrmask != intrmask) { 1079 sc->sc_intrmask = intrmask; 1080 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1081 } 1082 GE_FUNC_EXIT(sc, "#"); 1083 return 0; 1084 } 1085 1086 /* 1087 * The end-of-list descriptor we put on last time is the starting point 1088 * for this packet. The GT is supposed to terminate list processing on 1089 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1090 * must terminate the list. 1091 */ 1092 intrmask = sc->sc_intrmask; 1093 1094 m_copydata(m, 0, m->m_pkthdr.len, 1095 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1096 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1097 txq->txq_outptr, m->m_pkthdr.len, BUS_DMASYNC_PREWRITE); 1098 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1099 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1100 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1101 1102 /* 1103 * Request a buffer interrupt every 2/3 of the way thru the transmit 1104 * buffer. 1105 */ 1106 txq->txq_ei_gapcount += m->m_pkthdr.len + 7; 1107 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1108 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1109 txq->txq_ei_gapcount = 0; 1110 } else { 1111 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1112 } 1113 #if 0 1114 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1115 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1116 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1117 #endif 1118 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1119 1120 txq->txq_outptr += roundup(m->m_pkthdr.len, dcache_line_size); 1121 /* 1122 * Tell the SDMA engine to "Fetch!" 1123 */ 1124 GE_WRITE(sc, ESDCMR, 1125 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1126 1127 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1128 1129 /* 1130 * Update the last out appropriately. 1131 */ 1132 txq->txq_nactive++; 1133 if (++txq->txq_lo == GE_TXDESC_MAX) 1134 txq->txq_lo = 0; 1135 1136 /* 1137 * Move mbuf from the pending queue to the snd queue. 1138 */ 1139 IF_DEQUEUE(&txq->txq_pendq, m); 1140 #if NBPFILTER > 0 1141 if (ifp->if_bpf != NULL) 1142 bpf_mtap(ifp->if_bpf, m); 1143 #endif 1144 m_freem(m); 1145 ifp->if_flags &= ~IFF_OACTIVE; 1146 1147 /* 1148 * Since we have put an item into the packet queue, we now want 1149 * an interrupt when the transmit queue finishes processing the 1150 * list. But only update the mask if needs changing. 1151 */ 1152 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1153 if (sc->sc_intrmask != intrmask) { 1154 sc->sc_intrmask = intrmask; 1155 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1156 } 1157 if (ifp->if_timer == 0) 1158 ifp->if_timer = 5; 1159 GE_FUNC_EXIT(sc, "*"); 1160 return 1; 1161 } 1162 1163 uint32_t 1164 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1165 { 1166 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1167 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1168 1169 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1170 1171 if (txq == NULL) { 1172 GE_FUNC_EXIT(sc, ""); 1173 return intrmask; 1174 } 1175 1176 while (txq->txq_nactive > 0) { 1177 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1178 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1179 uint32_t cmdsts; 1180 size_t pktlen; 1181 1182 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1183 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1184 int nextin; 1185 1186 if (txq->txq_nactive == 1) { 1187 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1188 GE_FUNC_EXIT(sc, ""); 1189 return intrmask; 1190 } 1191 /* 1192 * Sometimes the Discovery forgets to update the 1193 * ownership bit in the descriptor. See if we own the 1194 * descriptor after it (since we know we've turned 1195 * that to the Discovery and if we own it now then the 1196 * Discovery gave it back). If we do, we know the 1197 * Discovery gave back this one but forgot to mark it 1198 * as ours. 1199 */ 1200 nextin = txq->txq_fi + 1; 1201 if (nextin == GE_TXDESC_MAX) 1202 nextin = 0; 1203 GE_TXDPOSTSYNC(sc, txq, nextin); 1204 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1205 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1206 GE_TXDPRESYNC(sc, txq, nextin); 1207 GE_FUNC_EXIT(sc, ""); 1208 return intrmask; 1209 } 1210 #ifdef DEBUG 1211 printf("%s: txdone: transmitter resynced at %d\n", 1212 sc->sc_dev.dv_xname, txq->txq_fi); 1213 #endif 1214 } 1215 #if 0 1216 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1217 txq->txq_lo, 1218 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1219 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1220 #endif 1221 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1222 if (++txq->txq_fi == GE_TXDESC_MAX) 1223 txq->txq_fi = 0; 1224 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1225 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1226 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1227 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1228 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1229 1230 /* statistics */ 1231 ifp->if_opackets++; 1232 if (cmdsts & TX_STS_ES) 1233 ifp->if_oerrors++; 1234 1235 /* txd->ed_bufptr = 0; */ 1236 1237 ifp->if_timer = 5; 1238 --txq->txq_nactive; 1239 } 1240 if (txq->txq_nactive != 0) 1241 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1242 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1243 ifp->if_timer = 0; 1244 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1245 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1246 GE_FUNC_EXIT(sc, ""); 1247 return intrmask; 1248 } 1249 1250 int 1251 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1252 { 1253 struct gfe_txqueue *txq; 1254 volatile struct gt_eth_desc *txd; 1255 unsigned int i; 1256 bus_addr_t addr; 1257 1258 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1259 1260 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1261 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1262 1263 if ((txq = sc->sc_txq[txprio]) == NULL) { 1264 int error; 1265 txq = (struct gfe_txqueue *) malloc(sizeof(*txq), 1266 M_DEVBUF, M_NOWAIT); 1267 if (txq == NULL) { 1268 GE_FUNC_EXIT(sc, ""); 1269 return ENOMEM; 1270 } 1271 memset(txq, 0, sizeof(*txq)); 1272 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1273 GE_TXMEM_SIZE, BUS_DMA_NOCACHE); 1274 if (error) { 1275 free(txq, M_DEVBUF); 1276 GE_FUNC_EXIT(sc, ""); 1277 return error; 1278 } 1279 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, 1280 GE_TXBUF_SIZE, 0); 1281 if (error) { 1282 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1283 free(txq, M_DEVBUF); 1284 GE_FUNC_EXIT(sc, ""); 1285 return error; 1286 } 1287 sc->sc_txq[txprio] = txq; 1288 } 1289 1290 txq->txq_descs = 1291 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1292 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1293 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1294 1295 txq->txq_pendq.ifq_maxlen = 10; 1296 txq->txq_ei_gapcount = 0; 1297 txq->txq_nactive = 0; 1298 txq->txq_fi = 0; 1299 txq->txq_lo = 0; 1300 txq->txq_inptr = GE_TXBUF_SIZE; 1301 txq->txq_outptr = 0; 1302 for (i = 0, txd = txq->txq_descs, 1303 addr = txq->txq_desc_busaddr + sizeof(*txd); 1304 i < GE_TXDESC_MAX - 1; 1305 i++, txd++, addr += sizeof(*txd)) { 1306 /* 1307 * update the nxtptr to point to the next txd. 1308 */ 1309 txd->ed_cmdsts = 0; 1310 txd->ed_nxtptr = htogt32(addr); 1311 } 1312 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1313 htogt32(txq->txq_desc_busaddr); 1314 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1315 GE_TXMEM_SIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1316 1317 switch (txprio) { 1318 case GE_TXPRIO_HI: 1319 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1320 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1321 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1322 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1323 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1324 break; 1325 1326 case GE_TXPRIO_LO: 1327 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1328 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1329 txq->txq_epsrbits = ETH_EPSR_TxLow; 1330 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1331 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1332 break; 1333 1334 case GE_TXPRIO_NONE: 1335 break; 1336 } 1337 #if 0 1338 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1339 gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); 1340 GE_DPRINTF(sc, (")")); 1341 #endif 1342 1343 /* 1344 * If we are restarting, there may be packets in the pending queue 1345 * waiting to be enqueued. Try enqueuing packets from both priority 1346 * queues until the pending queue is empty or there no room for them 1347 * on the device. 1348 */ 1349 while (gfe_tx_enqueue(sc, txprio)) 1350 continue; 1351 1352 GE_FUNC_EXIT(sc, ""); 1353 return 0; 1354 } 1355 1356 void 1357 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1358 { 1359 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1360 1361 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1362 if (txq == NULL) { 1363 GE_FUNC_EXIT(sc, ""); 1364 return; 1365 } 1366 1367 if (!flush) { 1368 GE_FUNC_EXIT(sc, ""); 1369 return; 1370 } 1371 1372 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1373 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1374 free(txq, M_DEVBUF); 1375 sc->sc_txq[txprio] = NULL; 1376 GE_FUNC_EXIT(sc, "-F"); 1377 } 1378 1379 void 1380 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1381 { 1382 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1383 1384 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1385 1386 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1387 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1388 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1389 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1390 1391 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1392 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1393 1394 sc->sc_ec.ec_if.if_timer = 0; 1395 GE_FUNC_EXIT(sc, ""); 1396 } 1397 1398 int 1400 gfe_intr(void *arg) 1401 { 1402 struct gfe_softc * const sc = arg; 1403 uint32_t cause; 1404 uint32_t intrmask = sc->sc_intrmask; 1405 int claim = 0; 1406 int cnt; 1407 1408 GE_FUNC_ENTER(sc, "gfe_intr"); 1409 1410 for (cnt = 0; cnt < 4; cnt++) { 1411 if (sc->sc_intrmask != intrmask) { 1412 sc->sc_intrmask = intrmask; 1413 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1414 } 1415 cause = GE_READ(sc, EICR); 1416 cause &= sc->sc_intrmask; 1417 GE_DPRINTF(sc, (".%#x", cause)); 1418 if (cause == 0) 1419 break; 1420 1421 claim = 1; 1422 1423 GE_WRITE(sc, EICR, ~cause); 1424 #ifndef GE_NORX 1425 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1426 intrmask = gfe_rx_process(sc, cause, intrmask); 1427 #endif 1428 1429 #ifndef GE_NOTX 1430 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1431 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1432 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1433 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1434 #endif 1435 if (cause & ETH_IR_MIIPhySTC) { 1436 sc->sc_flags |= GE_PHYSTSCHG; 1437 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1438 } 1439 } 1440 1441 GE_FUNC_EXIT(sc, ""); 1442 return claim; 1443 } 1444 1445 int 1447 gfe_mii_mediachange (struct ifnet *ifp) 1448 { 1449 struct gfe_softc *sc = ifp->if_softc; 1450 1451 if (ifp->if_flags & IFF_UP) 1452 mii_mediachg(&sc->sc_mii); 1453 1454 return (0); 1455 } 1456 void 1457 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1458 { 1459 struct gfe_softc *sc = ifp->if_softc; 1460 1461 if (sc->sc_flags & GE_PHYSTSCHG) { 1462 sc->sc_flags &= ~GE_PHYSTSCHG; 1463 mii_pollstat(&sc->sc_mii); 1464 } 1465 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1466 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1467 } 1468 1469 int 1470 gfe_mii_read (struct device *self, int phy, int reg) 1471 { 1472 return gt_mii_read(self, self->dv_parent, phy, reg); 1473 } 1474 1475 void 1476 gfe_mii_write (struct device *self, int phy, int reg, int value) 1477 { 1478 gt_mii_write(self, self->dv_parent, phy, reg, value); 1479 } 1480 1481 void 1482 gfe_mii_statchg (struct device *self) 1483 { 1484 /* struct gfe_softc *sc = (struct gfe_softc *) self; */ 1485 /* do nothing? */ 1486 } 1487 1488 int 1490 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1491 { 1492 int error = 0; 1493 GE_FUNC_ENTER(sc, "gfe_whack"); 1494 1495 switch (op) { 1496 case GE_WHACK_RESTART: 1497 #ifndef GE_NOTX 1498 gfe_tx_stop(sc, op); 1499 #endif 1500 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1501 /* FALLTHROUGH */ 1502 case GE_WHACK_START: 1503 #ifndef GE_NOHASH 1504 if (error == 0 && sc->sc_hashtable == NULL) { 1505 error = gfe_hash_alloc(sc); 1506 if (error) 1507 break; 1508 } 1509 if (op != GE_WHACK_RESTART) 1510 gfe_hash_fill(sc); 1511 #endif 1512 #ifndef GE_NORX 1513 if (op != GE_WHACK_RESTART) { 1514 error = gfe_rx_prime(sc); 1515 if (error) 1516 break; 1517 } 1518 #endif 1519 #ifndef GE_NOTX 1520 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1521 if (error) 1522 break; 1523 #endif 1524 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1525 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1526 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1527 GE_WRITE(sc, EICR, 0); 1528 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1529 #ifndef GE_NOHASH 1530 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1531 #endif 1532 #ifndef GE_NORX 1533 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1534 sc->sc_flags |= GE_RXACTIVE; 1535 #endif 1536 /* FALLTHROUGH */ 1537 case GE_WHACK_CHANGE: 1538 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1539 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1540 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1541 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1542 gfe_ifstart(&sc->sc_ec.ec_if); 1543 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1544 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1545 GE_FUNC_EXIT(sc, ""); 1546 return error; 1547 case GE_WHACK_STOP: 1548 break; 1549 } 1550 1551 #ifdef GE_DEBUG 1552 if (error) 1553 GE_DPRINTF(sc, (" failed: %d\n", error)); 1554 #endif 1555 GE_WRITE(sc, EPCR, sc->sc_pcr); 1556 GE_WRITE(sc, EIMR, 0); 1557 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1558 #ifndef GE_NOTX 1559 gfe_tx_stop(sc, GE_WHACK_STOP); 1560 #endif 1561 #ifndef GE_NORX 1562 gfe_rx_stop(sc, GE_WHACK_STOP); 1563 #endif 1564 #ifndef GE_NOHASH 1565 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1566 sc->sc_hashtable = NULL; 1567 #endif 1568 1569 GE_FUNC_EXIT(sc, ""); 1570 return error; 1571 } 1572 1573 int 1575 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1576 { 1577 uint32_t w0, add0, add1; 1578 uint32_t result; 1579 1580 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1581 add0 = ((uint32_t) eaddr[5] << 0) | 1582 ((uint32_t) eaddr[4] << 8) | 1583 ((uint32_t) eaddr[3] << 16); 1584 1585 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1586 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1587 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1588 1589 add1 = ((uint32_t) eaddr[2] << 0) | 1590 ((uint32_t) eaddr[1] << 8) | 1591 ((uint32_t) eaddr[0] << 16); 1592 1593 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1594 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1595 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1596 1597 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1598 /* 1599 * hashResult is the 15 bits Hash entry address. 1600 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1601 * MAC address, by nibble swapping in every byte (i.e MAC address 1602 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1603 */ 1604 1605 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1606 /* 1607 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1608 * 1609 * hashFunc0 calculates the hashResult in the following manner: 1610 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1611 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1612 */ 1613 result = (add0 & 3) | ((add0 >> 6) & ~3); 1614 result ^= (add0 >> 15) ^ (add1 >> 0); 1615 result &= 0x1ff; 1616 /* 1617 * hashResult[14:9] = ethernetADD[7:2] 1618 */ 1619 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1620 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1621 } else { 1622 #define TRIBITFLIP 073516240 /* yes its in octal */ 1623 /* 1624 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1625 * 1626 * hashFunc1 calculates the hashResult in the following manner: 1627 * hashResult[08:00] = ethernetADD[06:14] 1628 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1629 */ 1630 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1631 /* 1632 * Now bitswap those 9 bits 1633 */ 1634 result = 0; 1635 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1636 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1637 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1638 1639 /* 1640 * hashResult[14:09] = ethernetADD[00:05] 1641 */ 1642 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1643 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1644 GE_DPRINTF(sc, ("1(%#x)", result)); 1645 } 1646 GE_FUNC_EXIT(sc, ""); 1647 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1648 } 1649 1650 int 1651 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1652 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1653 { 1654 uint64_t he; 1655 uint64_t *maybe_he_p = NULL; 1656 int limit; 1657 int hash; 1658 int maybe_hash = 0; 1659 1660 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1661 1662 hash = gfe_hash_compute(sc, eaddr); 1663 1664 if (sc->sc_hashtable == NULL) { 1665 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1666 __LINE__); 1667 } 1668 1669 /* 1670 * Assume we are going to insert so create the hash entry we 1671 * are going to insert. We also use it to match entries we 1672 * will be removing. 1673 */ 1674 he = ((uint64_t) eaddr[5] << 43) | 1675 ((uint64_t) eaddr[4] << 35) | 1676 ((uint64_t) eaddr[3] << 27) | 1677 ((uint64_t) eaddr[2] << 19) | 1678 ((uint64_t) eaddr[1] << 11) | 1679 ((uint64_t) eaddr[0] << 3) | 1680 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1681 1682 /* 1683 * The GT will search upto 12 entries for a hit, so we must mimic that. 1684 */ 1685 hash &= sc->sc_hashmask / sizeof(he); 1686 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1687 /* 1688 * Does the GT wrap at the end, stop at the, or overrun the 1689 * end? Assume it wraps for now. Stash a copy of the 1690 * current hash entry. 1691 */ 1692 uint64_t *he_p = &sc->sc_hashtable[hash]; 1693 uint64_t thishe = *he_p; 1694 1695 /* 1696 * If the hash entry isn't valid, that break the chain. And 1697 * this entry a good candidate for reuse. 1698 */ 1699 if ((thishe & HSH_V) == 0) { 1700 maybe_he_p = he_p; 1701 break; 1702 } 1703 1704 /* 1705 * If the hash entry has the same address we are looking for 1706 * then ... if we are removing and the skip bit is set, its 1707 * already been removed. if are adding and the skip bit is 1708 * clear, then its already added. In either return EBUSY 1709 * indicating the op has already been done. Otherwise flip 1710 * the skip bit and return 0. 1711 */ 1712 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1713 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1714 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1715 return EBUSY; 1716 *he_p = thishe ^ HSH_S; 1717 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1718 hash * sizeof(he), sizeof(he), 1719 BUS_DMASYNC_PREWRITE); 1720 GE_FUNC_EXIT(sc, "^"); 1721 return 0; 1722 } 1723 1724 /* 1725 * If we haven't found a slot for the entry and this entry 1726 * is currently being skipped, return this entry. 1727 */ 1728 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1729 maybe_he_p = he_p; 1730 maybe_hash = hash; 1731 } 1732 1733 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1734 } 1735 1736 /* 1737 * If we got here, then there was no entry to remove. 1738 */ 1739 if (op == GE_HASH_REMOVE) { 1740 GE_FUNC_EXIT(sc, "?"); 1741 return ENOENT; 1742 } 1743 1744 /* 1745 * If we couldn't find a slot, return an error. 1746 */ 1747 if (maybe_he_p == NULL) { 1748 GE_FUNC_EXIT(sc, "!"); 1749 return ENOSPC; 1750 } 1751 1752 /* Update the entry. 1753 */ 1754 *maybe_he_p = he; 1755 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1756 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1757 GE_FUNC_EXIT(sc, "+"); 1758 return 0; 1759 } 1760 1761 int 1762 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1763 { 1764 struct gfe_softc * const sc = ec->ec_if.if_softc; 1765 int error; 1766 enum gfe_hash_op op; 1767 enum gfe_rxprio prio; 1768 1769 GE_FUNC_ENTER(sc, "hash_multichg"); 1770 /* 1771 * Is this a wildcard entry? If so and its being removed, recompute. 1772 */ 1773 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1774 if (cmd == SIOCDELMULTI) { 1775 GE_FUNC_EXIT(sc, ""); 1776 return ENETRESET; 1777 } 1778 1779 /* 1780 * Switch in 1781 */ 1782 sc->sc_flags |= GE_ALLMULTI; 1783 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1784 sc->sc_pcr |= ETH_EPCR_PM; 1785 GE_WRITE(sc, EPCR, sc->sc_pcr); 1786 GE_FUNC_EXIT(sc, ""); 1787 return 0; 1788 } 1789 GE_FUNC_EXIT(sc, ""); 1790 return ENETRESET; 1791 } 1792 1793 prio = GE_RXPRIO_MEDLO; 1794 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1795 1796 if (sc->sc_hashtable == NULL) { 1797 GE_FUNC_EXIT(sc, ""); 1798 return 0; 1799 } 1800 1801 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1802 if (error == EBUSY) { 1803 printf("%s: multichg: tried to %s %s again\n", 1804 sc->sc_dev.dv_xname, 1805 cmd == SIOCDELMULTI ? "remove" : "add", 1806 ether_sprintf(enm->enm_addrlo)); 1807 GE_FUNC_EXIT(sc, ""); 1808 return 0; 1809 } 1810 1811 if (error == ENOENT) { 1812 printf("%s: multichg: failed to remove %s: not in table\n", 1813 sc->sc_dev.dv_xname, 1814 ether_sprintf(enm->enm_addrlo)); 1815 GE_FUNC_EXIT(sc, ""); 1816 return 0; 1817 } 1818 1819 if (error == ENOSPC) { 1820 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1821 sc->sc_dev.dv_xname, 1822 ether_sprintf(enm->enm_addrlo)); 1823 GE_FUNC_EXIT(sc, ""); 1824 return ENETRESET; 1825 } 1826 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1827 sc->sc_dev.dv_xname, 1828 cmd == SIOCDELMULTI ? "remove" : "add", 1829 ether_sprintf(enm->enm_addrlo))); 1830 GE_FUNC_EXIT(sc, ""); 1831 return 0; 1832 } 1833 1834 int 1835 gfe_hash_fill(struct gfe_softc *sc) 1836 { 1837 struct ether_multistep step; 1838 struct ether_multi *enm; 1839 int error; 1840 1841 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1842 1843 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1844 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1845 if (error) 1846 GE_FUNC_EXIT(sc, "!"); 1847 return error; 1848 1849 sc->sc_flags &= ~GE_ALLMULTI; 1850 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1851 sc->sc_pcr &= ~ETH_EPCR_PM; 1852 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1853 while (enm != NULL) { 1854 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1855 sc->sc_flags |= GE_ALLMULTI; 1856 sc->sc_pcr |= ETH_EPCR_PM; 1857 } else { 1858 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1859 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1860 if (error == ENOSPC) 1861 break; 1862 } 1863 ETHER_NEXT_MULTI(step, enm); 1864 } 1865 1866 GE_FUNC_EXIT(sc, ""); 1867 return error; 1868 } 1869 1870 int 1871 gfe_hash_alloc(struct gfe_softc *sc) 1872 { 1873 int error; 1874 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1875 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1876 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1877 BUS_DMA_NOCACHE); 1878 if (error) { 1879 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1880 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1881 GE_FUNC_EXIT(sc, ""); 1882 return error; 1883 } 1884 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1885 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1886 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1887 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1888 GE_FUNC_EXIT(sc, ""); 1889 return 0; 1890 } 1891
Indexes created Tue Sep 30 11:09:46 GMT 2025