if_gfe.c revision 1.9
1 /* $NetBSD: if_gfe.c,v 1.9 2003/04/30 18:31:30 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Allegro Networks, Inc., and Wasabi Systems, Inc. 19 * 4. The name of Allegro Networks, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 23 * or promote products derived from this software without specific prior 24 * written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * if_gfe.c -- GT ethernet MAC driver 42 */ 43 44 #include "opt_inet.h" 45 #include "bpfilter.h" 46 47 #include <sys/param.h> 48 #include <sys/types.h> 49 #include <sys/inttypes.h> 50 #include <sys/queue.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <sys/callout.h> 55 #include <sys/device.h> 56 #include <sys/errno.h> 57 #include <sys/ioctl.h> 58 #include <sys/mbuf.h> 59 #include <sys/socket.h> 60 61 #include <machine/bus.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_ether.h> 66 #include <net/if_media.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/if_inarp.h> 71 #endif 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <dev/mii/miivar.h> 77 78 #include <dev/marvell/gtintrreg.h> 79 #include <dev/marvell/gtethreg.h> 80 81 #include <dev/marvell/gtvar.h> 82 #include <dev/marvell/if_gfevar.h> 83 84 #define GE_READ(sc, reg) \ 85 bus_space_read_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg) 86 #define GE_WRITE(sc, reg, v) \ 87 bus_space_write_4((sc)->sc_gt_memt, (sc)->sc_memh, ETH__ ## reg, (v)) 88 89 #define GE_DEBUG 90 #if 0 91 #define GE_NOHASH 92 #define GE_NORX 93 #endif 94 95 #ifdef GE_DEBUG 96 #define GE_DPRINTF(sc, a) do \ 97 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \ 98 printf a; \ 99 while (0) 100 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func)) 101 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]")) 102 #else 103 #define GE_DPRINTF(sc, a) do { } while (0) 104 #define GE_FUNC_ENTER(sc, func) do { } while (0) 105 #define GE_FUNC_EXIT(sc, str) do { } while (0) 106 #endif 107 enum gfe_whack_op { 108 GE_WHACK_START, GE_WHACK_RESTART, 109 GE_WHACK_CHANGE, GE_WHACK_STOP 110 }; 111 112 enum gfe_hash_op { 113 GE_HASH_ADD, GE_HASH_REMOVE, 114 }; 115 116 #if 1 117 #define htogt32(a) htobe32(a) 118 #define gt32toh(a) be32toh(a) 119 #else 120 #define htogt32(a) htole32(a) 121 #define gt32toh(a) le32toh(a) 122 #endif 123 124 #define GE_RXDSYNC(sc, rxq, n, ops) \ 125 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \ 126 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \ 127 (ops)) 128 #define GE_RXDPRESYNC(sc, rxq, n) \ 129 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 130 #define GE_RXDPOSTSYNC(sc, rxq, n) \ 131 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 132 133 #define GE_TXDSYNC(sc, txq, n, ops) \ 134 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \ 135 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \ 136 (ops)) 137 #define GE_TXDPRESYNC(sc, txq, n) \ 138 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE) 139 #define GE_TXDPOSTSYNC(sc, txq, n) \ 140 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE) 141 142 #define STATIC 143 144 STATIC int gfe_match (struct device *, struct cfdata *, void *); 145 STATIC void gfe_attach (struct device *, struct device *, void *); 146 147 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int, 148 size_t, int); 149 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *); 150 151 STATIC int gfe_ifioctl (struct ifnet *, u_long, caddr_t); 152 STATIC void gfe_ifstart (struct ifnet *); 153 STATIC void gfe_ifwatchdog (struct ifnet *); 154 155 STATIC int gfe_mii_mediachange (struct ifnet *); 156 STATIC void gfe_mii_mediastatus (struct ifnet *, struct ifmediareq *); 157 STATIC int gfe_mii_read (struct device *, int, int); 158 STATIC void gfe_mii_write (struct device *, int, int, int); 159 STATIC void gfe_mii_statchg (struct device *); 160 161 STATIC void gfe_tick(void *arg); 162 163 STATIC void gfe_tx_restart(void *); 164 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio); 165 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t); 166 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int); 167 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio); 168 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op); 169 170 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio); 171 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio); 172 STATIC int gfe_rx_prime(struct gfe_softc *); 173 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t); 174 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio); 175 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op); 176 177 STATIC int gfe_intr(void *); 178 179 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op); 180 181 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]); 182 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op, 183 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]); 184 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *, 185 u_long); 186 STATIC int gfe_hash_fill(struct gfe_softc *); 187 STATIC int gfe_hash_alloc(struct gfe_softc *); 188 189 /* Linkup to the rest of the kernel */ 190 CFATTACH_DECL(gfe, sizeof(struct gfe_softc), 191 gfe_match, gfe_attach, NULL, NULL); 192 193 extern struct cfdriver gfe_cd; 194 195 int 196 gfe_match(struct device *parent, struct cfdata *cf, void *aux) 197 { 198 struct gt_softc *gt = (struct gt_softc *) parent; 199 struct gt_attach_args *ga = aux; 200 uint8_t enaddr[6]; 201 202 if (!GT_ETHEROK(gt, ga, &gfe_cd)) 203 return 0; 204 205 if (gtget_macaddr(gt, ga->ga_unit, enaddr) < 0) 206 return 0; 207 208 if (enaddr[0] == 0 && enaddr[1] == 0 && enaddr[2] == 0 && 209 enaddr[3] == 0 && enaddr[4] == 0 && enaddr[5] == 0) 210 return 0; 211 212 return 1; 213 } 214 215 /* 216 * Attach this instance, and then all the sub-devices 217 */ 218 void 219 gfe_attach(struct device *parent, struct device *self, void *aux) 220 { 221 struct gt_attach_args * const ga = aux; 222 struct gt_softc * const gt = (struct gt_softc *) parent; 223 struct gfe_softc * const sc = (struct gfe_softc *) self; 224 struct ifnet * const ifp = &sc->sc_ec.ec_if; 225 uint32_t data; 226 uint8_t enaddr[6]; 227 int phyaddr; 228 uint32_t sdcr; 229 230 GT_ETHERFOUND(gt, ga); 231 232 sc->sc_gt_memt = ga->ga_memt; 233 sc->sc_gt_memh = ga->ga_memh; 234 sc->sc_dmat = ga->ga_dmat; 235 sc->sc_macno = ga->ga_unit; 236 237 if (bus_space_subregion(sc->sc_gt_memt, sc->sc_gt_memh, 238 ETH_BASE(sc->sc_macno), ETH_SIZE, &sc->sc_memh)) { 239 aprint_error(": failed to map registers\n"); 240 } 241 242 callout_init(&sc->sc_co); 243 244 data = bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, ETH_EPAR); 245 phyaddr = ETH_EPAR_PhyAD_GET(data, sc->sc_macno); 246 247 gtget_macaddr(gt, sc->sc_macno, enaddr); 248 249 sc->sc_pcr = GE_READ(sc, EPCR); 250 sc->sc_pcxr = GE_READ(sc, EPCXR); 251 sc->sc_intrmask = GE_READ(sc, EIMR) | ETH_IR_MIIPhySTC; 252 253 aprint_normal(": address %s", ether_sprintf(enaddr)); 254 255 #if defined(DEBUG) 256 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 257 #endif 258 259 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override; 260 if (sc->sc_dev.dv_cfdata->cf_flags & 1) { 261 aprint_normal(", phy %d (rmii)", phyaddr); 262 sc->sc_pcxr |= ETH_EPCXR_RMIIEn; 263 } else { 264 aprint_normal(", phy %d (mii)", phyaddr); 265 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn; 266 } 267 sc->sc_pcxr &= ~(3 << 14); 268 sc->sc_pcxr |= (ETH_EPCXR_MFL_1536 << 14); 269 270 if (sc->sc_pcr & ETH_EPCR_EN) { 271 int tries = 1000; 272 /* 273 * Abort transmitter and receiver and wait for them to quiese 274 */ 275 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR|ETH_ESDCMR_AT); 276 do { 277 delay(100); 278 } while (tries-- > 0 && (GE_READ(sc, ESDCMR) & (ETH_ESDCMR_AR|ETH_ESDCMR_AT))); 279 } 280 281 sc->sc_pcr &= ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF); 282 283 #if defined(DEBUG) 284 aprint_normal(", pcr %#x, pcxr %#x", sc->sc_pcr, sc->sc_pcxr); 285 #endif 286 287 /* 288 * Now turn off the GT. If it didn't quiese, too ***ing bad. 289 */ 290 GE_WRITE(sc, EPCR, sc->sc_pcr); 291 GE_WRITE(sc, EIMR, sc->sc_intrmask); 292 sdcr = GE_READ(sc, ESDCR); 293 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4); 294 sdcr |= ETH_ESDCR_RIFB; 295 GE_WRITE(sc, ESDCR, sdcr); 296 sc->sc_max_frame_length = 1536; 297 298 aprint_normal("\n"); 299 sc->sc_mii.mii_ifp = ifp; 300 sc->sc_mii.mii_readreg = gfe_mii_read; 301 sc->sc_mii.mii_writereg = gfe_mii_write; 302 sc->sc_mii.mii_statchg = gfe_mii_statchg; 303 304 ifmedia_init(&sc->sc_mii.mii_media, 0, gfe_mii_mediachange, 305 gfe_mii_mediastatus); 306 307 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, phyaddr, 308 MII_OFFSET_ANY, MIIF_NOISOLATE); 309 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 310 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 311 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 312 } else { 313 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 314 } 315 316 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 317 ifp->if_softc = sc; 318 /* ifp->if_mowner = &sc->sc_mowner; */ 319 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 320 #if 0 321 ifp->if_flags |= IFF_DEBUG; 322 #endif 323 ifp->if_ioctl = gfe_ifioctl; 324 ifp->if_start = gfe_ifstart; 325 ifp->if_watchdog = gfe_ifwatchdog; 326 327 if_attach(ifp); 328 ether_ifattach(ifp, enaddr); 329 #if NBPFILTER > 0 330 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 331 #endif 332 #if NRND > 0 333 rnd_attach_source(&sc->sc_rnd_source, self->dv_xname, RND_TYPE_NET, 0); 334 #endif 335 intr_establish(IRQ_ETH0 + sc->sc_macno, IST_LEVEL, IPL_NET, 336 gfe_intr, sc); 337 } 338 339 int 340 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs, 341 size_t size, int flags) 342 { 343 int error = 0; 344 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc"); 345 gdm->gdm_size = size; 346 gdm->gdm_maxsegs = maxsegs; 347 348 #if 0 349 flags |= BUS_DMA_NOCACHE; 350 #endif 351 352 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE, 353 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs, 354 BUS_DMA_NOWAIT); 355 if (error) 356 goto fail; 357 358 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs, 359 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT); 360 if (error) 361 goto fail; 362 363 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs, 364 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &gdm->gdm_map); 365 if (error) 366 goto fail; 367 368 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva, 369 gdm->gdm_size, NULL, BUS_DMA_NOWAIT); 370 if (error) 371 goto fail; 372 373 /* invalidate from cache */ 374 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size, 375 BUS_DMASYNC_PREREAD); 376 fail: 377 if (error) { 378 gfe_dmamem_free(sc, gdm); 379 GE_DPRINTF(sc, (":err=%d", error)); 380 } 381 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x", 382 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs, 383 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len)); 384 GE_FUNC_EXIT(sc, ""); 385 return error; 386 } 387 388 void 389 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm) 390 { 391 GE_FUNC_ENTER(sc, "gfe_dmamem_free"); 392 if (gdm->gdm_map) 393 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map); 394 if (gdm->gdm_kva) 395 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size); 396 if (gdm->gdm_nsegs > 0) 397 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs); 398 gdm->gdm_map = NULL; 399 gdm->gdm_kva = NULL; 400 gdm->gdm_nsegs = 0; 401 GE_FUNC_EXIT(sc, ""); 402 } 403 404 int 405 gfe_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 406 { 407 struct gfe_softc * const sc = ifp->if_softc; 408 struct ifreq *ifr = (struct ifreq *) data; 409 struct ifaddr *ifa = (struct ifaddr *) data; 410 int s, error = 0; 411 412 GE_FUNC_ENTER(sc, "gfe_ifioctl"); 413 s = splnet(); 414 415 switch (cmd) { 416 case SIOCSIFADDR: 417 ifp->if_flags |= IFF_UP; 418 switch (ifa->ifa_addr->sa_family) { 419 #ifdef INET 420 case AF_INET: 421 error = gfe_whack(sc, GE_WHACK_START); 422 if (error == 0) 423 arp_ifinit(ifp, ifa); 424 break; 425 #endif 426 default: 427 error = gfe_whack(sc, GE_WHACK_START); 428 break; 429 } 430 break; 431 432 case SIOCSIFFLAGS: 433 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 434 case IFF_UP|IFF_RUNNING:/* active->active, update */ 435 error = gfe_whack(sc, GE_WHACK_CHANGE); 436 break; 437 case IFF_RUNNING: /* not up, so we stop */ 438 error = gfe_whack(sc, GE_WHACK_STOP); 439 break; 440 case IFF_UP: /* not running, so we start */ 441 error = gfe_whack(sc, GE_WHACK_START); 442 break; 443 case 0: /* idle->idle: do nothing */ 444 break; 445 } 446 break; 447 448 case SIOCADDMULTI: 449 case SIOCDELMULTI: 450 error = (cmd == SIOCADDMULTI) 451 ? ether_addmulti(ifr, &sc->sc_ec) 452 : ether_delmulti(ifr, &sc->sc_ec); 453 if (error == ENETRESET) { 454 if (ifp->if_flags & IFF_RUNNING) 455 error = gfe_whack(sc, GE_WHACK_CHANGE); 456 else 457 error = 0; 458 } 459 break; 460 461 case SIOCSIFMTU: 462 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) { 463 error = EINVAL; 464 break; 465 } 466 ifp->if_mtu = ifr->ifr_mtu; 467 break; 468 469 case SIOCSIFMEDIA: 470 case SIOCGIFMEDIA: 471 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 472 break; 473 474 default: 475 error = EINVAL; 476 break; 477 } 478 splx(s); 479 GE_FUNC_EXIT(sc, ""); 480 return error; 481 } 482 483 void 484 gfe_ifstart(struct ifnet *ifp) 485 { 486 struct gfe_softc * const sc = ifp->if_softc; 487 struct mbuf *m; 488 489 GE_FUNC_ENTER(sc, "gfe_ifstart"); 490 491 if ((ifp->if_flags & IFF_RUNNING) == 0) { 492 GE_FUNC_EXIT(sc, "$"); 493 return; 494 } 495 496 if (sc->sc_txq[GE_TXPRIO_HI] == NULL) { 497 ifp->if_flags |= IFF_OACTIVE; 498 #if defined(DEBUG) || defined(DIAGNOSTIC) 499 printf("%s: ifstart: txq not yet created\n", ifp->if_xname); 500 #endif 501 GE_FUNC_EXIT(sc, ""); 502 return; 503 } 504 505 for (;;) { 506 IF_DEQUEUE(&ifp->if_snd, m); 507 if (m == NULL) { 508 ifp->if_flags &= ~IFF_OACTIVE; 509 GE_FUNC_EXIT(sc, ""); 510 return; 511 } 512 513 /* 514 * No space in the pending queue? try later. 515 */ 516 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq)) 517 break; 518 519 /* 520 * Try to enqueue a mbuf to the device. If that fails, we 521 * can always try to map the next mbuf. 522 */ 523 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI]->txq_pendq, m); 524 GE_DPRINTF(sc, (">")); 525 #ifndef GE_NOTX 526 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI); 527 #endif 528 } 529 530 /* 531 * Attempt to queue the mbuf for send failed. 532 */ 533 IF_PREPEND(&ifp->if_snd, m); 534 ifp->if_flags |= IFF_OACTIVE; 535 GE_FUNC_EXIT(sc, "%%"); 536 } 537 538 void 539 gfe_ifwatchdog(struct ifnet *ifp) 540 { 541 struct gfe_softc * const sc = ifp->if_softc; 542 struct gfe_txqueue *txq; 543 544 GE_FUNC_ENTER(sc, "gfe_ifwatchdog"); 545 printf("%s: device timeout", sc->sc_dev.dv_xname); 546 if ((txq = sc->sc_txq[GE_TXPRIO_HI]) != NULL) { 547 uint32_t curtxdnum = (bus_space_read_4(sc->sc_gt_memt, sc->sc_gt_memh, txq->txq_ectdp) - txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]); 548 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 549 GE_TXDPOSTSYNC(sc, txq, curtxdnum); 550 printf(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ", 551 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts, 552 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts, 553 GE_READ(sc, EICR)); 554 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 555 GE_TXDPRESYNC(sc, txq, curtxdnum); 556 } 557 printf("\n"); 558 ifp->if_oerrors++; 559 (void) gfe_whack(sc, GE_WHACK_RESTART); 560 GE_FUNC_EXIT(sc, ""); 561 } 562 563 int 565 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio) 566 { 567 struct gfe_rxqueue *rxq; 568 volatile struct gt_eth_desc *rxd; 569 const bus_dma_segment_t *ds; 570 int error; 571 int idx; 572 bus_addr_t nxtaddr; 573 bus_size_t boff; 574 575 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc"); 576 GE_DPRINTF(sc, ("(%d)", rxprio)); 577 if (sc->sc_rxq[rxprio] != NULL) { 578 GE_FUNC_EXIT(sc, ""); 579 return 0; 580 } 581 582 rxq = (struct gfe_rxqueue *) malloc(sizeof(*rxq), M_DEVBUF, M_NOWAIT); 583 if (rxq == NULL) { 584 GE_FUNC_EXIT(sc, "!"); 585 return ENOMEM; 586 } 587 588 memset(rxq, 0, sizeof(*rxq)); 589 590 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1, 591 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE); 592 if (error) { 593 free(rxq, M_DEVBUF); 594 GE_FUNC_EXIT(sc, "!!"); 595 return error; 596 } 597 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS, 598 GE_RXBUF_MEMSIZE, 0); 599 if (error) { 600 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 601 free(rxq, M_DEVBUF); 602 GE_FUNC_EXIT(sc, "!!!"); 603 return error; 604 } 605 606 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_TXMEM_SIZE); 607 608 sc->sc_rxq[rxprio] = rxq; 609 rxq->rxq_descs = 610 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva; 611 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr; 612 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva; 613 rxq->rxq_fi = 0; 614 rxq->rxq_active = GE_RXDESC_MAX; 615 for (idx = 0, rxd = rxq->rxq_descs, 616 boff = 0, ds = rxq->rxq_buf_mem.gdm_map->dm_segs, 617 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd); 618 idx < GE_RXDESC_MAX; 619 idx++, rxd++, nxtaddr += sizeof(*rxd)) { 620 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16); 621 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 622 rxd->ed_bufptr = htogt32(ds->ds_addr + boff); 623 /* 624 * update the nxtptr to point to the next txd. 625 */ 626 if (idx == GE_RXDESC_MAX - 1) 627 nxtaddr = rxq->rxq_desc_busaddr; 628 rxd->ed_nxtptr = htogt32(nxtaddr); 629 boff += GE_RXBUF_SIZE; 630 if (boff == ds->ds_len) { 631 ds++; 632 boff = 0; 633 } 634 } 635 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0, 636 rxq->rxq_desc_mem.gdm_map->dm_mapsize, 637 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 638 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0, 639 rxq->rxq_buf_mem.gdm_map->dm_mapsize, 640 BUS_DMASYNC_PREREAD); 641 642 rxq->rxq_intrbits = ETH_IR_RxBuffer|ETH_IR_RxError; 643 switch (rxprio) { 644 case GE_RXPRIO_HI: 645 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3|ETH_IR_RxError_3; 646 rxq->rxq_efrdp = ETH_EFRDP3(sc->sc_macno); 647 rxq->rxq_ecrdp = ETH_ECRDP3(sc->sc_macno); 648 break; 649 case GE_RXPRIO_MEDHI: 650 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2|ETH_IR_RxError_2; 651 rxq->rxq_efrdp = ETH_EFRDP2(sc->sc_macno); 652 rxq->rxq_ecrdp = ETH_ECRDP2(sc->sc_macno); 653 break; 654 case GE_RXPRIO_MEDLO: 655 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1|ETH_IR_RxError_1; 656 rxq->rxq_efrdp = ETH_EFRDP1(sc->sc_macno); 657 rxq->rxq_ecrdp = ETH_ECRDP1(sc->sc_macno); 658 break; 659 case GE_RXPRIO_LO: 660 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0|ETH_IR_RxError_0; 661 rxq->rxq_efrdp = ETH_EFRDP0(sc->sc_macno); 662 rxq->rxq_ecrdp = ETH_ECRDP0(sc->sc_macno); 663 break; 664 } 665 GE_FUNC_EXIT(sc, ""); 666 return error; 667 } 668 669 void 670 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio) 671 { 672 struct ifnet * const ifp = &sc->sc_ec.ec_if; 673 struct gfe_rxqueue * const rxq = sc->sc_rxq[rxprio]; 674 struct mbuf *m = rxq->rxq_curpkt; 675 676 GE_FUNC_ENTER(sc, "gfe_rx_get"); 677 GE_DPRINTF(sc, ("(%d)", rxprio)); 678 679 while (rxq->rxq_active > 0) { 680 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi]; 681 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi]; 682 const struct ether_header *eh; 683 unsigned int cmdsts; 684 size_t buflen; 685 686 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi); 687 cmdsts = gt32toh(rxd->ed_cmdsts); 688 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts)); 689 rxq->rxq_cmdsts = cmdsts; 690 /* 691 * Sometimes the GE "forgets" to reset the ownership bit. 692 * But if the length has been rewritten, the packet is ours 693 * so pretend the O bit is set. 694 */ 695 buflen = gt32toh(rxd->ed_lencnt) & 0xffff; 696 if ((cmdsts & RX_CMD_O) && buflen == 0) { 697 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 698 break; 699 } 700 701 /* 702 * If this is not a single buffer packet with no errors 703 * or for some reason it's bigger than our frame size, 704 * ignore it and go to the next packet. 705 */ 706 if ((cmdsts & (RX_CMD_F|RX_CMD_L|RX_STS_ES)) != 707 (RX_CMD_F|RX_CMD_L) || 708 buflen > sc->sc_max_frame_length) { 709 GE_DPRINTF(sc, ("!")); 710 --rxq->rxq_active; 711 ifp->if_ipackets++; 712 ifp->if_ierrors++; 713 goto give_it_back; 714 } 715 716 if (m == NULL) { 717 MGETHDR(m, M_DONTWAIT, MT_DATA); 718 if (m == NULL) { 719 GE_DPRINTF(sc, ("?")); 720 break; 721 } 722 } 723 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) { 724 MCLGET(m, M_DONTWAIT); 725 if ((m->m_flags & M_EXT) == 0) { 726 GE_DPRINTF(sc, ("?")); 727 break; 728 } 729 } 730 m->m_data += 2; 731 m->m_len = 0; 732 m->m_pkthdr.len = 0; 733 m->m_pkthdr.rcvif = ifp; 734 rxq->rxq_cmdsts = cmdsts; 735 --rxq->rxq_active; 736 737 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 738 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD); 739 740 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0); 741 memcpy(m->m_data + m->m_len, rxb->rb_data, buflen); 742 m->m_len = buflen; 743 m->m_pkthdr.len = buflen; 744 m->m_flags |= M_HASFCS; 745 746 ifp->if_ipackets++; 747 #if NBPFILTER > 0 748 if (ifp->if_bpf != NULL) 749 bpf_mtap(ifp->if_bpf, m); 750 #endif 751 752 eh = (const struct ether_header *) m->m_data; 753 if ((ifp->if_flags & IFF_PROMISC) || 754 (rxq->rxq_cmdsts & RX_STS_M) == 0 || 755 (rxq->rxq_cmdsts & RX_STS_HE) || 756 (eh->ether_dhost[0] & 1) != 0 || 757 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 758 ETHER_ADDR_LEN) == 0) { 759 (*ifp->if_input)(ifp, m); 760 m = NULL; 761 GE_DPRINTF(sc, (">")); 762 } else { 763 m->m_len = 0; 764 m->m_pkthdr.len = 0; 765 GE_DPRINTF(sc, ("+")); 766 } 767 rxq->rxq_cmdsts = 0; 768 769 give_it_back: 770 rxd->ed_lencnt &= ~0xffff; /* zero out length */ 771 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI); 772 #if 0 773 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", 774 rxq->rxq_fi, 775 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1], 776 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3])); 777 #endif 778 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi); 779 if (++rxq->rxq_fi == GE_RXDESC_MAX) 780 rxq->rxq_fi = 0; 781 rxq->rxq_active++; 782 } 783 rxq->rxq_curpkt = m; 784 GE_FUNC_EXIT(sc, ""); 785 } 786 787 uint32_t 788 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask) 789 { 790 struct ifnet * const ifp = &sc->sc_ec.ec_if; 791 struct gfe_rxqueue *rxq; 792 uint32_t rxbits; 793 #define RXPRIO_DECODER 0xffffaa50 794 GE_FUNC_ENTER(sc, "gfe_rx_process"); 795 796 rxbits = ETH_IR_RxBuffer_GET(cause); 797 while (rxbits) { 798 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 799 GE_DPRINTF(sc, ("%1x", rxbits)); 800 rxbits &= ~(1 << rxprio); 801 gfe_rx_get(sc, rxprio); 802 } 803 804 rxbits = ETH_IR_RxError_GET(cause); 805 while (rxbits) { 806 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3; 807 uint32_t masks[(GE_RXDESC_MAX + 31) / 32]; 808 int idx; 809 rxbits &= ~(1 << rxprio); 810 rxq = sc->sc_rxq[rxprio]; 811 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits); 812 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits); 813 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) { 814 sc->sc_tickflags |= GE_TICK_RX_RESTART; 815 callout_reset(&sc->sc_co, 1, gfe_tick, sc); 816 } 817 ifp->if_ierrors++; 818 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n", 819 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi)); 820 memset(masks, 0, sizeof(masks)); 821 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 822 0, rxq->rxq_desc_mem.gdm_size, 823 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 824 for (idx = 0; idx < GE_RXDESC_MAX; idx++) { 825 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx]; 826 827 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts)) 828 masks[idx/32] |= 1 << (idx & 31); 829 } 830 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 831 0, rxq->rxq_desc_mem.gdm_size, 832 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 833 #if defined(DEBUG) 834 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n", 835 sc->sc_dev.dv_xname, rxprio, rxq->rxq_fi, 836 rxq->rxq_cmdsts, masks[0], masks[1]); 837 #endif 838 } 839 if ((intrmask & ETH_IR_RxBits) == 0) 840 intrmask &= ~(ETH_IR_RxBuffer|ETH_IR_RxError); 841 842 GE_FUNC_EXIT(sc, ""); 843 return intrmask; 844 } 845 846 int 847 gfe_rx_prime(struct gfe_softc *sc) 848 { 849 struct gfe_rxqueue *rxq; 850 int error; 851 852 GE_FUNC_ENTER(sc, "gfe_rx_prime"); 853 854 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI); 855 if (error) 856 goto bail; 857 rxq = sc->sc_rxq[GE_RXPRIO_HI]; 858 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 859 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 860 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 861 } 862 sc->sc_intrmask |= rxq->rxq_intrbits; 863 864 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI); 865 if (error) 866 goto bail; 867 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 868 rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 869 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 870 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 871 sc->sc_intrmask |= rxq->rxq_intrbits; 872 } 873 874 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO); 875 if (error) 876 goto bail; 877 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 878 rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 879 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 880 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 881 sc->sc_intrmask |= rxq->rxq_intrbits; 882 } 883 884 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO); 885 if (error) 886 goto bail; 887 if ((sc->sc_flags & GE_RXACTIVE) == 0) { 888 rxq = sc->sc_rxq[GE_RXPRIO_LO]; 889 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 890 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 891 sc->sc_intrmask |= rxq->rxq_intrbits; 892 } 893 894 bail: 895 GE_FUNC_EXIT(sc, ""); 896 return error; 897 } 898 899 void 900 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio) 901 { 902 struct gfe_rxqueue *rxq = sc->sc_rxq[rxprio]; 903 GE_FUNC_ENTER(sc, "gfe_rx_cleanup"); 904 if (rxq == NULL) { 905 GE_FUNC_EXIT(sc, ""); 906 return; 907 } 908 909 if (rxq->rxq_curpkt) 910 m_freem(rxq->rxq_curpkt); 911 gfe_dmamem_free(sc, &rxq->rxq_desc_mem); 912 gfe_dmamem_free(sc, &rxq->rxq_buf_mem); 913 free(rxq, M_DEVBUF); 914 sc->sc_rxq[rxprio] = NULL; 915 GE_FUNC_EXIT(sc, ""); 916 } 917 918 void 919 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 920 { 921 GE_FUNC_ENTER(sc, "gfe_rx_stop"); 922 sc->sc_flags &= ~GE_RXACTIVE; 923 sc->sc_idlemask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 924 sc->sc_intrmask &= ~(ETH_IR_RxBits|ETH_IR_RxBuffer|ETH_IR_RxError); 925 GE_WRITE(sc, EIMR, sc->sc_intrmask); 926 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_AR); 927 do { 928 delay(10); 929 } while (GE_READ(sc, ESDCMR) & ETH_ESDCMR_AR); 930 gfe_rx_cleanup(sc, GE_RXPRIO_HI); 931 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI); 932 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO); 933 gfe_rx_cleanup(sc, GE_RXPRIO_LO); 934 GE_FUNC_EXIT(sc, ""); 935 } 936 937 void 939 gfe_tick(void *arg) 940 { 941 struct gfe_softc * const sc = arg; 942 uint32_t intrmask; 943 unsigned int tickflags; 944 int s; 945 946 GE_FUNC_ENTER(sc, "gfe_tick"); 947 948 s = splnet(); 949 950 tickflags = sc->sc_tickflags; 951 sc->sc_tickflags = 0; 952 intrmask = sc->sc_intrmask; 953 if (tickflags & GE_TICK_TX_IFSTART) 954 gfe_ifstart(&sc->sc_ec.ec_if); 955 if (tickflags & GE_TICK_RX_RESTART) { 956 intrmask |= sc->sc_idlemask; 957 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3|ETH_IR_RxError_3)) { 958 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_HI]; 959 rxq->rxq_fi = 0; 960 GE_WRITE(sc, EFRDP3, rxq->rxq_desc_busaddr); 961 GE_WRITE(sc, ECRDP3, rxq->rxq_desc_busaddr); 962 } 963 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2|ETH_IR_RxError_2)) { 964 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDHI]; 965 rxq->rxq_fi = 0; 966 GE_WRITE(sc, EFRDP2, rxq->rxq_desc_busaddr); 967 GE_WRITE(sc, ECRDP2, rxq->rxq_desc_busaddr); 968 } 969 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1|ETH_IR_RxError_1)) { 970 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_MEDLO]; 971 rxq->rxq_fi = 0; 972 GE_WRITE(sc, EFRDP1, rxq->rxq_desc_busaddr); 973 GE_WRITE(sc, ECRDP1, rxq->rxq_desc_busaddr); 974 } 975 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0|ETH_IR_RxError_0)) { 976 struct gfe_rxqueue *rxq = sc->sc_rxq[GE_RXPRIO_LO]; 977 rxq->rxq_fi = 0; 978 GE_WRITE(sc, EFRDP0, rxq->rxq_desc_busaddr); 979 GE_WRITE(sc, ECRDP0, rxq->rxq_desc_busaddr); 980 } 981 sc->sc_idlemask = 0; 982 } 983 if (intrmask != sc->sc_intrmask) { 984 sc->sc_intrmask = intrmask; 985 GE_WRITE(sc, EIMR, sc->sc_intrmask); 986 } 987 gfe_intr(sc); 988 splx(s); 989 990 GE_FUNC_EXIT(sc, ""); 991 } 992 993 int 994 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio) 995 { 996 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 997 struct ifnet * const ifp = &sc->sc_ec.ec_if; 998 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 999 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo]; 1000 uint32_t intrmask = sc->sc_intrmask; 1001 size_t buflen; 1002 struct mbuf *m; 1003 1004 GE_FUNC_ENTER(sc, "gfe_tx_enqueue"); 1005 1006 /* 1007 * Anything in the pending queue to enqueue? if not, punt. 1008 * otherwise grab its dmamap. 1009 */ 1010 if ((m = txq->txq_pendq.ifq_head) == NULL) { 1011 GE_FUNC_EXIT(sc, "-"); 1012 return 0; 1013 } 1014 1015 /* 1016 * Have we [over]consumed our limit of descriptors? 1017 * Do we have enough free descriptors? 1018 */ 1019 if (GE_TXDESC_MAX == txq->txq_nactive + 2) { 1020 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi]; 1021 uint32_t cmdsts; 1022 size_t pktlen; 1023 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1024 cmdsts = gt32toh(txd2->ed_cmdsts); 1025 if (cmdsts & TX_CMD_O) { 1026 int nextin; 1027 /* 1028 * Sometime the Discovery forgets to update the 1029 * last descriptor. See if we own the descriptor 1030 * after it (since we know we've turned that to 1031 * the discovery and if we owned it, the Discovery 1032 * gave it back). If we do, we know the Discovery 1033 * gave back this one but forgot to mark it as ours. 1034 */ 1035 nextin = txq->txq_fi + 1; 1036 if (nextin == GE_TXDESC_MAX) 1037 nextin = 0; 1038 GE_TXDPOSTSYNC(sc, txq, nextin); 1039 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1040 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1041 GE_TXDPRESYNC(sc, txq, nextin); 1042 GE_FUNC_EXIT(sc, "@"); 1043 return 0; 1044 } 1045 #ifdef DEBUG 1046 printf("%s: txenqueue: transmitter resynced at %d\n", 1047 sc->sc_dev.dv_xname, txq->txq_fi); 1048 #endif 1049 } 1050 if (++txq->txq_fi == GE_TXDESC_MAX) 1051 txq->txq_fi = 0; 1052 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr; 1053 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff; 1054 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1055 txq->txq_nactive--; 1056 1057 /* statistics */ 1058 ifp->if_opackets++; 1059 if (cmdsts & TX_STS_ES) 1060 ifp->if_oerrors++; 1061 GE_DPRINTF(sc, ("%%")); 1062 } 1063 1064 buflen = roundup(m->m_pkthdr.len, dcache_line_size); 1065 1066 /* 1067 * If this packet would wrap around the end of the buffer, reset back 1068 * to the beginning. 1069 */ 1070 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) { 1071 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr; 1072 txq->txq_outptr = 0; 1073 } 1074 1075 /* 1076 * Make sure the output packet doesn't run over the beginning of 1077 * what we've already given the GT. 1078 */ 1079 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr && 1080 txq->txq_outptr + buflen > txq->txq_inptr) { 1081 intrmask |= txq->txq_intrbits & 1082 (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow); 1083 if (sc->sc_intrmask != intrmask) { 1084 sc->sc_intrmask = intrmask; 1085 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1086 } 1087 GE_FUNC_EXIT(sc, "#"); 1088 return 0; 1089 } 1090 1091 /* 1092 * The end-of-list descriptor we put on last time is the starting point 1093 * for this packet. The GT is supposed to terminate list processing on 1094 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor 1095 * must terminate the list. 1096 */ 1097 intrmask = sc->sc_intrmask; 1098 1099 m_copydata(m, 0, m->m_pkthdr.len, 1100 txq->txq_buf_mem.gdm_kva + txq->txq_outptr); 1101 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1102 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE); 1103 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr); 1104 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16); 1105 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1106 1107 /* 1108 * Request a buffer interrupt every 2/3 of the way thru the transmit 1109 * buffer. 1110 */ 1111 txq->txq_ei_gapcount += buflen; 1112 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) { 1113 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST|TX_CMD_EI); 1114 txq->txq_ei_gapcount = 0; 1115 } else { 1116 txd->ed_cmdsts = htogt32(TX_CMD_FIRST|TX_CMD_LAST); 1117 } 1118 #if 0 1119 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo, 1120 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1121 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1122 #endif 1123 GE_TXDPRESYNC(sc, txq, txq->txq_lo); 1124 1125 txq->txq_outptr += buflen; 1126 /* 1127 * Tell the SDMA engine to "Fetch!" 1128 */ 1129 GE_WRITE(sc, ESDCMR, 1130 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH|ETH_ESDCMR_TXDL)); 1131 1132 GE_DPRINTF(sc, ("(%d)", txq->txq_lo)); 1133 1134 /* 1135 * Update the last out appropriately. 1136 */ 1137 txq->txq_nactive++; 1138 if (++txq->txq_lo == GE_TXDESC_MAX) 1139 txq->txq_lo = 0; 1140 1141 /* 1142 * Move mbuf from the pending queue to the snd queue. 1143 */ 1144 IF_DEQUEUE(&txq->txq_pendq, m); 1145 #if NBPFILTER > 0 1146 if (ifp->if_bpf != NULL) 1147 bpf_mtap(ifp->if_bpf, m); 1148 #endif 1149 m_freem(m); 1150 ifp->if_flags &= ~IFF_OACTIVE; 1151 1152 /* 1153 * Since we have put an item into the packet queue, we now want 1154 * an interrupt when the transmit queue finishes processing the 1155 * list. But only update the mask if needs changing. 1156 */ 1157 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow); 1158 if (sc->sc_intrmask != intrmask) { 1159 sc->sc_intrmask = intrmask; 1160 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1161 } 1162 if (ifp->if_timer == 0) 1163 ifp->if_timer = 5; 1164 GE_FUNC_EXIT(sc, "*"); 1165 return 1; 1166 } 1167 1168 uint32_t 1169 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask) 1170 { 1171 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1172 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1173 1174 GE_FUNC_ENTER(sc, "gfe_tx_done"); 1175 1176 if (txq == NULL) { 1177 GE_FUNC_EXIT(sc, ""); 1178 return intrmask; 1179 } 1180 1181 while (txq->txq_nactive > 0) { 1182 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 1183 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi]; 1184 uint32_t cmdsts; 1185 size_t pktlen; 1186 1187 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi); 1188 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) { 1189 int nextin; 1190 1191 if (txq->txq_nactive == 1) { 1192 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1193 GE_FUNC_EXIT(sc, ""); 1194 return intrmask; 1195 } 1196 /* 1197 * Sometimes the Discovery forgets to update the 1198 * ownership bit in the descriptor. See if we own the 1199 * descriptor after it (since we know we've turned 1200 * that to the Discovery and if we own it now then the 1201 * Discovery gave it back). If we do, we know the 1202 * Discovery gave back this one but forgot to mark it 1203 * as ours. 1204 */ 1205 nextin = txq->txq_fi + 1; 1206 if (nextin == GE_TXDESC_MAX) 1207 nextin = 0; 1208 GE_TXDPOSTSYNC(sc, txq, nextin); 1209 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) { 1210 GE_TXDPRESYNC(sc, txq, txq->txq_fi); 1211 GE_TXDPRESYNC(sc, txq, nextin); 1212 GE_FUNC_EXIT(sc, ""); 1213 return intrmask; 1214 } 1215 #ifdef DEBUG 1216 printf("%s: txdone: transmitter resynced at %d\n", 1217 sc->sc_dev.dv_xname, txq->txq_fi); 1218 #endif 1219 } 1220 #if 0 1221 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)", 1222 txq->txq_lo, 1223 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1], 1224 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3])); 1225 #endif 1226 GE_DPRINTF(sc, ("(%d)", txq->txq_fi)); 1227 if (++txq->txq_fi == GE_TXDESC_MAX) 1228 txq->txq_fi = 0; 1229 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr; 1230 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff; 1231 txq->txq_inptr += roundup(pktlen, dcache_line_size); 1232 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map, 1233 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE); 1234 1235 /* statistics */ 1236 ifp->if_opackets++; 1237 if (cmdsts & TX_STS_ES) 1238 ifp->if_oerrors++; 1239 1240 /* txd->ed_bufptr = 0; */ 1241 1242 ifp->if_timer = 5; 1243 --txq->txq_nactive; 1244 } 1245 if (txq->txq_nactive != 0) 1246 panic("%s: transmit fifo%d empty but active count (%d) > 0!", 1247 sc->sc_dev.dv_xname, txprio, txq->txq_nactive); 1248 ifp->if_timer = 0; 1249 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxEndHigh|ETH_IR_TxEndLow)); 1250 intrmask &= ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh|ETH_IR_TxBufferLow)); 1251 GE_FUNC_EXIT(sc, ""); 1252 return intrmask; 1253 } 1254 1255 int 1256 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio) 1257 { 1258 struct gfe_txqueue *txq; 1259 volatile struct gt_eth_desc *txd; 1260 unsigned int i; 1261 bus_addr_t addr; 1262 1263 GE_FUNC_ENTER(sc, "gfe_tx_start"); 1264 1265 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1266 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1267 1268 if ((txq = sc->sc_txq[txprio]) == NULL) { 1269 int error; 1270 txq = (struct gfe_txqueue *) malloc(sizeof(*txq), 1271 M_DEVBUF, M_NOWAIT); 1272 if (txq == NULL) { 1273 GE_FUNC_EXIT(sc, ""); 1274 return ENOMEM; 1275 } 1276 memset(txq, 0, sizeof(*txq)); 1277 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1, 1278 GE_TXMEM_SIZE, BUS_DMA_NOCACHE); 1279 if (error) { 1280 free(txq, M_DEVBUF); 1281 GE_FUNC_EXIT(sc, ""); 1282 return error; 1283 } 1284 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, 1285 GE_TXBUF_SIZE, 0); 1286 if (error) { 1287 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1288 free(txq, M_DEVBUF); 1289 GE_FUNC_EXIT(sc, ""); 1290 return error; 1291 } 1292 sc->sc_txq[txprio] = txq; 1293 } 1294 1295 txq->txq_descs = 1296 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva; 1297 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr; 1298 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr; 1299 1300 txq->txq_pendq.ifq_maxlen = 10; 1301 txq->txq_ei_gapcount = 0; 1302 txq->txq_nactive = 0; 1303 txq->txq_fi = 0; 1304 txq->txq_lo = 0; 1305 txq->txq_inptr = GE_TXBUF_SIZE; 1306 txq->txq_outptr = 0; 1307 for (i = 0, txd = txq->txq_descs, 1308 addr = txq->txq_desc_busaddr + sizeof(*txd); 1309 i < GE_TXDESC_MAX - 1; 1310 i++, txd++, addr += sizeof(*txd)) { 1311 /* 1312 * update the nxtptr to point to the next txd. 1313 */ 1314 txd->ed_cmdsts = 0; 1315 txd->ed_nxtptr = htogt32(addr); 1316 } 1317 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr = 1318 htogt32(txq->txq_desc_busaddr); 1319 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0, 1320 GE_TXMEM_SIZE, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1321 1322 switch (txprio) { 1323 case GE_TXPRIO_HI: 1324 txq->txq_intrbits = ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh; 1325 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH; 1326 txq->txq_epsrbits = ETH_EPSR_TxHigh; 1327 txq->txq_ectdp = ETH_ECTDP1(sc->sc_macno); 1328 GE_WRITE(sc, ECTDP1, txq->txq_desc_busaddr); 1329 break; 1330 1331 case GE_TXPRIO_LO: 1332 txq->txq_intrbits = ETH_IR_TxEndLow|ETH_IR_TxBufferLow; 1333 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL; 1334 txq->txq_epsrbits = ETH_EPSR_TxLow; 1335 txq->txq_ectdp = ETH_ECTDP0(sc->sc_macno); 1336 GE_WRITE(sc, ECTDP0, txq->txq_desc_busaddr); 1337 break; 1338 1339 case GE_TXPRIO_NONE: 1340 break; 1341 } 1342 #if 0 1343 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp)); 1344 gt_write(sc->sc_dev.dv_parent, txq->txq_ectdp, txq->txq_desc_busaddr); 1345 GE_DPRINTF(sc, (")")); 1346 #endif 1347 1348 /* 1349 * If we are restarting, there may be packets in the pending queue 1350 * waiting to be enqueued. Try enqueuing packets from both priority 1351 * queues until the pending queue is empty or there no room for them 1352 * on the device. 1353 */ 1354 while (gfe_tx_enqueue(sc, txprio)) 1355 continue; 1356 1357 GE_FUNC_EXIT(sc, ""); 1358 return 0; 1359 } 1360 1361 void 1362 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush) 1363 { 1364 struct gfe_txqueue * const txq = sc->sc_txq[txprio]; 1365 1366 GE_FUNC_ENTER(sc, "gfe_tx_cleanup"); 1367 if (txq == NULL) { 1368 GE_FUNC_EXIT(sc, ""); 1369 return; 1370 } 1371 1372 if (!flush) { 1373 GE_FUNC_EXIT(sc, ""); 1374 return; 1375 } 1376 1377 gfe_dmamem_free(sc, &txq->txq_desc_mem); 1378 gfe_dmamem_free(sc, &txq->txq_buf_mem); 1379 free(txq, M_DEVBUF); 1380 sc->sc_txq[txprio] = NULL; 1381 GE_FUNC_EXIT(sc, "-F"); 1382 } 1383 1384 void 1385 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op) 1386 { 1387 GE_FUNC_ENTER(sc, "gfe_tx_stop"); 1388 1389 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_STDH|ETH_ESDCMR_STDL); 1390 1391 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask); 1392 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask); 1393 sc->sc_intrmask &= ~(ETH_IR_TxEndHigh|ETH_IR_TxBufferHigh| 1394 ETH_IR_TxEndLow |ETH_IR_TxBufferLow); 1395 1396 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP); 1397 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP); 1398 1399 sc->sc_ec.ec_if.if_timer = 0; 1400 GE_FUNC_EXIT(sc, ""); 1401 } 1402 1403 int 1405 gfe_intr(void *arg) 1406 { 1407 struct gfe_softc * const sc = arg; 1408 uint32_t cause; 1409 uint32_t intrmask = sc->sc_intrmask; 1410 int claim = 0; 1411 int cnt; 1412 1413 GE_FUNC_ENTER(sc, "gfe_intr"); 1414 1415 for (cnt = 0; cnt < 4; cnt++) { 1416 if (sc->sc_intrmask != intrmask) { 1417 sc->sc_intrmask = intrmask; 1418 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1419 } 1420 cause = GE_READ(sc, EICR); 1421 cause &= sc->sc_intrmask; 1422 GE_DPRINTF(sc, (".%#x", cause)); 1423 if (cause == 0) 1424 break; 1425 1426 claim = 1; 1427 1428 GE_WRITE(sc, EICR, ~cause); 1429 #ifndef GE_NORX 1430 if (cause & (ETH_IR_RxBuffer|ETH_IR_RxError)) 1431 intrmask = gfe_rx_process(sc, cause, intrmask); 1432 #endif 1433 1434 #ifndef GE_NOTX 1435 if (cause & (ETH_IR_TxBufferHigh|ETH_IR_TxEndHigh)) 1436 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask); 1437 if (cause & (ETH_IR_TxBufferLow|ETH_IR_TxEndLow)) 1438 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask); 1439 #endif 1440 if (cause & ETH_IR_MIIPhySTC) { 1441 sc->sc_flags |= GE_PHYSTSCHG; 1442 /* intrmask &= ~ETH_IR_MIIPhySTC; */ 1443 } 1444 } 1445 1446 GE_FUNC_EXIT(sc, ""); 1447 return claim; 1448 } 1449 1450 int 1452 gfe_mii_mediachange (struct ifnet *ifp) 1453 { 1454 struct gfe_softc *sc = ifp->if_softc; 1455 1456 if (ifp->if_flags & IFF_UP) 1457 mii_mediachg(&sc->sc_mii); 1458 1459 return (0); 1460 } 1461 void 1462 gfe_mii_mediastatus (struct ifnet *ifp, struct ifmediareq *ifmr) 1463 { 1464 struct gfe_softc *sc = ifp->if_softc; 1465 1466 if (sc->sc_flags & GE_PHYSTSCHG) { 1467 sc->sc_flags &= ~GE_PHYSTSCHG; 1468 mii_pollstat(&sc->sc_mii); 1469 } 1470 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1471 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1472 } 1473 1474 int 1475 gfe_mii_read (struct device *self, int phy, int reg) 1476 { 1477 return gt_mii_read(self, self->dv_parent, phy, reg); 1478 } 1479 1480 void 1481 gfe_mii_write (struct device *self, int phy, int reg, int value) 1482 { 1483 gt_mii_write(self, self->dv_parent, phy, reg, value); 1484 } 1485 1486 void 1487 gfe_mii_statchg (struct device *self) 1488 { 1489 /* struct gfe_softc *sc = (struct gfe_softc *) self; */ 1490 /* do nothing? */ 1491 } 1492 1493 int 1495 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op) 1496 { 1497 int error = 0; 1498 GE_FUNC_ENTER(sc, "gfe_whack"); 1499 1500 switch (op) { 1501 case GE_WHACK_RESTART: 1502 #ifndef GE_NOTX 1503 gfe_tx_stop(sc, op); 1504 #endif 1505 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */ 1506 /* FALLTHROUGH */ 1507 case GE_WHACK_START: 1508 #ifndef GE_NOHASH 1509 if (error == 0 && sc->sc_hashtable == NULL) { 1510 error = gfe_hash_alloc(sc); 1511 if (error) 1512 break; 1513 } 1514 if (op != GE_WHACK_RESTART) 1515 gfe_hash_fill(sc); 1516 #endif 1517 #ifndef GE_NORX 1518 if (op != GE_WHACK_RESTART) { 1519 error = gfe_rx_prime(sc); 1520 if (error) 1521 break; 1522 } 1523 #endif 1524 #ifndef GE_NOTX 1525 error = gfe_tx_start(sc, GE_TXPRIO_HI); 1526 if (error) 1527 break; 1528 #endif 1529 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING; 1530 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1531 GE_WRITE(sc, EPCXR, sc->sc_pcxr); 1532 GE_WRITE(sc, EICR, 0); 1533 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1534 #ifndef GE_NOHASH 1535 GE_WRITE(sc, EHTPR, sc->sc_hash_mem.gdm_map->dm_segs->ds_addr); 1536 #endif 1537 #ifndef GE_NORX 1538 GE_WRITE(sc, ESDCMR, ETH_ESDCMR_ERD); 1539 sc->sc_flags |= GE_RXACTIVE; 1540 #endif 1541 /* FALLTHROUGH */ 1542 case GE_WHACK_CHANGE: 1543 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)", 1544 GE_READ(sc, EPCR), GE_READ(sc, EIMR))); 1545 GE_WRITE(sc, EPCR, sc->sc_pcr | ETH_EPCR_EN); 1546 GE_WRITE(sc, EIMR, sc->sc_intrmask); 1547 gfe_ifstart(&sc->sc_ec.ec_if); 1548 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)", 1549 GE_READ(sc, ECTDP0), GE_READ(sc, ECTDP1))); 1550 GE_FUNC_EXIT(sc, ""); 1551 return error; 1552 case GE_WHACK_STOP: 1553 break; 1554 } 1555 1556 #ifdef GE_DEBUG 1557 if (error) 1558 GE_DPRINTF(sc, (" failed: %d\n", error)); 1559 #endif 1560 GE_WRITE(sc, EPCR, sc->sc_pcr); 1561 GE_WRITE(sc, EIMR, 0); 1562 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; 1563 #ifndef GE_NOTX 1564 gfe_tx_stop(sc, GE_WHACK_STOP); 1565 #endif 1566 #ifndef GE_NORX 1567 gfe_rx_stop(sc, GE_WHACK_STOP); 1568 #endif 1569 #ifndef GE_NOHASH 1570 gfe_dmamem_free(sc, &sc->sc_hash_mem); 1571 sc->sc_hashtable = NULL; 1572 #endif 1573 1574 GE_FUNC_EXIT(sc, ""); 1575 return error; 1576 } 1577 1578 int 1580 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN]) 1581 { 1582 uint32_t w0, add0, add1; 1583 uint32_t result; 1584 1585 GE_FUNC_ENTER(sc, "gfe_hash_compute"); 1586 add0 = ((uint32_t) eaddr[5] << 0) | 1587 ((uint32_t) eaddr[4] << 8) | 1588 ((uint32_t) eaddr[3] << 16); 1589 1590 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4); 1591 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2); 1592 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1); 1593 1594 add1 = ((uint32_t) eaddr[2] << 0) | 1595 ((uint32_t) eaddr[1] << 8) | 1596 ((uint32_t) eaddr[0] << 16); 1597 1598 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4); 1599 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2); 1600 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1); 1601 1602 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr))); 1603 /* 1604 * hashResult is the 15 bits Hash entry address. 1605 * ethernetADD is a 48 bit number, which is derived from the Ethernet 1606 * MAC address, by nibble swapping in every byte (i.e MAC address 1607 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb). 1608 */ 1609 1610 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) { 1611 /* 1612 * hashResult[14:0] = hashFunc0(ethernetADD[47:0]) 1613 * 1614 * hashFunc0 calculates the hashResult in the following manner: 1615 * hashResult[ 8:0] = ethernetADD[14:8,1,0] 1616 * XOR ethernetADD[23:15] XOR ethernetADD[32:24] 1617 */ 1618 result = (add0 & 3) | ((add0 >> 6) & ~3); 1619 result ^= (add0 >> 15) ^ (add1 >> 0); 1620 result &= 0x1ff; 1621 /* 1622 * hashResult[14:9] = ethernetADD[7:2] 1623 */ 1624 result |= (add0 & ~3) << 7; /* excess bits will be masked */ 1625 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff)); 1626 } else { 1627 #define TRIBITFLIP 073516240 /* yes its in octal */ 1628 /* 1629 * hashResult[14:0] = hashFunc1(ethernetADD[47:0]) 1630 * 1631 * hashFunc1 calculates the hashResult in the following manner: 1632 * hashResult[08:00] = ethernetADD[06:14] 1633 * XOR ethernetADD[15:23] XOR ethernetADD[24:32] 1634 */ 1635 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff; 1636 /* 1637 * Now bitswap those 9 bits 1638 */ 1639 result = 0; 1640 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6; 1641 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3; 1642 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0; 1643 1644 /* 1645 * hashResult[14:09] = ethernetADD[00:05] 1646 */ 1647 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12; 1648 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9; 1649 GE_DPRINTF(sc, ("1(%#x)", result)); 1650 } 1651 GE_FUNC_EXIT(sc, ""); 1652 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff); 1653 } 1654 1655 int 1656 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op, 1657 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN]) 1658 { 1659 uint64_t he; 1660 uint64_t *maybe_he_p = NULL; 1661 int limit; 1662 int hash; 1663 int maybe_hash = 0; 1664 1665 GE_FUNC_ENTER(sc, "gfe_hash_entry_op"); 1666 1667 hash = gfe_hash_compute(sc, eaddr); 1668 1669 if (sc->sc_hashtable == NULL) { 1670 panic("%s:%d: hashtable == NULL!", sc->sc_dev.dv_xname, 1671 __LINE__); 1672 } 1673 1674 /* 1675 * Assume we are going to insert so create the hash entry we 1676 * are going to insert. We also use it to match entries we 1677 * will be removing. 1678 */ 1679 he = ((uint64_t) eaddr[5] << 43) | 1680 ((uint64_t) eaddr[4] << 35) | 1681 ((uint64_t) eaddr[3] << 27) | 1682 ((uint64_t) eaddr[2] << 19) | 1683 ((uint64_t) eaddr[1] << 11) | 1684 ((uint64_t) eaddr[0] << 3) | 1685 HSH_PRIO_INS(prio) | HSH_V | HSH_R; 1686 1687 /* 1688 * The GT will search upto 12 entries for a hit, so we must mimic that. 1689 */ 1690 hash &= sc->sc_hashmask / sizeof(he); 1691 for (limit = HSH_LIMIT; limit > 0 ; --limit) { 1692 /* 1693 * Does the GT wrap at the end, stop at the, or overrun the 1694 * end? Assume it wraps for now. Stash a copy of the 1695 * current hash entry. 1696 */ 1697 uint64_t *he_p = &sc->sc_hashtable[hash]; 1698 uint64_t thishe = *he_p; 1699 1700 /* 1701 * If the hash entry isn't valid, that break the chain. And 1702 * this entry a good candidate for reuse. 1703 */ 1704 if ((thishe & HSH_V) == 0) { 1705 maybe_he_p = he_p; 1706 break; 1707 } 1708 1709 /* 1710 * If the hash entry has the same address we are looking for 1711 * then ... if we are removing and the skip bit is set, its 1712 * already been removed. if are adding and the skip bit is 1713 * clear, then its already added. In either return EBUSY 1714 * indicating the op has already been done. Otherwise flip 1715 * the skip bit and return 0. 1716 */ 1717 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) { 1718 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) || 1719 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0)) 1720 return EBUSY; 1721 *he_p = thishe ^ HSH_S; 1722 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1723 hash * sizeof(he), sizeof(he), 1724 BUS_DMASYNC_PREWRITE); 1725 GE_FUNC_EXIT(sc, "^"); 1726 return 0; 1727 } 1728 1729 /* 1730 * If we haven't found a slot for the entry and this entry 1731 * is currently being skipped, return this entry. 1732 */ 1733 if (maybe_he_p == NULL && (thishe & HSH_S)) { 1734 maybe_he_p = he_p; 1735 maybe_hash = hash; 1736 } 1737 1738 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he)); 1739 } 1740 1741 /* 1742 * If we got here, then there was no entry to remove. 1743 */ 1744 if (op == GE_HASH_REMOVE) { 1745 GE_FUNC_EXIT(sc, "?"); 1746 return ENOENT; 1747 } 1748 1749 /* 1750 * If we couldn't find a slot, return an error. 1751 */ 1752 if (maybe_he_p == NULL) { 1753 GE_FUNC_EXIT(sc, "!"); 1754 return ENOSPC; 1755 } 1756 1757 /* Update the entry. 1758 */ 1759 *maybe_he_p = he; 1760 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1761 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE); 1762 GE_FUNC_EXIT(sc, "+"); 1763 return 0; 1764 } 1765 1766 int 1767 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm, u_long cmd) 1768 { 1769 struct gfe_softc * const sc = ec->ec_if.if_softc; 1770 int error; 1771 enum gfe_hash_op op; 1772 enum gfe_rxprio prio; 1773 1774 GE_FUNC_ENTER(sc, "hash_multichg"); 1775 /* 1776 * Is this a wildcard entry? If so and its being removed, recompute. 1777 */ 1778 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { 1779 if (cmd == SIOCDELMULTI) { 1780 GE_FUNC_EXIT(sc, ""); 1781 return ENETRESET; 1782 } 1783 1784 /* 1785 * Switch in 1786 */ 1787 sc->sc_flags |= GE_ALLMULTI; 1788 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) { 1789 sc->sc_pcr |= ETH_EPCR_PM; 1790 GE_WRITE(sc, EPCR, sc->sc_pcr); 1791 GE_FUNC_EXIT(sc, ""); 1792 return 0; 1793 } 1794 GE_FUNC_EXIT(sc, ""); 1795 return ENETRESET; 1796 } 1797 1798 prio = GE_RXPRIO_MEDLO; 1799 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD); 1800 1801 if (sc->sc_hashtable == NULL) { 1802 GE_FUNC_EXIT(sc, ""); 1803 return 0; 1804 } 1805 1806 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo); 1807 if (error == EBUSY) { 1808 printf("%s: multichg: tried to %s %s again\n", 1809 sc->sc_dev.dv_xname, 1810 cmd == SIOCDELMULTI ? "remove" : "add", 1811 ether_sprintf(enm->enm_addrlo)); 1812 GE_FUNC_EXIT(sc, ""); 1813 return 0; 1814 } 1815 1816 if (error == ENOENT) { 1817 printf("%s: multichg: failed to remove %s: not in table\n", 1818 sc->sc_dev.dv_xname, 1819 ether_sprintf(enm->enm_addrlo)); 1820 GE_FUNC_EXIT(sc, ""); 1821 return 0; 1822 } 1823 1824 if (error == ENOSPC) { 1825 printf("%s: multichg: failed to add %s: no space; regenerating table\n", 1826 sc->sc_dev.dv_xname, 1827 ether_sprintf(enm->enm_addrlo)); 1828 GE_FUNC_EXIT(sc, ""); 1829 return ENETRESET; 1830 } 1831 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n", 1832 sc->sc_dev.dv_xname, 1833 cmd == SIOCDELMULTI ? "remove" : "add", 1834 ether_sprintf(enm->enm_addrlo))); 1835 GE_FUNC_EXIT(sc, ""); 1836 return 0; 1837 } 1838 1839 int 1840 gfe_hash_fill(struct gfe_softc *sc) 1841 { 1842 struct ether_multistep step; 1843 struct ether_multi *enm; 1844 int error; 1845 1846 GE_FUNC_ENTER(sc, "gfe_hash_fill"); 1847 1848 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI, 1849 LLADDR(sc->sc_ec.ec_if.if_sadl)); 1850 if (error) 1851 GE_FUNC_EXIT(sc, "!"); 1852 return error; 1853 1854 sc->sc_flags &= ~GE_ALLMULTI; 1855 if ((sc->sc_ec.ec_if.if_flags & IFF_PROMISC) == 0) 1856 sc->sc_pcr &= ~ETH_EPCR_PM; 1857 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 1858 while (enm != NULL) { 1859 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1860 sc->sc_flags |= GE_ALLMULTI; 1861 sc->sc_pcr |= ETH_EPCR_PM; 1862 } else { 1863 error = gfe_hash_entry_op(sc, GE_HASH_ADD, 1864 GE_RXPRIO_MEDLO, enm->enm_addrlo); 1865 if (error == ENOSPC) 1866 break; 1867 } 1868 ETHER_NEXT_MULTI(step, enm); 1869 } 1870 1871 GE_FUNC_EXIT(sc, ""); 1872 return error; 1873 } 1874 1875 int 1876 gfe_hash_alloc(struct gfe_softc *sc) 1877 { 1878 int error; 1879 GE_FUNC_ENTER(sc, "gfe_hash_alloc"); 1880 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1; 1881 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1, 1882 BUS_DMA_NOCACHE); 1883 if (error) { 1884 printf("%s: failed to allocate %d bytes for hash table: %d\n", 1885 sc->sc_dev.dv_xname, sc->sc_hashmask + 1, error); 1886 GE_FUNC_EXIT(sc, ""); 1887 return error; 1888 } 1889 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva; 1890 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1); 1891 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map, 1892 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE); 1893 GE_FUNC_EXIT(sc, ""); 1894 return 0; 1895 } 1896
Indexes created Tue Sep 30 11:09:46 GMT 2025