if_mvgbe.c revision 1.15
1 /* $NetBSD: if_mvgbe.c,v 1.15 2011/11/19 22:51:23 tls Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.15 2011/11/19 22:51:23 tls Exp $"); 29 30 #include "rnd.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/endian.h> 36 #include <sys/errno.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 #include <sys/sockio.h> 40 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 #include <dev/marvell/mvgbereg.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/in_systm.h> 51 #include <netinet/ip.h> 52 53 #include <net/bpf.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include "locators.h" 62 63 /* #define MVGBE_DEBUG 3 */ 64 #ifdef MVGBE_DEBUG 65 #define DPRINTF(x) if (mvgbe_debug) printf x 66 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 67 int mvgbe_debug = MVGBE_DEBUG; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n,x) 71 #endif 72 73 74 #define MVGBE_READ(sc, reg) \ 75 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 76 #define MVGBE_WRITE(sc, reg, val) \ 77 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 78 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 79 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 80 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 81 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 82 83 #define MVGBE_TX_RING_CNT 256 84 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 85 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 86 #define MVGBE_RX_RING_CNT 256 87 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 88 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 89 90 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 91 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 92 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 93 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 94 95 #define MVGBE_JSLOTS 384 /* XXXX */ 96 #define MVGBE_JLEN ((MVGBE_MRU + MVGBE_RXBUF_ALIGN)&~MVGBE_RXBUF_MASK) 97 #define MVGBE_NTXSEG 30 98 #define MVGBE_JPAGESZ PAGE_SIZE 99 #define MVGBE_RESID \ 100 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 101 #define MVGBE_JMEM \ 102 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 103 104 #define MVGBE_TX_RING_ADDR(sc, i) \ 105 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 106 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 107 108 #define MVGBE_RX_RING_ADDR(sc, i) \ 109 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 110 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 111 112 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 113 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 114 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 115 116 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 117 do { \ 118 int __x, __n; \ 119 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 120 \ 121 __x = (x); \ 122 __n = (n); \ 123 \ 124 /* If it will wrap around, sync to the end of the ring. */ \ 125 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 126 bus_dmamap_sync((sc)->sc_dmat, \ 127 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 128 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 129 __n -= (MVGBE_TX_RING_CNT - __x); \ 130 __x = 0; \ 131 } \ 132 \ 133 /* Now sync whatever is left. */ \ 134 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 135 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 136 } while (0 /*CONSTCOND*/) 137 138 #define MVGBE_CDRXSYNC(sc, x, ops) \ 139 do { \ 140 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 141 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 142 } while (/*CONSTCOND*/0) 143 144 145 struct mvgbe_jpool_entry { 146 int slot; 147 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 148 }; 149 150 struct mvgbe_chain { 151 void *mvgbe_desc; 152 struct mbuf *mvgbe_mbuf; 153 struct mvgbe_chain *mvgbe_next; 154 }; 155 156 struct mvgbe_txmap_entry { 157 bus_dmamap_t dmamap; 158 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 159 }; 160 161 struct mvgbe_chain_data { 162 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 163 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 164 int mvgbe_tx_prod; 165 int mvgbe_tx_cons; 166 int mvgbe_tx_cnt; 167 168 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 169 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 170 bus_dmamap_t mvgbe_rx_jumbo_map; 171 int mvgbe_rx_prod; 172 int mvgbe_rx_cons; 173 int mvgbe_rx_cnt; 174 175 /* Stick the jumbo mem management stuff here too. */ 176 void *mvgbe_jslots[MVGBE_JSLOTS]; 177 void *mvgbe_jumbo_buf; 178 }; 179 180 struct mvgbe_ring_data { 181 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 182 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 183 }; 184 185 struct mvgbec_softc { 186 device_t sc_dev; 187 188 bus_space_tag_t sc_iot; 189 bus_space_handle_t sc_ioh; 190 191 kmutex_t sc_mtx; 192 193 int sc_flags; 194 }; 195 196 struct mvgbe_softc { 197 device_t sc_dev; 198 int sc_port; 199 200 bus_space_tag_t sc_iot; 201 bus_space_handle_t sc_ioh; 202 bus_space_handle_t sc_dafh; /* dest address filter handle */ 203 bus_dma_tag_t sc_dmat; 204 205 struct ethercom sc_ethercom; 206 struct mii_data sc_mii; 207 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 208 209 struct mvgbe_chain_data sc_cdata; 210 struct mvgbe_ring_data *sc_rdata; 211 bus_dmamap_t sc_ring_map; 212 int sc_if_flags; 213 214 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 215 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 216 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 217 218 #if NRND > 0 219 krndsource_t sc_rnd_source; 220 #endif 221 }; 222 223 224 /* Gigabit Ethernet Unit Global part functions */ 225 226 static int mvgbec_match(device_t, struct cfdata *, void *); 227 static void mvgbec_attach(device_t, device_t, void *); 228 229 static int mvgbec_print(void *, const char *); 230 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 231 232 /* MII funcstions */ 233 static int mvgbec_miibus_readreg(device_t, int, int); 234 static void mvgbec_miibus_writereg(device_t, int, int, int); 235 static void mvgbec_miibus_statchg(device_t); 236 237 static void mvgbec_wininit(struct mvgbec_softc *); 238 239 /* Gigabit Ethernet Port part functions */ 240 241 static int mvgbe_match(device_t, struct cfdata *, void *); 242 static void mvgbe_attach(device_t, device_t, void *); 243 244 static int mvgbe_intr(void *); 245 246 static void mvgbe_start(struct ifnet *); 247 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 248 static int mvgbe_init(struct ifnet *); 249 static void mvgbe_stop(struct ifnet *, int); 250 static void mvgbe_watchdog(struct ifnet *); 251 252 static int mvgbe_ifflags_cb(struct ethercom *); 253 254 static int mvgbe_mediachange(struct ifnet *); 255 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 256 257 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 258 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 259 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 260 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 261 static void *mvgbe_jalloc(struct mvgbe_softc *); 262 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 263 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 264 static void mvgbe_rxeof(struct mvgbe_softc *); 265 static void mvgbe_txeof(struct mvgbe_softc *); 266 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 267 static void mvgbe_filter_setup(struct mvgbe_softc *); 268 #ifdef MVGBE_DEBUG 269 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 270 #endif 271 272 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 273 mvgbec_match, mvgbec_attach, NULL, NULL); 274 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 275 mvgbec_match, mvgbec_attach, NULL, NULL); 276 277 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 278 mvgbe_match, mvgbe_attach, NULL, NULL); 279 280 device_t mvgbec0 = NULL; 281 282 struct mvgbe_port { 283 int model; 284 int unit; 285 int ports; 286 int irqs[3]; 287 int flags; 288 #define FLAGS_FIX_TQTB (1 << 0) 289 #define FLAGS_FIX_MTU (1 << 1) 290 } mvgbe_ports[] = { 291 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 292 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 293 #if 0 294 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 295 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 296 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 297 #endif 298 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 299 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 300 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU }, 301 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU }, 302 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU }, 303 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 304 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 305 306 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 307 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 308 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 14 }, FLAGS_FIX_TQTB }, 309 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 310 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB }, 311 312 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 313 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 314 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 315 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 316 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB }, 317 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB }, 318 }; 319 320 321 /* ARGSUSED */ 322 static int 323 mvgbec_match(device_t parent, cfdata_t match, void *aux) 324 { 325 struct marvell_attach_args *mva = aux; 326 int i; 327 328 if (strcmp(mva->mva_name, match->cf_name) != 0) 329 return 0; 330 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 331 return 0; 332 333 for (i = 0; i < __arraycount(mvgbe_ports); i++) 334 if (mva->mva_model == mvgbe_ports[i].model) { 335 mva->mva_size = MVGBE_SIZE; 336 return 1; 337 } 338 return 0; 339 } 340 341 /* ARGSUSED */ 342 static void 343 mvgbec_attach(device_t parent, device_t self, void *aux) 344 { 345 struct mvgbec_softc *sc = device_private(self); 346 struct marvell_attach_args *mva = aux, gbea; 347 struct mvgbe_softc *port; 348 struct mii_softc *mii; 349 device_t child; 350 uint32_t phyaddr; 351 int i, j; 352 353 aprint_naive("\n"); 354 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 355 356 sc->sc_dev = self; 357 sc->sc_iot = mva->mva_iot; 358 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 359 mva->mva_size, &sc->sc_ioh)) { 360 aprint_error_dev(self, "Cannot map registers\n"); 361 return; 362 } 363 364 if (mvgbec0 == NULL) 365 mvgbec0 = self; 366 367 phyaddr = 0; 368 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 369 370 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 371 372 /* Disable and clear Gigabit Ethernet Unit interrupts */ 373 MVGBE_WRITE(sc, MVGBE_EUIM, 0); 374 MVGBE_WRITE(sc, MVGBE_EUIC, 0); 375 376 mvgbec_wininit(sc); 377 378 memset(&gbea, 0, sizeof(gbea)); 379 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 380 if (mvgbe_ports[i].model != mva->mva_model || 381 mvgbe_ports[i].unit != mva->mva_unit) 382 continue; 383 384 sc->sc_flags = mvgbe_ports[i].flags; 385 386 for (j = 0; j < mvgbe_ports[i].ports; j++) { 387 gbea.mva_name = "mvgbe"; 388 gbea.mva_model = mva->mva_model; 389 gbea.mva_iot = sc->sc_iot; 390 gbea.mva_ioh = sc->sc_ioh; 391 gbea.mva_unit = j; 392 gbea.mva_dmat = mva->mva_dmat; 393 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 394 child = config_found_sm_loc(sc->sc_dev, "mvgbec", NULL, 395 &gbea, mvgbec_print, mvgbec_search); 396 if (child) { 397 port = device_private(child); 398 mii = LIST_FIRST(&port->sc_mii.mii_phys); 399 phyaddr |= MVGBE_PHYADDR_PHYAD(j, mii->mii_phy); 400 } 401 } 402 break; 403 } 404 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 405 } 406 407 static int 408 mvgbec_print(void *aux, const char *pnp) 409 { 410 struct marvell_attach_args *gbea = aux; 411 412 if (pnp) 413 aprint_normal("%s at %s port %d", 414 gbea->mva_name, pnp, gbea->mva_unit); 415 else { 416 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 417 aprint_normal(" port %d", gbea->mva_unit); 418 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 419 aprint_normal(" irq %d", gbea->mva_irq); 420 } 421 return UNCONF; 422 } 423 424 /* ARGSUSED */ 425 static int 426 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 427 { 428 struct marvell_attach_args *gbea = aux; 429 430 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 431 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 432 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 433 434 return config_match(parent, cf, aux); 435 } 436 437 static int 438 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 439 { 440 struct mvgbe_softc *sc = device_private(dev); 441 struct mvgbec_softc *csc; 442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 443 uint32_t smi, val; 444 int i; 445 446 if (mvgbec0 == NULL) { 447 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 448 return -1; 449 } 450 csc = device_private(mvgbec0); 451 452 mutex_enter(&csc->sc_mtx); 453 454 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 455 DELAY(1); 456 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 457 break; 458 } 459 if (i == MVGBE_PHY_TIMEOUT) { 460 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 461 mutex_exit(&csc->sc_mtx); 462 return -1; 463 } 464 465 smi = 466 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 467 MVGBE_WRITE(csc, MVGBE_SMI, smi); 468 469 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 470 DELAY(1); 471 smi = MVGBE_READ(csc, MVGBE_SMI); 472 if (smi & MVGBE_SMI_READVALID) 473 break; 474 } 475 476 mutex_exit(&csc->sc_mtx); 477 478 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 479 i, MVGBE_PHY_TIMEOUT)); 480 481 val = smi & MVGBE_SMI_DATA_MASK; 482 483 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 484 phy, reg, val)); 485 486 return val; 487 } 488 489 static void 490 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 491 { 492 struct mvgbe_softc *sc = device_private(dev); 493 struct mvgbec_softc *csc; 494 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 495 uint32_t smi; 496 int i; 497 498 if (mvgbec0 == NULL) { 499 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 500 return; 501 } 502 csc = device_private(mvgbec0); 503 504 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 505 phy, reg, val)); 506 507 mutex_enter(&csc->sc_mtx); 508 509 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 510 DELAY(1); 511 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 512 break; 513 } 514 if (i == MVGBE_PHY_TIMEOUT) { 515 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 516 mutex_exit(&csc->sc_mtx); 517 return; 518 } 519 520 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 521 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 522 MVGBE_WRITE(csc, MVGBE_SMI, smi); 523 524 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 525 DELAY(1); 526 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 527 break; 528 } 529 530 mutex_exit(&csc->sc_mtx); 531 532 if (i == MVGBE_PHY_TIMEOUT) 533 aprint_error_ifnet(ifp, "phy write timed out\n"); 534 } 535 536 static void 537 mvgbec_miibus_statchg(device_t dev) 538 { 539 540 /* nothing to do */ 541 } 542 543 544 static void 545 mvgbec_wininit(struct mvgbec_softc *sc) 546 { 547 device_t pdev = device_parent(sc->sc_dev); 548 uint64_t base; 549 uint32_t en, ac, size; 550 int window, target, attr, rv, i; 551 static int tags[] = { 552 MARVELL_TAG_SDRAM_CS0, 553 MARVELL_TAG_SDRAM_CS1, 554 MARVELL_TAG_SDRAM_CS2, 555 MARVELL_TAG_SDRAM_CS3, 556 557 MARVELL_TAG_UNDEFINED, 558 }; 559 560 /* First disable all address decode windows */ 561 en = MVGBE_BARE_EN_MASK; 562 MVGBE_WRITE(sc, MVGBE_BARE, en); 563 564 ac = 0; 565 for (window = 0, i = 0; 566 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 567 rv = marvell_winparams_by_tag(pdev, tags[i], 568 &target, &attr, &base, &size); 569 if (rv != 0 || size == 0) 570 continue; 571 572 if (base > 0xffffffffULL) { 573 if (window >= MVGBE_NREMAP) { 574 aprint_error_dev(sc->sc_dev, 575 "can't remap window %d\n", window); 576 continue; 577 } 578 MVGBE_WRITE(sc, MVGBE_HA(window), 579 (base >> 32) & 0xffffffff); 580 } 581 582 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 583 MVGBE_BASEADDR_TARGET(target) | 584 MVGBE_BASEADDR_ATTR(attr) | 585 MVGBE_BASEADDR_BASE(base)); 586 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 587 588 en &= ~(1 << window); 589 /* set full access (r/w) */ 590 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 591 window++; 592 } 593 /* allow to access decode window */ 594 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 595 596 MVGBE_WRITE(sc, MVGBE_BARE, en); 597 } 598 599 600 /* ARGSUSED */ 601 static int 602 mvgbe_match(device_t parent, cfdata_t match, void *aux) 603 { 604 struct marvell_attach_args *mva = aux; 605 uint32_t pbase, maddrh, maddrl; 606 607 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 608 maddrh = 609 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 610 maddrl = 611 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 612 if ((maddrh | maddrl) == 0) 613 return 0; 614 615 return 1; 616 } 617 618 /* ARGSUSED */ 619 static void 620 mvgbe_attach(device_t parent, device_t self, void *aux) 621 { 622 struct mvgbe_softc *sc = device_private(self); 623 struct marvell_attach_args *mva = aux; 624 struct mvgbe_txmap_entry *entry; 625 struct ifnet *ifp; 626 bus_dma_segment_t seg; 627 bus_dmamap_t dmamap; 628 int rseg, i; 629 uint32_t maddrh, maddrl; 630 void *kva; 631 632 aprint_naive("\n"); 633 aprint_normal("\n"); 634 635 sc->sc_dev = self; 636 sc->sc_port = mva->mva_unit; 637 sc->sc_iot = mva->mva_iot; 638 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 639 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 640 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 641 aprint_error_dev(self, "Cannot map registers\n"); 642 return; 643 } 644 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 645 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 646 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 647 aprint_error_dev(self, 648 "Cannot map destination address filter registers\n"); 649 return; 650 } 651 sc->sc_dmat = mva->mva_dmat; 652 653 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 654 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 655 sc->sc_enaddr[0] = maddrh >> 24; 656 sc->sc_enaddr[1] = maddrh >> 16; 657 sc->sc_enaddr[2] = maddrh >> 8; 658 sc->sc_enaddr[3] = maddrh >> 0; 659 sc->sc_enaddr[4] = maddrl >> 8; 660 sc->sc_enaddr[5] = maddrl >> 0; 661 aprint_normal_dev(self, "Ethernet address %s\n", 662 ether_sprintf(sc->sc_enaddr)); 663 664 /* clear all ethernet port interrupts */ 665 MVGBE_WRITE(sc, MVGBE_IC, 0); 666 MVGBE_WRITE(sc, MVGBE_ICE, 0); 667 668 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 669 670 /* Allocate the descriptor queues. */ 671 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 672 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 673 aprint_error_dev(self, "can't alloc rx buffers\n"); 674 return; 675 } 676 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 677 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 678 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 679 (u_long)sizeof(struct mvgbe_ring_data)); 680 goto fail1; 681 } 682 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 683 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 684 &sc->sc_ring_map)) { 685 aprint_error_dev(self, "can't create dma map\n"); 686 goto fail2; 687 } 688 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 689 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 690 aprint_error_dev(self, "can't load dma map\n"); 691 goto fail3; 692 } 693 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 694 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 695 696 SIMPLEQ_INIT(&sc->sc_txmap_head); 697 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 698 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 699 700 if (bus_dmamap_create(sc->sc_dmat, 701 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 702 BUS_DMA_NOWAIT, &dmamap)) { 703 aprint_error_dev(self, "Can't create TX dmamap\n"); 704 goto fail4; 705 } 706 707 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 708 if (!entry) { 709 aprint_error_dev(self, "Can't alloc txmap entry\n"); 710 bus_dmamap_destroy(sc->sc_dmat, dmamap); 711 goto fail4; 712 } 713 entry->dmamap = dmamap; 714 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 715 } 716 717 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 718 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 719 720 /* 721 * We can support 802.1Q VLAN-sized frames and jumbo 722 * Ethernet frames. 723 */ 724 sc->sc_ethercom.ec_capabilities |= 725 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 726 727 /* Try to allocate memory for jumbo buffers. */ 728 if (mvgbe_alloc_jumbo_mem(sc)) { 729 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 730 goto fail4; 731 } 732 733 ifp = &sc->sc_ethercom.ec_if; 734 ifp->if_softc = sc; 735 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 736 ifp->if_start = mvgbe_start; 737 ifp->if_ioctl = mvgbe_ioctl; 738 ifp->if_init = mvgbe_init; 739 ifp->if_stop = mvgbe_stop; 740 ifp->if_watchdog = mvgbe_watchdog; 741 /* 742 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 743 */ 744 sc->sc_ethercom.ec_if.if_capabilities |= 745 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 746 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 747 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 748 /* 749 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 750 */ 751 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 752 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 753 IFQ_SET_READY(&ifp->if_snd); 754 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 755 756 mvgbe_stop(ifp, 0); 757 758 /* 759 * Do MII setup. 760 */ 761 sc->sc_mii.mii_ifp = ifp; 762 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 763 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 764 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 765 766 sc->sc_ethercom.ec_mii = &sc->sc_mii; 767 ifmedia_init(&sc->sc_mii.mii_media, 0, 768 mvgbe_mediachange, mvgbe_mediastatus); 769 mii_attach(self, &sc->sc_mii, 0xffffffff, 770 MII_PHY_ANY, parent == mvgbec0 ? 0 : 1, 0); 771 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 772 aprint_error_dev(self, "no PHY found!\n"); 773 ifmedia_add(&sc->sc_mii.mii_media, 774 IFM_ETHER|IFM_MANUAL, 0, NULL); 775 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 776 } else 777 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 778 779 /* 780 * Call MI attach routines. 781 */ 782 if_attach(ifp); 783 784 ether_ifattach(ifp, sc->sc_enaddr); 785 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 786 787 #if NRND > 0 788 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 789 RND_TYPE_NET, 0); 790 #endif 791 792 return; 793 794 fail4: 795 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 796 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 797 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 798 } 799 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 800 fail3: 801 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 802 fail2: 803 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 804 fail1: 805 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 806 return; 807 } 808 809 810 static int 811 mvgbe_intr(void *arg) 812 { 813 struct mvgbe_softc *sc = arg; 814 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 815 uint32_t ic, ice, datum = 0; 816 int claimed = 0; 817 818 for (;;) { 819 ice = MVGBE_READ(sc, MVGBE_ICE); 820 ic = MVGBE_READ(sc, MVGBE_IC); 821 822 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 823 if (ic == 0 && ice == 0) 824 break; 825 826 datum = datum ^ ic ^ ice; 827 828 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 829 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 830 831 claimed = 1; 832 833 if (ice & MVGBE_ICE_LINKCHG) { 834 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 835 /* Enable port RX and TX. */ 836 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 837 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 838 } else { 839 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 840 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 841 } 842 } 843 844 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 845 mvgbe_rxeof(sc); 846 847 if (ice & (MVGBE_ICE_TXBUF | MVGBE_ICE_TXERR)) 848 mvgbe_txeof(sc); 849 } 850 851 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 852 mvgbe_start(ifp); 853 854 #if NRND > 0 855 if (RND_ENABLED(&sc->sc_rnd_source)) 856 rnd_add_uint32(&sc->sc_rnd_source, datum); 857 #endif 858 859 return claimed; 860 } 861 862 static void 863 mvgbe_start(struct ifnet *ifp) 864 { 865 struct mvgbe_softc *sc = ifp->if_softc; 866 struct mbuf *m_head = NULL; 867 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 868 int pkts = 0; 869 870 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 871 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 872 873 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 874 return; 875 /* If Link is DOWN, can't start TX */ 876 if (!(MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP)) 877 return; 878 879 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 880 IFQ_POLL(&ifp->if_snd, m_head); 881 if (m_head == NULL) 882 break; 883 884 /* 885 * Pack the data into the transmit ring. If we 886 * don't have room, set the OACTIVE flag and wait 887 * for the NIC to drain the ring. 888 */ 889 if (mvgbe_encap(sc, m_head, &idx)) { 890 ifp->if_flags |= IFF_OACTIVE; 891 break; 892 } 893 894 /* now we are committed to transmit the packet */ 895 IFQ_DEQUEUE(&ifp->if_snd, m_head); 896 pkts++; 897 898 /* 899 * If there's a BPF listener, bounce a copy of this frame 900 * to him. 901 */ 902 bpf_mtap(ifp, m_head); 903 } 904 if (pkts == 0) 905 return; 906 907 /* Transmit at Queue 0 */ 908 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 909 sc->sc_cdata.mvgbe_tx_prod = idx; 910 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 911 912 /* 913 * Set a timeout in case the chip goes out to lunch. 914 */ 915 ifp->if_timer = 5; 916 } 917 } 918 919 static int 920 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 921 { 922 struct mvgbe_softc *sc = ifp->if_softc; 923 struct ifreq *ifr = data; 924 int s, error = 0; 925 926 s = splnet(); 927 928 switch (cmd) { 929 case SIOCGIFMEDIA: 930 case SIOCSIFMEDIA: 931 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 932 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 933 break; 934 default: 935 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 936 error = ether_ioctl(ifp, cmd, data); 937 if (error == ENETRESET) { 938 if (ifp->if_flags & IFF_RUNNING) { 939 mvgbe_filter_setup(sc); 940 } 941 error = 0; 942 } 943 break; 944 } 945 946 splx(s); 947 948 return error; 949 } 950 951 int mvgbe_rximt = 0; 952 int mvgbe_tximt = 0; 953 954 static int 955 mvgbe_init(struct ifnet *ifp) 956 { 957 struct mvgbe_softc *sc = ifp->if_softc; 958 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 959 struct mii_data *mii = &sc->sc_mii; 960 uint32_t reg; 961 int i; 962 963 DPRINTFN(2, ("mvgbe_init\n")); 964 965 /* Cancel pending I/O and free all RX/TX buffers. */ 966 mvgbe_stop(ifp, 0); 967 968 /* clear all ethernet port interrupts */ 969 MVGBE_WRITE(sc, MVGBE_IC, 0); 970 MVGBE_WRITE(sc, MVGBE_ICE, 0); 971 972 /* Init TX/RX descriptors */ 973 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 974 aprint_error_ifnet(ifp, 975 "initialization failed: no memory for tx buffers\n"); 976 return ENOBUFS; 977 } 978 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 979 aprint_error_ifnet(ifp, 980 "initialization failed: no memory for rx buffers\n"); 981 return ENOBUFS; 982 } 983 984 if (csc->sc_flags & FLAGS_FIX_MTU) 985 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 986 MVGBE_WRITE(sc, MVGBE_PSC, 987 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 988 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 989 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 990 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 991 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 992 /* XXXX: mvgbe(4) always use RGMII. */ 993 MVGBE_WRITE(sc, MVGBE_PSC1, 994 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 995 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 996 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 997 998 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 999 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1000 1001 if (csc->sc_flags & FLAGS_FIX_TQTB) { 1002 /* 1003 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1004 * And offset 0x72704 must be programmed to 0x03ffffff. 1005 * Queue 1 through 7 must be programmed to 0x0. 1006 */ 1007 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1008 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1009 for (i = 1; i < 8; i++) { 1010 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1011 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1012 } 1013 } else 1014 for (i = 1; i < 8; i++) { 1015 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1016 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1017 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1018 } 1019 1020 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1021 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1022 MVGBE_WRITE(sc, MVGBE_SDC, 1023 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1024 #if BYTE_ORDER == LITTLE_ENDIAN 1025 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1026 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1027 #endif 1028 MVGBE_SDC_IPGINTRX(mvgbe_rximt) | 1029 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1030 MVGBE_WRITE(sc, MVGBE_PTFUT, MVGBE_PTFUT_IPGINTTX(mvgbe_tximt)); 1031 1032 mvgbe_filter_setup(sc); 1033 1034 mii_mediachg(mii); 1035 1036 /* Enable port */ 1037 reg = MVGBE_READ(sc, MVGBE_PSC); 1038 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1039 1040 /* If Link is UP, Start RX and TX traffic */ 1041 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 1042 /* Enable port RX/TX. */ 1043 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1044 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 1045 } 1046 1047 /* Enable interrupt masks */ 1048 MVGBE_WRITE(sc, MVGBE_PIM, 1049 MVGBE_IC_RXBUF | 1050 MVGBE_IC_EXTEND | 1051 MVGBE_IC_RXBUFQ_MASK | 1052 MVGBE_IC_RXERROR | 1053 MVGBE_IC_RXERRQ_MASK); 1054 MVGBE_WRITE(sc, MVGBE_PEIM, 1055 MVGBE_ICE_TXBUF | 1056 MVGBE_ICE_TXERR | 1057 MVGBE_ICE_LINKCHG); 1058 1059 ifp->if_flags |= IFF_RUNNING; 1060 ifp->if_flags &= ~IFF_OACTIVE; 1061 1062 return 0; 1063 } 1064 1065 /* ARGSUSED */ 1066 static void 1067 mvgbe_stop(struct ifnet *ifp, int disable) 1068 { 1069 struct mvgbe_softc *sc = ifp->if_softc; 1070 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1071 uint32_t reg; 1072 int i, cnt; 1073 1074 DPRINTFN(2, ("mvgbe_stop\n")); 1075 1076 /* Stop Rx port activity. Check port Rx activity. */ 1077 reg = MVGBE_READ(sc, MVGBE_RQC); 1078 if (reg & MVGBE_RQC_ENQ_MASK) 1079 /* Issue stop command for active channels only */ 1080 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1081 1082 /* Stop Tx port activity. Check port Tx activity. */ 1083 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ) 1084 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 1085 1086 /* Force link down */ 1087 reg = MVGBE_READ(sc, MVGBE_PSC); 1088 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1089 1090 #define RX_DISABLE_TIMEOUT 0x1000000 1091 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1092 /* Wait for all Rx activity to terminate. */ 1093 cnt = 0; 1094 do { 1095 if (cnt >= RX_DISABLE_TIMEOUT) { 1096 aprint_error_ifnet(ifp, 1097 "timeout for RX stopped. rqc 0x%x\n", reg); 1098 break; 1099 } 1100 cnt++; 1101 1102 /* 1103 * Check Receive Queue Command register that all Rx queues 1104 * are stopped 1105 */ 1106 reg = MVGBE_READ(sc, MVGBE_RQC); 1107 } while (reg & 0xff); 1108 1109 /* Double check to verify that TX FIFO is empty */ 1110 cnt = 0; 1111 while (1) { 1112 do { 1113 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1114 aprint_error_ifnet(ifp, 1115 "timeout for TX FIFO empty. status 0x%x\n", 1116 reg); 1117 break; 1118 } 1119 cnt++; 1120 1121 reg = MVGBE_READ(sc, MVGBE_PS); 1122 } while 1123 (!(reg & MVGBE_PS_TXFIFOEMP) || reg & MVGBE_PS_TXINPROG); 1124 1125 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1126 break; 1127 1128 /* Double check */ 1129 reg = MVGBE_READ(sc, MVGBE_PS); 1130 if (reg & MVGBE_PS_TXFIFOEMP && !(reg & MVGBE_PS_TXINPROG)) 1131 break; 1132 else 1133 aprint_error_ifnet(ifp, 1134 "TX FIFO empty double check failed." 1135 " %d loops, status 0x%x\n", cnt, reg); 1136 } 1137 1138 /* Reset the Enable bit in the Port Serial Control Register */ 1139 reg = MVGBE_READ(sc, MVGBE_PSC); 1140 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1141 1142 /* Disable interrupts */ 1143 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1144 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1145 1146 /* Free RX and TX mbufs still in the queues. */ 1147 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1148 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1149 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1150 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1151 } 1152 } 1153 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1154 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1155 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1156 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1157 } 1158 } 1159 1160 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1161 } 1162 1163 static void 1164 mvgbe_watchdog(struct ifnet *ifp) 1165 { 1166 struct mvgbe_softc *sc = ifp->if_softc; 1167 1168 /* 1169 * Reclaim first as there is a possibility of losing Tx completion 1170 * interrupts. 1171 */ 1172 mvgbe_txeof(sc); 1173 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1174 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1175 1176 ifp->if_oerrors++; 1177 1178 mvgbe_init(ifp); 1179 } 1180 } 1181 1182 static int 1183 mvgbe_ifflags_cb(struct ethercom *ec) 1184 { 1185 struct ifnet *ifp = &ec->ec_if; 1186 struct mvgbe_softc *sc = ifp->if_softc; 1187 int change = ifp->if_flags ^ sc->sc_if_flags; 1188 1189 if (change != 0) 1190 sc->sc_if_flags = ifp->if_flags; 1191 1192 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1193 return ENETRESET; 1194 1195 if ((change & IFF_PROMISC) != 0) 1196 mvgbe_filter_setup(sc); 1197 1198 return 0; 1199 } 1200 1201 /* 1202 * Set media options. 1203 */ 1204 static int 1205 mvgbe_mediachange(struct ifnet *ifp) 1206 { 1207 return ether_mediachange(ifp); 1208 } 1209 1210 /* 1211 * Report current media status. 1212 */ 1213 static void 1214 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1215 { 1216 ether_mediastatus(ifp, ifmr); 1217 } 1218 1219 1220 static int 1221 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1222 { 1223 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1224 struct mvgbe_ring_data *rd = sc->sc_rdata; 1225 int i; 1226 1227 memset(rd->mvgbe_rx_ring, 0, 1228 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1229 1230 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1231 cd->mvgbe_rx_chain[i].mvgbe_desc = 1232 &rd->mvgbe_rx_ring[i]; 1233 if (i == MVGBE_RX_RING_CNT - 1) { 1234 cd->mvgbe_rx_chain[i].mvgbe_next = 1235 &cd->mvgbe_rx_chain[0]; 1236 rd->mvgbe_rx_ring[i].nextdescptr = 1237 MVGBE_RX_RING_ADDR(sc, 0); 1238 } else { 1239 cd->mvgbe_rx_chain[i].mvgbe_next = 1240 &cd->mvgbe_rx_chain[i + 1]; 1241 rd->mvgbe_rx_ring[i].nextdescptr = 1242 MVGBE_RX_RING_ADDR(sc, i + 1); 1243 } 1244 } 1245 1246 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1247 if (mvgbe_newbuf(sc, i, NULL, 1248 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1249 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1250 "failed alloc of %dth mbuf\n", i); 1251 return ENOBUFS; 1252 } 1253 } 1254 sc->sc_cdata.mvgbe_rx_prod = 0; 1255 sc->sc_cdata.mvgbe_rx_cons = 0; 1256 1257 return 0; 1258 } 1259 1260 static int 1261 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1262 { 1263 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1264 struct mvgbe_ring_data *rd = sc->sc_rdata; 1265 int i; 1266 1267 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1268 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1269 1270 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1271 cd->mvgbe_tx_chain[i].mvgbe_desc = 1272 &rd->mvgbe_tx_ring[i]; 1273 if (i == MVGBE_TX_RING_CNT - 1) { 1274 cd->mvgbe_tx_chain[i].mvgbe_next = 1275 &cd->mvgbe_tx_chain[0]; 1276 rd->mvgbe_tx_ring[i].nextdescptr = 1277 MVGBE_TX_RING_ADDR(sc, 0); 1278 } else { 1279 cd->mvgbe_tx_chain[i].mvgbe_next = 1280 &cd->mvgbe_tx_chain[i + 1]; 1281 rd->mvgbe_tx_ring[i].nextdescptr = 1282 MVGBE_TX_RING_ADDR(sc, i + 1); 1283 } 1284 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1285 } 1286 1287 sc->sc_cdata.mvgbe_tx_prod = 0; 1288 sc->sc_cdata.mvgbe_tx_cons = 0; 1289 sc->sc_cdata.mvgbe_tx_cnt = 0; 1290 1291 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1292 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1293 1294 return 0; 1295 } 1296 1297 static int 1298 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1299 bus_dmamap_t dmamap) 1300 { 1301 struct mbuf *m_new = NULL; 1302 struct mvgbe_chain *c; 1303 struct mvgbe_rx_desc *r; 1304 int align; 1305 1306 if (m == NULL) { 1307 void *buf = NULL; 1308 1309 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1310 if (m_new == NULL) { 1311 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1312 "no memory for rx list -- packet dropped!\n"); 1313 return ENOBUFS; 1314 } 1315 1316 /* Allocate the jumbo buffer */ 1317 buf = mvgbe_jalloc(sc); 1318 if (buf == NULL) { 1319 m_freem(m_new); 1320 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1321 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1322 return ENOBUFS; 1323 } 1324 1325 /* Attach the buffer to the mbuf */ 1326 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1327 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1328 } else { 1329 /* 1330 * We're re-using a previously allocated mbuf; 1331 * be sure to re-init pointers and lengths to 1332 * default values. 1333 */ 1334 m_new = m; 1335 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1336 m_new->m_data = m_new->m_ext.ext_buf; 1337 } 1338 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1339 if (align != 0) { 1340 DPRINTFN(1,("align = %d\n", align)); 1341 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1342 } 1343 1344 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1345 r = c->mvgbe_desc; 1346 c->mvgbe_mbuf = m_new; 1347 r->bufptr = dmamap->dm_segs[0].ds_addr + 1348 (((vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf)); 1349 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1350 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1351 1352 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1353 1354 return 0; 1355 } 1356 1357 /* 1358 * Memory management for jumbo frames. 1359 */ 1360 1361 static int 1362 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1363 { 1364 char *ptr, *kva; 1365 bus_dma_segment_t seg; 1366 int i, rseg, state, error; 1367 struct mvgbe_jpool_entry *entry; 1368 1369 state = error = 0; 1370 1371 /* Grab a big chunk o' storage. */ 1372 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1373 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1374 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1375 return ENOBUFS; 1376 } 1377 1378 state = 1; 1379 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1380 (void **)&kva, BUS_DMA_NOWAIT)) { 1381 aprint_error_dev(sc->sc_dev, 1382 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1383 error = ENOBUFS; 1384 goto out; 1385 } 1386 1387 state = 2; 1388 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1389 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1390 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1391 error = ENOBUFS; 1392 goto out; 1393 } 1394 1395 state = 3; 1396 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1397 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1398 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1399 error = ENOBUFS; 1400 goto out; 1401 } 1402 1403 state = 4; 1404 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1405 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1406 1407 LIST_INIT(&sc->sc_jfree_listhead); 1408 LIST_INIT(&sc->sc_jinuse_listhead); 1409 1410 /* 1411 * Now divide it up into 9K pieces and save the addresses 1412 * in an array. 1413 */ 1414 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1415 for (i = 0; i < MVGBE_JSLOTS; i++) { 1416 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1417 ptr += MVGBE_JLEN; 1418 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1419 if (entry == NULL) { 1420 aprint_error_dev(sc->sc_dev, 1421 "no memory for jumbo buffer queue!\n"); 1422 error = ENOBUFS; 1423 goto out; 1424 } 1425 entry->slot = i; 1426 if (i) 1427 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1428 jpool_entries); 1429 else 1430 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1431 jpool_entries); 1432 } 1433 out: 1434 if (error != 0) { 1435 switch (state) { 1436 case 4: 1437 bus_dmamap_unload(sc->sc_dmat, 1438 sc->sc_cdata.mvgbe_rx_jumbo_map); 1439 case 3: 1440 bus_dmamap_destroy(sc->sc_dmat, 1441 sc->sc_cdata.mvgbe_rx_jumbo_map); 1442 case 2: 1443 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1444 case 1: 1445 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1446 break; 1447 default: 1448 break; 1449 } 1450 } 1451 1452 return error; 1453 } 1454 1455 /* 1456 * Allocate a jumbo buffer. 1457 */ 1458 static void * 1459 mvgbe_jalloc(struct mvgbe_softc *sc) 1460 { 1461 struct mvgbe_jpool_entry *entry; 1462 1463 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1464 1465 if (entry == NULL) 1466 return NULL; 1467 1468 LIST_REMOVE(entry, jpool_entries); 1469 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1470 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1471 } 1472 1473 /* 1474 * Release a jumbo buffer. 1475 */ 1476 static void 1477 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1478 { 1479 struct mvgbe_jpool_entry *entry; 1480 struct mvgbe_softc *sc; 1481 int i, s; 1482 1483 /* Extract the softc struct pointer. */ 1484 sc = (struct mvgbe_softc *)arg; 1485 1486 if (sc == NULL) 1487 panic("%s: can't find softc pointer!", __func__); 1488 1489 /* calculate the slot this buffer belongs to */ 1490 1491 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1492 1493 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1494 panic("%s: asked to free buffer that we don't manage!", 1495 __func__); 1496 1497 s = splvm(); 1498 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1499 if (entry == NULL) 1500 panic("%s: buffer not in use!", __func__); 1501 entry->slot = i; 1502 LIST_REMOVE(entry, jpool_entries); 1503 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1504 1505 if (__predict_true(m != NULL)) 1506 pool_cache_put(mb_cache, m); 1507 splx(s); 1508 } 1509 1510 static int 1511 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1512 uint32_t *txidx) 1513 { 1514 struct mvgbe_tx_desc *f = NULL; 1515 struct mvgbe_txmap_entry *entry; 1516 bus_dma_segment_t *txseg; 1517 bus_dmamap_t txmap; 1518 uint32_t first, current, last, cmdsts = 0; 1519 int m_csumflags, i; 1520 bool needs_defrag = false; 1521 1522 DPRINTFN(3, ("mvgbe_encap\n")); 1523 1524 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1525 if (entry == NULL) { 1526 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1527 return ENOBUFS; 1528 } 1529 txmap = entry->dmamap; 1530 1531 first = current = last = *txidx; 1532 1533 /* 1534 * Preserve m_pkthdr.csum_flags here since m_head might be 1535 * updated by m_defrag() 1536 */ 1537 m_csumflags = m_head->m_pkthdr.csum_flags; 1538 1539 do_defrag: 1540 if (__predict_false(needs_defrag == true)) { 1541 /* A small unaligned segment was detected. */ 1542 struct mbuf *m_new; 1543 m_new = m_defrag(m_head, M_DONTWAIT); 1544 if (m_new == NULL) 1545 return EFBIG; 1546 m_head = m_new; 1547 } 1548 1549 /* 1550 * Start packing the mbufs in this chain into 1551 * the fragment pointers. Stop when we run out 1552 * of fragments or hit the end of the mbuf chain. 1553 */ 1554 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1555 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1556 return ENOBUFS; 1557 } 1558 1559 txseg = txmap->dm_segs; 1560 1561 if (__predict_true(needs_defrag == false)) { 1562 /* 1563 * Detect rarely encountered DMA limitation. 1564 */ 1565 for (i = 0; i < txmap->dm_nsegs; i++) { 1566 if (((txseg[i].ds_addr & 7) != 0) && 1567 (txseg[i].ds_len <= 8) && 1568 (txseg[i].ds_len >= 1) 1569 ) { 1570 txseg = NULL; 1571 bus_dmamap_unload(sc->sc_dmat, txmap); 1572 needs_defrag = true; 1573 goto do_defrag; 1574 } 1575 } 1576 } 1577 1578 /* Sync the DMA map. */ 1579 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1580 BUS_DMASYNC_PREWRITE); 1581 1582 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1583 MVGBE_TX_RING_CNT) { 1584 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1585 bus_dmamap_unload(sc->sc_dmat, txmap); 1586 return ENOBUFS; 1587 } 1588 1589 1590 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1591 1592 for (i = 0; i < txmap->dm_nsegs; i++) { 1593 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1594 f->bufptr = txseg[i].ds_addr; 1595 f->bytecnt = txseg[i].ds_len; 1596 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1597 last = current; 1598 current = MVGBE_TX_RING_NEXT(current); 1599 } 1600 1601 if (m_csumflags & M_CSUM_IPv4) 1602 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1603 if (m_csumflags & M_CSUM_TCPv4) 1604 cmdsts |= 1605 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1606 if (m_csumflags & M_CSUM_UDPv4) 1607 cmdsts |= 1608 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1609 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1610 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1611 1612 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1613 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1614 } 1615 if (txmap->dm_nsegs == 1) 1616 f->cmdsts = cmdsts | 1617 MVGBE_BUFFER_OWNED_BY_DMA | 1618 MVGBE_TX_GENERATE_CRC | 1619 MVGBE_TX_ENABLE_INTERRUPT | 1620 MVGBE_TX_ZERO_PADDING | 1621 MVGBE_TX_FIRST_DESC | 1622 MVGBE_TX_LAST_DESC; 1623 else { 1624 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1625 f->cmdsts = cmdsts | 1626 MVGBE_BUFFER_OWNED_BY_DMA | 1627 MVGBE_TX_GENERATE_CRC | 1628 MVGBE_TX_FIRST_DESC; 1629 1630 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1631 f->cmdsts = 1632 MVGBE_BUFFER_OWNED_BY_DMA | 1633 MVGBE_TX_ENABLE_INTERRUPT | 1634 MVGBE_TX_ZERO_PADDING | 1635 MVGBE_TX_LAST_DESC; 1636 } 1637 1638 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1639 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1640 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1641 1642 /* Sync descriptors before handing to chip */ 1643 MVGBE_CDTXSYNC(sc, *txidx, txmap->dm_nsegs, 1644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1645 1646 sc->sc_cdata.mvgbe_tx_cnt += i; 1647 *txidx = current; 1648 1649 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1650 1651 return 0; 1652 } 1653 1654 static void 1655 mvgbe_rxeof(struct mvgbe_softc *sc) 1656 { 1657 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1658 struct mvgbe_rx_desc *cur_rx; 1659 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1660 struct mbuf *m; 1661 bus_dmamap_t dmamap; 1662 uint32_t rxstat; 1663 int idx, cur, total_len; 1664 1665 idx = sc->sc_cdata.mvgbe_rx_prod; 1666 1667 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1668 1669 for (;;) { 1670 cur = idx; 1671 1672 /* Sync the descriptor */ 1673 MVGBE_CDRXSYNC(sc, idx, 1674 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1675 1676 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1677 1678 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1679 MVGBE_BUFFER_OWNED_BY_DMA) { 1680 /* Invalidate the descriptor -- it's not ready yet */ 1681 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1682 sc->sc_cdata.mvgbe_rx_prod = idx; 1683 break; 1684 } 1685 #ifdef DIAGNOSTIC 1686 if ((cur_rx->cmdsts & 1687 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1688 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1689 panic( 1690 "mvgbe_rxeof: buffer size is smaller than packet"); 1691 #endif 1692 1693 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1694 1695 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1696 BUS_DMASYNC_POSTREAD); 1697 1698 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1699 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1700 total_len = cur_rx->bytecnt; 1701 rxstat = cur_rx->cmdsts; 1702 1703 cdata->mvgbe_rx_map[idx] = NULL; 1704 1705 idx = MVGBE_RX_RING_NEXT(idx); 1706 1707 if (rxstat & MVGBE_ERROR_SUMMARY) { 1708 #if 0 1709 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1710 1711 if (err == MVGBE_RX_CRC_ERROR) 1712 ifp->if_ierrors++; 1713 if (err == MVGBE_RX_OVERRUN_ERROR) 1714 ifp->if_ierrors++; 1715 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1716 ifp->if_ierrors++; 1717 if (err == MVGBE_RX_RESOURCE_ERROR) 1718 ifp->if_ierrors++; 1719 #else 1720 ifp->if_ierrors++; 1721 #endif 1722 mvgbe_newbuf(sc, cur, m, dmamap); 1723 continue; 1724 } 1725 1726 if (total_len <= MVGBE_RX_CSUM_MIN_BYTE) /* XXX documented? */ 1727 goto sw_csum; 1728 1729 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1730 /* Check IPv4 header checksum */ 1731 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1732 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 1733 m->m_pkthdr.csum_flags |= 1734 M_CSUM_IPv4_BAD; 1735 /* Check TCPv4/UDPv4 checksum */ 1736 if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1737 MVGBE_RX_L4_TYPE_TCP) 1738 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1739 else if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1740 MVGBE_RX_L4_TYPE_UDP) 1741 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1742 if (!(rxstat & MVGBE_RX_L4_CHECKSUM)) 1743 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1744 } 1745 sw_csum: 1746 1747 /* 1748 * Try to allocate a new jumbo buffer. If that 1749 * fails, copy the packet to mbufs and put the 1750 * jumbo buffer back in the ring so it can be 1751 * re-used. If allocating mbufs fails, then we 1752 * have to drop the packet. 1753 */ 1754 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 1755 struct mbuf *m0; 1756 1757 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 1758 mvgbe_newbuf(sc, cur, m, dmamap); 1759 if (m0 == NULL) { 1760 aprint_error_ifnet(ifp, 1761 "no receive buffers available --" 1762 " packet dropped!\n"); 1763 ifp->if_ierrors++; 1764 continue; 1765 } 1766 m = m0; 1767 } else { 1768 m->m_pkthdr.rcvif = ifp; 1769 m->m_pkthdr.len = m->m_len = total_len; 1770 } 1771 1772 /* Skip on first 2byte (HW header) */ 1773 m_adj(m, MVGBE_HWHEADER_SIZE); 1774 m->m_flags |= M_HASFCS; 1775 1776 ifp->if_ipackets++; 1777 1778 bpf_mtap(ifp, m); 1779 1780 /* pass it on. */ 1781 (*ifp->if_input)(ifp, m); 1782 } 1783 } 1784 1785 static void 1786 mvgbe_txeof(struct mvgbe_softc *sc) 1787 { 1788 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1789 struct mvgbe_tx_desc *cur_tx; 1790 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1791 struct mvgbe_txmap_entry *entry; 1792 int idx; 1793 1794 DPRINTFN(3, ("mvgbe_txeof\n")); 1795 1796 /* 1797 * Go through our tx ring and free mbufs for those 1798 * frames that have been sent. 1799 */ 1800 idx = cdata->mvgbe_tx_cons; 1801 while (idx != cdata->mvgbe_tx_prod) { 1802 MVGBE_CDTXSYNC(sc, idx, 1, 1803 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1804 1805 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 1806 #ifdef MVGBE_DEBUG 1807 if (mvgbe_debug >= 3) 1808 mvgbe_dump_txdesc(cur_tx, idx); 1809 #endif 1810 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1811 MVGBE_BUFFER_OWNED_BY_DMA) { 1812 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 1813 break; 1814 } 1815 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 1816 ifp->if_opackets++; 1817 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 1818 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 1819 1820 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 1821 ifp->if_collisions++; 1822 if (err == MVGBE_TX_UNDERRUN_ERROR) 1823 ifp->if_oerrors++; 1824 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 1825 ifp->if_collisions++; 1826 } 1827 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 1828 entry = cdata->mvgbe_tx_map[idx]; 1829 1830 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 1831 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 1832 1833 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 1834 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1835 1836 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 1837 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 1838 cdata->mvgbe_tx_map[idx] = NULL; 1839 } 1840 cdata->mvgbe_tx_cnt--; 1841 idx = MVGBE_TX_RING_NEXT(idx); 1842 } 1843 if (cdata->mvgbe_tx_cnt == 0) 1844 ifp->if_timer = 0; 1845 1846 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 1847 ifp->if_flags &= ~IFF_OACTIVE; 1848 1849 cdata->mvgbe_tx_cons = idx; 1850 } 1851 1852 static uint8_t 1853 mvgbe_crc8(const uint8_t *data, size_t size) 1854 { 1855 int bit; 1856 uint8_t byte; 1857 uint8_t crc = 0; 1858 const uint8_t poly = 0x07; 1859 1860 while(size--) 1861 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 1862 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 1863 1864 return crc; 1865 } 1866 1867 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 1868 1869 static void 1870 mvgbe_filter_setup(struct mvgbe_softc *sc) 1871 { 1872 struct ethercom *ec = &sc->sc_ethercom; 1873 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 1874 struct ether_multi *enm; 1875 struct ether_multistep step; 1876 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 1877 uint32_t pxc; 1878 int i; 1879 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 1880 1881 memset(dfut, 0, sizeof(dfut)); 1882 memset(dfsmt, 0, sizeof(dfsmt)); 1883 memset(dfomt, 0, sizeof(dfomt)); 1884 1885 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1886 goto allmulti; 1887 } 1888 1889 ETHER_FIRST_MULTI(step, ec, enm); 1890 while (enm != NULL) { 1891 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1892 /* ranges are complex and somewhat rare */ 1893 goto allmulti; 1894 } 1895 /* chip handles some IPv4 multicast specially */ 1896 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 1897 i = enm->enm_addrlo[5]; 1898 dfsmt[i>>2] = 1899 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1900 } else { 1901 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 1902 dfomt[i>>2] = 1903 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1904 } 1905 1906 ETHER_NEXT_MULTI(step, enm); 1907 } 1908 goto set; 1909 1910 allmulti: 1911 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1912 for (i = 0; i < MVGBE_NDFSMT; i++) { 1913 dfsmt[i] = dfomt[i] = 1914 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1915 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1916 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1917 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1918 } 1919 } 1920 1921 set: 1922 pxc = MVGBE_READ(sc, MVGBE_PXC); 1923 pxc &= ~MVGBE_PXC_UPM; 1924 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 1925 if (ifp->if_flags & IFF_BROADCAST) { 1926 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 1927 } 1928 if (ifp->if_flags & IFF_PROMISC) { 1929 pxc |= MVGBE_PXC_UPM; 1930 } 1931 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 1932 1933 /* Set Destination Address Filter Unicast Table */ 1934 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 1935 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1936 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 1937 1938 /* Set Destination Address Filter Multicast Tables */ 1939 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 1940 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 1941 } 1942 1943 #ifdef MVGBE_DEBUG 1944 static void 1945 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 1946 { 1947 #define DESC_PRINT(X) \ 1948 if (X) \ 1949 printf("txdesc[%d]." #X "=%#x\n", idx, X); 1950 1951 #if BYTE_ORDER == BIG_ENDIAN 1952 DESC_PRINT(desc->bytecnt); 1953 DESC_PRINT(desc->l4ichk); 1954 DESC_PRINT(desc->cmdsts); 1955 DESC_PRINT(desc->nextdescptr); 1956 DESC_PRINT(desc->bufptr); 1957 #else /* LITTLE_ENDIAN */ 1958 DESC_PRINT(desc->cmdsts); 1959 DESC_PRINT(desc->l4ichk); 1960 DESC_PRINT(desc->bytecnt); 1961 DESC_PRINT(desc->bufptr); 1962 DESC_PRINT(desc->nextdescptr); 1963 #endif 1964 #undef DESC_PRINT 1965 } 1966 #endif 1967
Indexes created Wed Oct 01 07:09:59 GMT 2025