if_mvgbe.c revision 1.16
1 /* $NetBSD: if_mvgbe.c,v 1.16 2012/02/02 19:43:04 tls Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.16 2012/02/02 19:43:04 tls Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/device.h> 33 #include <sys/endian.h> 34 #include <sys/errno.h> 35 #include <sys/kmem.h> 36 #include <sys/mutex.h> 37 #include <sys/sockio.h> 38 39 #include <dev/marvell/marvellreg.h> 40 #include <dev/marvell/marvellvar.h> 41 #include <dev/marvell/mvgbereg.h> 42 43 #include <net/if.h> 44 #include <net/if_ether.h> 45 #include <net/if_media.h> 46 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/ip.h> 50 51 #include <net/bpf.h> 52 #include <sys/rnd.h> 53 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 57 #include "locators.h" 58 59 /* #define MVGBE_DEBUG 3 */ 60 #ifdef MVGBE_DEBUG 61 #define DPRINTF(x) if (mvgbe_debug) printf x 62 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 63 int mvgbe_debug = MVGBE_DEBUG; 64 #else 65 #define DPRINTF(x) 66 #define DPRINTFN(n,x) 67 #endif 68 69 70 #define MVGBE_READ(sc, reg) \ 71 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 72 #define MVGBE_WRITE(sc, reg, val) \ 73 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 74 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 75 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 76 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 77 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 78 79 #define MVGBE_TX_RING_CNT 256 80 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 81 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 82 #define MVGBE_RX_RING_CNT 256 83 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 84 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 85 86 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 87 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 88 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 89 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 90 91 #define MVGBE_JSLOTS 384 /* XXXX */ 92 #define MVGBE_JLEN ((MVGBE_MRU + MVGBE_RXBUF_ALIGN)&~MVGBE_RXBUF_MASK) 93 #define MVGBE_NTXSEG 30 94 #define MVGBE_JPAGESZ PAGE_SIZE 95 #define MVGBE_RESID \ 96 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 97 #define MVGBE_JMEM \ 98 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 99 100 #define MVGBE_TX_RING_ADDR(sc, i) \ 101 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 102 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 103 104 #define MVGBE_RX_RING_ADDR(sc, i) \ 105 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 106 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 107 108 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 109 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 110 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 111 112 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 113 do { \ 114 int __x, __n; \ 115 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 116 \ 117 __x = (x); \ 118 __n = (n); \ 119 \ 120 /* If it will wrap around, sync to the end of the ring. */ \ 121 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 122 bus_dmamap_sync((sc)->sc_dmat, \ 123 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 124 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 125 __n -= (MVGBE_TX_RING_CNT - __x); \ 126 __x = 0; \ 127 } \ 128 \ 129 /* Now sync whatever is left. */ \ 130 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 131 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 132 } while (0 /*CONSTCOND*/) 133 134 #define MVGBE_CDRXSYNC(sc, x, ops) \ 135 do { \ 136 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 137 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 138 } while (/*CONSTCOND*/0) 139 140 141 struct mvgbe_jpool_entry { 142 int slot; 143 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 144 }; 145 146 struct mvgbe_chain { 147 void *mvgbe_desc; 148 struct mbuf *mvgbe_mbuf; 149 struct mvgbe_chain *mvgbe_next; 150 }; 151 152 struct mvgbe_txmap_entry { 153 bus_dmamap_t dmamap; 154 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 155 }; 156 157 struct mvgbe_chain_data { 158 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 159 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 160 int mvgbe_tx_prod; 161 int mvgbe_tx_cons; 162 int mvgbe_tx_cnt; 163 164 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 165 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 166 bus_dmamap_t mvgbe_rx_jumbo_map; 167 int mvgbe_rx_prod; 168 int mvgbe_rx_cons; 169 int mvgbe_rx_cnt; 170 171 /* Stick the jumbo mem management stuff here too. */ 172 void *mvgbe_jslots[MVGBE_JSLOTS]; 173 void *mvgbe_jumbo_buf; 174 }; 175 176 struct mvgbe_ring_data { 177 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 178 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 179 }; 180 181 struct mvgbec_softc { 182 device_t sc_dev; 183 184 bus_space_tag_t sc_iot; 185 bus_space_handle_t sc_ioh; 186 187 kmutex_t sc_mtx; 188 189 int sc_flags; 190 }; 191 192 struct mvgbe_softc { 193 device_t sc_dev; 194 int sc_port; 195 196 bus_space_tag_t sc_iot; 197 bus_space_handle_t sc_ioh; 198 bus_space_handle_t sc_dafh; /* dest address filter handle */ 199 bus_dma_tag_t sc_dmat; 200 201 struct ethercom sc_ethercom; 202 struct mii_data sc_mii; 203 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 204 205 struct mvgbe_chain_data sc_cdata; 206 struct mvgbe_ring_data *sc_rdata; 207 bus_dmamap_t sc_ring_map; 208 int sc_if_flags; 209 210 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 211 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 212 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 213 214 krndsource_t sc_rnd_source; 215 }; 216 217 218 /* Gigabit Ethernet Unit Global part functions */ 219 220 static int mvgbec_match(device_t, struct cfdata *, void *); 221 static void mvgbec_attach(device_t, device_t, void *); 222 223 static int mvgbec_print(void *, const char *); 224 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 225 226 /* MII funcstions */ 227 static int mvgbec_miibus_readreg(device_t, int, int); 228 static void mvgbec_miibus_writereg(device_t, int, int, int); 229 static void mvgbec_miibus_statchg(device_t); 230 231 static void mvgbec_wininit(struct mvgbec_softc *); 232 233 /* Gigabit Ethernet Port part functions */ 234 235 static int mvgbe_match(device_t, struct cfdata *, void *); 236 static void mvgbe_attach(device_t, device_t, void *); 237 238 static int mvgbe_intr(void *); 239 240 static void mvgbe_start(struct ifnet *); 241 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 242 static int mvgbe_init(struct ifnet *); 243 static void mvgbe_stop(struct ifnet *, int); 244 static void mvgbe_watchdog(struct ifnet *); 245 246 static int mvgbe_ifflags_cb(struct ethercom *); 247 248 static int mvgbe_mediachange(struct ifnet *); 249 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 250 251 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 252 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 253 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 254 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 255 static void *mvgbe_jalloc(struct mvgbe_softc *); 256 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 257 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 258 static void mvgbe_rxeof(struct mvgbe_softc *); 259 static void mvgbe_txeof(struct mvgbe_softc *); 260 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 261 static void mvgbe_filter_setup(struct mvgbe_softc *); 262 #ifdef MVGBE_DEBUG 263 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 264 #endif 265 266 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 267 mvgbec_match, mvgbec_attach, NULL, NULL); 268 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 269 mvgbec_match, mvgbec_attach, NULL, NULL); 270 271 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 272 mvgbe_match, mvgbe_attach, NULL, NULL); 273 274 device_t mvgbec0 = NULL; 275 276 struct mvgbe_port { 277 int model; 278 int unit; 279 int ports; 280 int irqs[3]; 281 int flags; 282 #define FLAGS_FIX_TQTB (1 << 0) 283 #define FLAGS_FIX_MTU (1 << 1) 284 } mvgbe_ports[] = { 285 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 286 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 287 #if 0 288 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 289 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 290 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 291 #endif 292 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 293 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 294 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU }, 295 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU }, 296 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU }, 297 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 298 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 299 300 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 301 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 302 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 14 }, FLAGS_FIX_TQTB }, 303 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 304 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB }, 305 306 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 307 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 308 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 309 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 310 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB }, 311 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB }, 312 }; 313 314 315 /* ARGSUSED */ 316 static int 317 mvgbec_match(device_t parent, cfdata_t match, void *aux) 318 { 319 struct marvell_attach_args *mva = aux; 320 int i; 321 322 if (strcmp(mva->mva_name, match->cf_name) != 0) 323 return 0; 324 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 325 return 0; 326 327 for (i = 0; i < __arraycount(mvgbe_ports); i++) 328 if (mva->mva_model == mvgbe_ports[i].model) { 329 mva->mva_size = MVGBE_SIZE; 330 return 1; 331 } 332 return 0; 333 } 334 335 /* ARGSUSED */ 336 static void 337 mvgbec_attach(device_t parent, device_t self, void *aux) 338 { 339 struct mvgbec_softc *sc = device_private(self); 340 struct marvell_attach_args *mva = aux, gbea; 341 struct mvgbe_softc *port; 342 struct mii_softc *mii; 343 device_t child; 344 uint32_t phyaddr; 345 int i, j; 346 347 aprint_naive("\n"); 348 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 349 350 sc->sc_dev = self; 351 sc->sc_iot = mva->mva_iot; 352 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 353 mva->mva_size, &sc->sc_ioh)) { 354 aprint_error_dev(self, "Cannot map registers\n"); 355 return; 356 } 357 358 if (mvgbec0 == NULL) 359 mvgbec0 = self; 360 361 phyaddr = 0; 362 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 363 364 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 365 366 /* Disable and clear Gigabit Ethernet Unit interrupts */ 367 MVGBE_WRITE(sc, MVGBE_EUIM, 0); 368 MVGBE_WRITE(sc, MVGBE_EUIC, 0); 369 370 mvgbec_wininit(sc); 371 372 memset(&gbea, 0, sizeof(gbea)); 373 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 374 if (mvgbe_ports[i].model != mva->mva_model || 375 mvgbe_ports[i].unit != mva->mva_unit) 376 continue; 377 378 sc->sc_flags = mvgbe_ports[i].flags; 379 380 for (j = 0; j < mvgbe_ports[i].ports; j++) { 381 gbea.mva_name = "mvgbe"; 382 gbea.mva_model = mva->mva_model; 383 gbea.mva_iot = sc->sc_iot; 384 gbea.mva_ioh = sc->sc_ioh; 385 gbea.mva_unit = j; 386 gbea.mva_dmat = mva->mva_dmat; 387 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 388 child = config_found_sm_loc(sc->sc_dev, "mvgbec", NULL, 389 &gbea, mvgbec_print, mvgbec_search); 390 if (child) { 391 port = device_private(child); 392 mii = LIST_FIRST(&port->sc_mii.mii_phys); 393 phyaddr |= MVGBE_PHYADDR_PHYAD(j, mii->mii_phy); 394 } 395 } 396 break; 397 } 398 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 399 } 400 401 static int 402 mvgbec_print(void *aux, const char *pnp) 403 { 404 struct marvell_attach_args *gbea = aux; 405 406 if (pnp) 407 aprint_normal("%s at %s port %d", 408 gbea->mva_name, pnp, gbea->mva_unit); 409 else { 410 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 411 aprint_normal(" port %d", gbea->mva_unit); 412 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 413 aprint_normal(" irq %d", gbea->mva_irq); 414 } 415 return UNCONF; 416 } 417 418 /* ARGSUSED */ 419 static int 420 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 421 { 422 struct marvell_attach_args *gbea = aux; 423 424 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 425 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 426 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 427 428 return config_match(parent, cf, aux); 429 } 430 431 static int 432 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 433 { 434 struct mvgbe_softc *sc = device_private(dev); 435 struct mvgbec_softc *csc; 436 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 437 uint32_t smi, val; 438 int i; 439 440 if (mvgbec0 == NULL) { 441 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 442 return -1; 443 } 444 csc = device_private(mvgbec0); 445 446 mutex_enter(&csc->sc_mtx); 447 448 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 449 DELAY(1); 450 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 451 break; 452 } 453 if (i == MVGBE_PHY_TIMEOUT) { 454 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 455 mutex_exit(&csc->sc_mtx); 456 return -1; 457 } 458 459 smi = 460 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 461 MVGBE_WRITE(csc, MVGBE_SMI, smi); 462 463 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 464 DELAY(1); 465 smi = MVGBE_READ(csc, MVGBE_SMI); 466 if (smi & MVGBE_SMI_READVALID) 467 break; 468 } 469 470 mutex_exit(&csc->sc_mtx); 471 472 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 473 i, MVGBE_PHY_TIMEOUT)); 474 475 val = smi & MVGBE_SMI_DATA_MASK; 476 477 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 478 phy, reg, val)); 479 480 return val; 481 } 482 483 static void 484 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 485 { 486 struct mvgbe_softc *sc = device_private(dev); 487 struct mvgbec_softc *csc; 488 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 489 uint32_t smi; 490 int i; 491 492 if (mvgbec0 == NULL) { 493 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 494 return; 495 } 496 csc = device_private(mvgbec0); 497 498 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 499 phy, reg, val)); 500 501 mutex_enter(&csc->sc_mtx); 502 503 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 504 DELAY(1); 505 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 506 break; 507 } 508 if (i == MVGBE_PHY_TIMEOUT) { 509 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 510 mutex_exit(&csc->sc_mtx); 511 return; 512 } 513 514 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 515 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 516 MVGBE_WRITE(csc, MVGBE_SMI, smi); 517 518 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 519 DELAY(1); 520 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 521 break; 522 } 523 524 mutex_exit(&csc->sc_mtx); 525 526 if (i == MVGBE_PHY_TIMEOUT) 527 aprint_error_ifnet(ifp, "phy write timed out\n"); 528 } 529 530 static void 531 mvgbec_miibus_statchg(device_t dev) 532 { 533 534 /* nothing to do */ 535 } 536 537 538 static void 539 mvgbec_wininit(struct mvgbec_softc *sc) 540 { 541 device_t pdev = device_parent(sc->sc_dev); 542 uint64_t base; 543 uint32_t en, ac, size; 544 int window, target, attr, rv, i; 545 static int tags[] = { 546 MARVELL_TAG_SDRAM_CS0, 547 MARVELL_TAG_SDRAM_CS1, 548 MARVELL_TAG_SDRAM_CS2, 549 MARVELL_TAG_SDRAM_CS3, 550 551 MARVELL_TAG_UNDEFINED, 552 }; 553 554 /* First disable all address decode windows */ 555 en = MVGBE_BARE_EN_MASK; 556 MVGBE_WRITE(sc, MVGBE_BARE, en); 557 558 ac = 0; 559 for (window = 0, i = 0; 560 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 561 rv = marvell_winparams_by_tag(pdev, tags[i], 562 &target, &attr, &base, &size); 563 if (rv != 0 || size == 0) 564 continue; 565 566 if (base > 0xffffffffULL) { 567 if (window >= MVGBE_NREMAP) { 568 aprint_error_dev(sc->sc_dev, 569 "can't remap window %d\n", window); 570 continue; 571 } 572 MVGBE_WRITE(sc, MVGBE_HA(window), 573 (base >> 32) & 0xffffffff); 574 } 575 576 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 577 MVGBE_BASEADDR_TARGET(target) | 578 MVGBE_BASEADDR_ATTR(attr) | 579 MVGBE_BASEADDR_BASE(base)); 580 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 581 582 en &= ~(1 << window); 583 /* set full access (r/w) */ 584 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 585 window++; 586 } 587 /* allow to access decode window */ 588 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 589 590 MVGBE_WRITE(sc, MVGBE_BARE, en); 591 } 592 593 594 /* ARGSUSED */ 595 static int 596 mvgbe_match(device_t parent, cfdata_t match, void *aux) 597 { 598 struct marvell_attach_args *mva = aux; 599 uint32_t pbase, maddrh, maddrl; 600 601 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 602 maddrh = 603 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 604 maddrl = 605 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 606 if ((maddrh | maddrl) == 0) 607 return 0; 608 609 return 1; 610 } 611 612 /* ARGSUSED */ 613 static void 614 mvgbe_attach(device_t parent, device_t self, void *aux) 615 { 616 struct mvgbe_softc *sc = device_private(self); 617 struct marvell_attach_args *mva = aux; 618 struct mvgbe_txmap_entry *entry; 619 struct ifnet *ifp; 620 bus_dma_segment_t seg; 621 bus_dmamap_t dmamap; 622 int rseg, i; 623 uint32_t maddrh, maddrl; 624 void *kva; 625 626 aprint_naive("\n"); 627 aprint_normal("\n"); 628 629 sc->sc_dev = self; 630 sc->sc_port = mva->mva_unit; 631 sc->sc_iot = mva->mva_iot; 632 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 633 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 634 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 635 aprint_error_dev(self, "Cannot map registers\n"); 636 return; 637 } 638 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 639 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 640 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 641 aprint_error_dev(self, 642 "Cannot map destination address filter registers\n"); 643 return; 644 } 645 sc->sc_dmat = mva->mva_dmat; 646 647 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 648 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 649 sc->sc_enaddr[0] = maddrh >> 24; 650 sc->sc_enaddr[1] = maddrh >> 16; 651 sc->sc_enaddr[2] = maddrh >> 8; 652 sc->sc_enaddr[3] = maddrh >> 0; 653 sc->sc_enaddr[4] = maddrl >> 8; 654 sc->sc_enaddr[5] = maddrl >> 0; 655 aprint_normal_dev(self, "Ethernet address %s\n", 656 ether_sprintf(sc->sc_enaddr)); 657 658 /* clear all ethernet port interrupts */ 659 MVGBE_WRITE(sc, MVGBE_IC, 0); 660 MVGBE_WRITE(sc, MVGBE_ICE, 0); 661 662 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 663 664 /* Allocate the descriptor queues. */ 665 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 666 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 667 aprint_error_dev(self, "can't alloc rx buffers\n"); 668 return; 669 } 670 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 671 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 672 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 673 (u_long)sizeof(struct mvgbe_ring_data)); 674 goto fail1; 675 } 676 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 677 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 678 &sc->sc_ring_map)) { 679 aprint_error_dev(self, "can't create dma map\n"); 680 goto fail2; 681 } 682 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 683 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 684 aprint_error_dev(self, "can't load dma map\n"); 685 goto fail3; 686 } 687 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 688 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 689 690 SIMPLEQ_INIT(&sc->sc_txmap_head); 691 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 692 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 693 694 if (bus_dmamap_create(sc->sc_dmat, 695 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 696 BUS_DMA_NOWAIT, &dmamap)) { 697 aprint_error_dev(self, "Can't create TX dmamap\n"); 698 goto fail4; 699 } 700 701 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 702 if (!entry) { 703 aprint_error_dev(self, "Can't alloc txmap entry\n"); 704 bus_dmamap_destroy(sc->sc_dmat, dmamap); 705 goto fail4; 706 } 707 entry->dmamap = dmamap; 708 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 709 } 710 711 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 712 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 713 714 /* 715 * We can support 802.1Q VLAN-sized frames and jumbo 716 * Ethernet frames. 717 */ 718 sc->sc_ethercom.ec_capabilities |= 719 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 720 721 /* Try to allocate memory for jumbo buffers. */ 722 if (mvgbe_alloc_jumbo_mem(sc)) { 723 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 724 goto fail4; 725 } 726 727 ifp = &sc->sc_ethercom.ec_if; 728 ifp->if_softc = sc; 729 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 730 ifp->if_start = mvgbe_start; 731 ifp->if_ioctl = mvgbe_ioctl; 732 ifp->if_init = mvgbe_init; 733 ifp->if_stop = mvgbe_stop; 734 ifp->if_watchdog = mvgbe_watchdog; 735 /* 736 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 737 */ 738 sc->sc_ethercom.ec_if.if_capabilities |= 739 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 740 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 741 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 742 /* 743 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 744 */ 745 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 746 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 747 IFQ_SET_READY(&ifp->if_snd); 748 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 749 750 mvgbe_stop(ifp, 0); 751 752 /* 753 * Do MII setup. 754 */ 755 sc->sc_mii.mii_ifp = ifp; 756 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 757 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 758 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 759 760 sc->sc_ethercom.ec_mii = &sc->sc_mii; 761 ifmedia_init(&sc->sc_mii.mii_media, 0, 762 mvgbe_mediachange, mvgbe_mediastatus); 763 mii_attach(self, &sc->sc_mii, 0xffffffff, 764 MII_PHY_ANY, parent == mvgbec0 ? 0 : 1, 0); 765 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 766 aprint_error_dev(self, "no PHY found!\n"); 767 ifmedia_add(&sc->sc_mii.mii_media, 768 IFM_ETHER|IFM_MANUAL, 0, NULL); 769 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 770 } else 771 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 772 773 /* 774 * Call MI attach routines. 775 */ 776 if_attach(ifp); 777 778 ether_ifattach(ifp, sc->sc_enaddr); 779 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 780 781 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 782 RND_TYPE_NET, 0); 783 784 return; 785 786 fail4: 787 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 788 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 789 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 790 } 791 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 792 fail3: 793 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 794 fail2: 795 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 796 fail1: 797 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 798 return; 799 } 800 801 802 static int 803 mvgbe_intr(void *arg) 804 { 805 struct mvgbe_softc *sc = arg; 806 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 807 uint32_t ic, ice, datum = 0; 808 int claimed = 0; 809 810 for (;;) { 811 ice = MVGBE_READ(sc, MVGBE_ICE); 812 ic = MVGBE_READ(sc, MVGBE_IC); 813 814 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 815 if (ic == 0 && ice == 0) 816 break; 817 818 datum = datum ^ ic ^ ice; 819 820 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 821 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 822 823 claimed = 1; 824 825 if (ice & MVGBE_ICE_LINKCHG) { 826 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 827 /* Enable port RX and TX. */ 828 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 829 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 830 } else { 831 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 832 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 833 } 834 } 835 836 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 837 mvgbe_rxeof(sc); 838 839 if (ice & (MVGBE_ICE_TXBUF | MVGBE_ICE_TXERR)) 840 mvgbe_txeof(sc); 841 } 842 843 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 844 mvgbe_start(ifp); 845 846 rnd_add_uint32(&sc->sc_rnd_source, datum); 847 848 return claimed; 849 } 850 851 static void 852 mvgbe_start(struct ifnet *ifp) 853 { 854 struct mvgbe_softc *sc = ifp->if_softc; 855 struct mbuf *m_head = NULL; 856 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 857 int pkts = 0; 858 859 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 860 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 861 862 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 863 return; 864 /* If Link is DOWN, can't start TX */ 865 if (!(MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP)) 866 return; 867 868 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 869 IFQ_POLL(&ifp->if_snd, m_head); 870 if (m_head == NULL) 871 break; 872 873 /* 874 * Pack the data into the transmit ring. If we 875 * don't have room, set the OACTIVE flag and wait 876 * for the NIC to drain the ring. 877 */ 878 if (mvgbe_encap(sc, m_head, &idx)) { 879 ifp->if_flags |= IFF_OACTIVE; 880 break; 881 } 882 883 /* now we are committed to transmit the packet */ 884 IFQ_DEQUEUE(&ifp->if_snd, m_head); 885 pkts++; 886 887 /* 888 * If there's a BPF listener, bounce a copy of this frame 889 * to him. 890 */ 891 bpf_mtap(ifp, m_head); 892 } 893 if (pkts == 0) 894 return; 895 896 /* Transmit at Queue 0 */ 897 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 898 sc->sc_cdata.mvgbe_tx_prod = idx; 899 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 900 901 /* 902 * Set a timeout in case the chip goes out to lunch. 903 */ 904 ifp->if_timer = 5; 905 } 906 } 907 908 static int 909 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 910 { 911 struct mvgbe_softc *sc = ifp->if_softc; 912 struct ifreq *ifr = data; 913 int s, error = 0; 914 915 s = splnet(); 916 917 switch (cmd) { 918 case SIOCGIFMEDIA: 919 case SIOCSIFMEDIA: 920 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 921 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 922 break; 923 default: 924 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 925 error = ether_ioctl(ifp, cmd, data); 926 if (error == ENETRESET) { 927 if (ifp->if_flags & IFF_RUNNING) { 928 mvgbe_filter_setup(sc); 929 } 930 error = 0; 931 } 932 break; 933 } 934 935 splx(s); 936 937 return error; 938 } 939 940 int mvgbe_rximt = 0; 941 int mvgbe_tximt = 0; 942 943 static int 944 mvgbe_init(struct ifnet *ifp) 945 { 946 struct mvgbe_softc *sc = ifp->if_softc; 947 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 948 struct mii_data *mii = &sc->sc_mii; 949 uint32_t reg; 950 int i; 951 952 DPRINTFN(2, ("mvgbe_init\n")); 953 954 /* Cancel pending I/O and free all RX/TX buffers. */ 955 mvgbe_stop(ifp, 0); 956 957 /* clear all ethernet port interrupts */ 958 MVGBE_WRITE(sc, MVGBE_IC, 0); 959 MVGBE_WRITE(sc, MVGBE_ICE, 0); 960 961 /* Init TX/RX descriptors */ 962 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 963 aprint_error_ifnet(ifp, 964 "initialization failed: no memory for tx buffers\n"); 965 return ENOBUFS; 966 } 967 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 968 aprint_error_ifnet(ifp, 969 "initialization failed: no memory for rx buffers\n"); 970 return ENOBUFS; 971 } 972 973 if (csc->sc_flags & FLAGS_FIX_MTU) 974 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 975 MVGBE_WRITE(sc, MVGBE_PSC, 976 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 977 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 978 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 979 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 980 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 981 /* XXXX: mvgbe(4) always use RGMII. */ 982 MVGBE_WRITE(sc, MVGBE_PSC1, 983 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 984 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 985 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 986 987 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 988 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 989 990 if (csc->sc_flags & FLAGS_FIX_TQTB) { 991 /* 992 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 993 * And offset 0x72704 must be programmed to 0x03ffffff. 994 * Queue 1 through 7 must be programmed to 0x0. 995 */ 996 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 997 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 998 for (i = 1; i < 8; i++) { 999 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1000 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1001 } 1002 } else 1003 for (i = 1; i < 8; i++) { 1004 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1005 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1006 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1007 } 1008 1009 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1010 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1011 MVGBE_WRITE(sc, MVGBE_SDC, 1012 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1013 #if BYTE_ORDER == LITTLE_ENDIAN 1014 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1015 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1016 #endif 1017 MVGBE_SDC_IPGINTRX(mvgbe_rximt) | 1018 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1019 MVGBE_WRITE(sc, MVGBE_PTFUT, MVGBE_PTFUT_IPGINTTX(mvgbe_tximt)); 1020 1021 mvgbe_filter_setup(sc); 1022 1023 mii_mediachg(mii); 1024 1025 /* Enable port */ 1026 reg = MVGBE_READ(sc, MVGBE_PSC); 1027 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1028 1029 /* If Link is UP, Start RX and TX traffic */ 1030 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 1031 /* Enable port RX/TX. */ 1032 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1033 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 1034 } 1035 1036 /* Enable interrupt masks */ 1037 MVGBE_WRITE(sc, MVGBE_PIM, 1038 MVGBE_IC_RXBUF | 1039 MVGBE_IC_EXTEND | 1040 MVGBE_IC_RXBUFQ_MASK | 1041 MVGBE_IC_RXERROR | 1042 MVGBE_IC_RXERRQ_MASK); 1043 MVGBE_WRITE(sc, MVGBE_PEIM, 1044 MVGBE_ICE_TXBUF | 1045 MVGBE_ICE_TXERR | 1046 MVGBE_ICE_LINKCHG); 1047 1048 ifp->if_flags |= IFF_RUNNING; 1049 ifp->if_flags &= ~IFF_OACTIVE; 1050 1051 return 0; 1052 } 1053 1054 /* ARGSUSED */ 1055 static void 1056 mvgbe_stop(struct ifnet *ifp, int disable) 1057 { 1058 struct mvgbe_softc *sc = ifp->if_softc; 1059 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1060 uint32_t reg; 1061 int i, cnt; 1062 1063 DPRINTFN(2, ("mvgbe_stop\n")); 1064 1065 /* Stop Rx port activity. Check port Rx activity. */ 1066 reg = MVGBE_READ(sc, MVGBE_RQC); 1067 if (reg & MVGBE_RQC_ENQ_MASK) 1068 /* Issue stop command for active channels only */ 1069 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1070 1071 /* Stop Tx port activity. Check port Tx activity. */ 1072 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ) 1073 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 1074 1075 /* Force link down */ 1076 reg = MVGBE_READ(sc, MVGBE_PSC); 1077 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1078 1079 #define RX_DISABLE_TIMEOUT 0x1000000 1080 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1081 /* Wait for all Rx activity to terminate. */ 1082 cnt = 0; 1083 do { 1084 if (cnt >= RX_DISABLE_TIMEOUT) { 1085 aprint_error_ifnet(ifp, 1086 "timeout for RX stopped. rqc 0x%x\n", reg); 1087 break; 1088 } 1089 cnt++; 1090 1091 /* 1092 * Check Receive Queue Command register that all Rx queues 1093 * are stopped 1094 */ 1095 reg = MVGBE_READ(sc, MVGBE_RQC); 1096 } while (reg & 0xff); 1097 1098 /* Double check to verify that TX FIFO is empty */ 1099 cnt = 0; 1100 while (1) { 1101 do { 1102 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1103 aprint_error_ifnet(ifp, 1104 "timeout for TX FIFO empty. status 0x%x\n", 1105 reg); 1106 break; 1107 } 1108 cnt++; 1109 1110 reg = MVGBE_READ(sc, MVGBE_PS); 1111 } while 1112 (!(reg & MVGBE_PS_TXFIFOEMP) || reg & MVGBE_PS_TXINPROG); 1113 1114 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1115 break; 1116 1117 /* Double check */ 1118 reg = MVGBE_READ(sc, MVGBE_PS); 1119 if (reg & MVGBE_PS_TXFIFOEMP && !(reg & MVGBE_PS_TXINPROG)) 1120 break; 1121 else 1122 aprint_error_ifnet(ifp, 1123 "TX FIFO empty double check failed." 1124 " %d loops, status 0x%x\n", cnt, reg); 1125 } 1126 1127 /* Reset the Enable bit in the Port Serial Control Register */ 1128 reg = MVGBE_READ(sc, MVGBE_PSC); 1129 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1130 1131 /* Disable interrupts */ 1132 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1133 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1134 1135 /* Free RX and TX mbufs still in the queues. */ 1136 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1137 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1138 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1139 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1140 } 1141 } 1142 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1143 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1144 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1145 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1146 } 1147 } 1148 1149 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1150 } 1151 1152 static void 1153 mvgbe_watchdog(struct ifnet *ifp) 1154 { 1155 struct mvgbe_softc *sc = ifp->if_softc; 1156 1157 /* 1158 * Reclaim first as there is a possibility of losing Tx completion 1159 * interrupts. 1160 */ 1161 mvgbe_txeof(sc); 1162 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1163 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1164 1165 ifp->if_oerrors++; 1166 1167 mvgbe_init(ifp); 1168 } 1169 } 1170 1171 static int 1172 mvgbe_ifflags_cb(struct ethercom *ec) 1173 { 1174 struct ifnet *ifp = &ec->ec_if; 1175 struct mvgbe_softc *sc = ifp->if_softc; 1176 int change = ifp->if_flags ^ sc->sc_if_flags; 1177 1178 if (change != 0) 1179 sc->sc_if_flags = ifp->if_flags; 1180 1181 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1182 return ENETRESET; 1183 1184 if ((change & IFF_PROMISC) != 0) 1185 mvgbe_filter_setup(sc); 1186 1187 return 0; 1188 } 1189 1190 /* 1191 * Set media options. 1192 */ 1193 static int 1194 mvgbe_mediachange(struct ifnet *ifp) 1195 { 1196 return ether_mediachange(ifp); 1197 } 1198 1199 /* 1200 * Report current media status. 1201 */ 1202 static void 1203 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1204 { 1205 ether_mediastatus(ifp, ifmr); 1206 } 1207 1208 1209 static int 1210 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1211 { 1212 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1213 struct mvgbe_ring_data *rd = sc->sc_rdata; 1214 int i; 1215 1216 memset(rd->mvgbe_rx_ring, 0, 1217 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1218 1219 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1220 cd->mvgbe_rx_chain[i].mvgbe_desc = 1221 &rd->mvgbe_rx_ring[i]; 1222 if (i == MVGBE_RX_RING_CNT - 1) { 1223 cd->mvgbe_rx_chain[i].mvgbe_next = 1224 &cd->mvgbe_rx_chain[0]; 1225 rd->mvgbe_rx_ring[i].nextdescptr = 1226 MVGBE_RX_RING_ADDR(sc, 0); 1227 } else { 1228 cd->mvgbe_rx_chain[i].mvgbe_next = 1229 &cd->mvgbe_rx_chain[i + 1]; 1230 rd->mvgbe_rx_ring[i].nextdescptr = 1231 MVGBE_RX_RING_ADDR(sc, i + 1); 1232 } 1233 } 1234 1235 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1236 if (mvgbe_newbuf(sc, i, NULL, 1237 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1238 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1239 "failed alloc of %dth mbuf\n", i); 1240 return ENOBUFS; 1241 } 1242 } 1243 sc->sc_cdata.mvgbe_rx_prod = 0; 1244 sc->sc_cdata.mvgbe_rx_cons = 0; 1245 1246 return 0; 1247 } 1248 1249 static int 1250 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1251 { 1252 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1253 struct mvgbe_ring_data *rd = sc->sc_rdata; 1254 int i; 1255 1256 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1257 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1258 1259 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1260 cd->mvgbe_tx_chain[i].mvgbe_desc = 1261 &rd->mvgbe_tx_ring[i]; 1262 if (i == MVGBE_TX_RING_CNT - 1) { 1263 cd->mvgbe_tx_chain[i].mvgbe_next = 1264 &cd->mvgbe_tx_chain[0]; 1265 rd->mvgbe_tx_ring[i].nextdescptr = 1266 MVGBE_TX_RING_ADDR(sc, 0); 1267 } else { 1268 cd->mvgbe_tx_chain[i].mvgbe_next = 1269 &cd->mvgbe_tx_chain[i + 1]; 1270 rd->mvgbe_tx_ring[i].nextdescptr = 1271 MVGBE_TX_RING_ADDR(sc, i + 1); 1272 } 1273 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1274 } 1275 1276 sc->sc_cdata.mvgbe_tx_prod = 0; 1277 sc->sc_cdata.mvgbe_tx_cons = 0; 1278 sc->sc_cdata.mvgbe_tx_cnt = 0; 1279 1280 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1281 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1282 1283 return 0; 1284 } 1285 1286 static int 1287 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1288 bus_dmamap_t dmamap) 1289 { 1290 struct mbuf *m_new = NULL; 1291 struct mvgbe_chain *c; 1292 struct mvgbe_rx_desc *r; 1293 int align; 1294 1295 if (m == NULL) { 1296 void *buf = NULL; 1297 1298 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1299 if (m_new == NULL) { 1300 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1301 "no memory for rx list -- packet dropped!\n"); 1302 return ENOBUFS; 1303 } 1304 1305 /* Allocate the jumbo buffer */ 1306 buf = mvgbe_jalloc(sc); 1307 if (buf == NULL) { 1308 m_freem(m_new); 1309 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1310 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1311 return ENOBUFS; 1312 } 1313 1314 /* Attach the buffer to the mbuf */ 1315 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1316 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1317 } else { 1318 /* 1319 * We're re-using a previously allocated mbuf; 1320 * be sure to re-init pointers and lengths to 1321 * default values. 1322 */ 1323 m_new = m; 1324 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1325 m_new->m_data = m_new->m_ext.ext_buf; 1326 } 1327 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1328 if (align != 0) { 1329 DPRINTFN(1,("align = %d\n", align)); 1330 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1331 } 1332 1333 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1334 r = c->mvgbe_desc; 1335 c->mvgbe_mbuf = m_new; 1336 r->bufptr = dmamap->dm_segs[0].ds_addr + 1337 (((vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf)); 1338 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1339 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1340 1341 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1342 1343 return 0; 1344 } 1345 1346 /* 1347 * Memory management for jumbo frames. 1348 */ 1349 1350 static int 1351 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1352 { 1353 char *ptr, *kva; 1354 bus_dma_segment_t seg; 1355 int i, rseg, state, error; 1356 struct mvgbe_jpool_entry *entry; 1357 1358 state = error = 0; 1359 1360 /* Grab a big chunk o' storage. */ 1361 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1362 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1363 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1364 return ENOBUFS; 1365 } 1366 1367 state = 1; 1368 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1369 (void **)&kva, BUS_DMA_NOWAIT)) { 1370 aprint_error_dev(sc->sc_dev, 1371 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1372 error = ENOBUFS; 1373 goto out; 1374 } 1375 1376 state = 2; 1377 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1378 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1379 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1380 error = ENOBUFS; 1381 goto out; 1382 } 1383 1384 state = 3; 1385 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1386 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1387 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1388 error = ENOBUFS; 1389 goto out; 1390 } 1391 1392 state = 4; 1393 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1394 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1395 1396 LIST_INIT(&sc->sc_jfree_listhead); 1397 LIST_INIT(&sc->sc_jinuse_listhead); 1398 1399 /* 1400 * Now divide it up into 9K pieces and save the addresses 1401 * in an array. 1402 */ 1403 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1404 for (i = 0; i < MVGBE_JSLOTS; i++) { 1405 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1406 ptr += MVGBE_JLEN; 1407 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1408 if (entry == NULL) { 1409 aprint_error_dev(sc->sc_dev, 1410 "no memory for jumbo buffer queue!\n"); 1411 error = ENOBUFS; 1412 goto out; 1413 } 1414 entry->slot = i; 1415 if (i) 1416 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1417 jpool_entries); 1418 else 1419 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1420 jpool_entries); 1421 } 1422 out: 1423 if (error != 0) { 1424 switch (state) { 1425 case 4: 1426 bus_dmamap_unload(sc->sc_dmat, 1427 sc->sc_cdata.mvgbe_rx_jumbo_map); 1428 case 3: 1429 bus_dmamap_destroy(sc->sc_dmat, 1430 sc->sc_cdata.mvgbe_rx_jumbo_map); 1431 case 2: 1432 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1433 case 1: 1434 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1435 break; 1436 default: 1437 break; 1438 } 1439 } 1440 1441 return error; 1442 } 1443 1444 /* 1445 * Allocate a jumbo buffer. 1446 */ 1447 static void * 1448 mvgbe_jalloc(struct mvgbe_softc *sc) 1449 { 1450 struct mvgbe_jpool_entry *entry; 1451 1452 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1453 1454 if (entry == NULL) 1455 return NULL; 1456 1457 LIST_REMOVE(entry, jpool_entries); 1458 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1459 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1460 } 1461 1462 /* 1463 * Release a jumbo buffer. 1464 */ 1465 static void 1466 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1467 { 1468 struct mvgbe_jpool_entry *entry; 1469 struct mvgbe_softc *sc; 1470 int i, s; 1471 1472 /* Extract the softc struct pointer. */ 1473 sc = (struct mvgbe_softc *)arg; 1474 1475 if (sc == NULL) 1476 panic("%s: can't find softc pointer!", __func__); 1477 1478 /* calculate the slot this buffer belongs to */ 1479 1480 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1481 1482 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1483 panic("%s: asked to free buffer that we don't manage!", 1484 __func__); 1485 1486 s = splvm(); 1487 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1488 if (entry == NULL) 1489 panic("%s: buffer not in use!", __func__); 1490 entry->slot = i; 1491 LIST_REMOVE(entry, jpool_entries); 1492 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1493 1494 if (__predict_true(m != NULL)) 1495 pool_cache_put(mb_cache, m); 1496 splx(s); 1497 } 1498 1499 static int 1500 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1501 uint32_t *txidx) 1502 { 1503 struct mvgbe_tx_desc *f = NULL; 1504 struct mvgbe_txmap_entry *entry; 1505 bus_dma_segment_t *txseg; 1506 bus_dmamap_t txmap; 1507 uint32_t first, current, last, cmdsts = 0; 1508 int m_csumflags, i; 1509 bool needs_defrag = false; 1510 1511 DPRINTFN(3, ("mvgbe_encap\n")); 1512 1513 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1514 if (entry == NULL) { 1515 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1516 return ENOBUFS; 1517 } 1518 txmap = entry->dmamap; 1519 1520 first = current = last = *txidx; 1521 1522 /* 1523 * Preserve m_pkthdr.csum_flags here since m_head might be 1524 * updated by m_defrag() 1525 */ 1526 m_csumflags = m_head->m_pkthdr.csum_flags; 1527 1528 do_defrag: 1529 if (__predict_false(needs_defrag == true)) { 1530 /* A small unaligned segment was detected. */ 1531 struct mbuf *m_new; 1532 m_new = m_defrag(m_head, M_DONTWAIT); 1533 if (m_new == NULL) 1534 return EFBIG; 1535 m_head = m_new; 1536 } 1537 1538 /* 1539 * Start packing the mbufs in this chain into 1540 * the fragment pointers. Stop when we run out 1541 * of fragments or hit the end of the mbuf chain. 1542 */ 1543 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1544 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1545 return ENOBUFS; 1546 } 1547 1548 txseg = txmap->dm_segs; 1549 1550 if (__predict_true(needs_defrag == false)) { 1551 /* 1552 * Detect rarely encountered DMA limitation. 1553 */ 1554 for (i = 0; i < txmap->dm_nsegs; i++) { 1555 if (((txseg[i].ds_addr & 7) != 0) && 1556 (txseg[i].ds_len <= 8) && 1557 (txseg[i].ds_len >= 1) 1558 ) { 1559 txseg = NULL; 1560 bus_dmamap_unload(sc->sc_dmat, txmap); 1561 needs_defrag = true; 1562 goto do_defrag; 1563 } 1564 } 1565 } 1566 1567 /* Sync the DMA map. */ 1568 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1569 BUS_DMASYNC_PREWRITE); 1570 1571 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1572 MVGBE_TX_RING_CNT) { 1573 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1574 bus_dmamap_unload(sc->sc_dmat, txmap); 1575 return ENOBUFS; 1576 } 1577 1578 1579 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1580 1581 for (i = 0; i < txmap->dm_nsegs; i++) { 1582 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1583 f->bufptr = txseg[i].ds_addr; 1584 f->bytecnt = txseg[i].ds_len; 1585 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1586 last = current; 1587 current = MVGBE_TX_RING_NEXT(current); 1588 } 1589 1590 if (m_csumflags & M_CSUM_IPv4) 1591 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1592 if (m_csumflags & M_CSUM_TCPv4) 1593 cmdsts |= 1594 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1595 if (m_csumflags & M_CSUM_UDPv4) 1596 cmdsts |= 1597 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1598 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1599 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1600 1601 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1602 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1603 } 1604 if (txmap->dm_nsegs == 1) 1605 f->cmdsts = cmdsts | 1606 MVGBE_BUFFER_OWNED_BY_DMA | 1607 MVGBE_TX_GENERATE_CRC | 1608 MVGBE_TX_ENABLE_INTERRUPT | 1609 MVGBE_TX_ZERO_PADDING | 1610 MVGBE_TX_FIRST_DESC | 1611 MVGBE_TX_LAST_DESC; 1612 else { 1613 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1614 f->cmdsts = cmdsts | 1615 MVGBE_BUFFER_OWNED_BY_DMA | 1616 MVGBE_TX_GENERATE_CRC | 1617 MVGBE_TX_FIRST_DESC; 1618 1619 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1620 f->cmdsts = 1621 MVGBE_BUFFER_OWNED_BY_DMA | 1622 MVGBE_TX_ENABLE_INTERRUPT | 1623 MVGBE_TX_ZERO_PADDING | 1624 MVGBE_TX_LAST_DESC; 1625 } 1626 1627 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1628 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1629 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1630 1631 /* Sync descriptors before handing to chip */ 1632 MVGBE_CDTXSYNC(sc, *txidx, txmap->dm_nsegs, 1633 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1634 1635 sc->sc_cdata.mvgbe_tx_cnt += i; 1636 *txidx = current; 1637 1638 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1639 1640 return 0; 1641 } 1642 1643 static void 1644 mvgbe_rxeof(struct mvgbe_softc *sc) 1645 { 1646 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1647 struct mvgbe_rx_desc *cur_rx; 1648 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1649 struct mbuf *m; 1650 bus_dmamap_t dmamap; 1651 uint32_t rxstat; 1652 int idx, cur, total_len; 1653 1654 idx = sc->sc_cdata.mvgbe_rx_prod; 1655 1656 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1657 1658 for (;;) { 1659 cur = idx; 1660 1661 /* Sync the descriptor */ 1662 MVGBE_CDRXSYNC(sc, idx, 1663 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1664 1665 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1666 1667 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1668 MVGBE_BUFFER_OWNED_BY_DMA) { 1669 /* Invalidate the descriptor -- it's not ready yet */ 1670 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1671 sc->sc_cdata.mvgbe_rx_prod = idx; 1672 break; 1673 } 1674 #ifdef DIAGNOSTIC 1675 if ((cur_rx->cmdsts & 1676 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1677 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1678 panic( 1679 "mvgbe_rxeof: buffer size is smaller than packet"); 1680 #endif 1681 1682 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1683 1684 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1685 BUS_DMASYNC_POSTREAD); 1686 1687 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1688 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1689 total_len = cur_rx->bytecnt; 1690 rxstat = cur_rx->cmdsts; 1691 1692 cdata->mvgbe_rx_map[idx] = NULL; 1693 1694 idx = MVGBE_RX_RING_NEXT(idx); 1695 1696 if (rxstat & MVGBE_ERROR_SUMMARY) { 1697 #if 0 1698 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1699 1700 if (err == MVGBE_RX_CRC_ERROR) 1701 ifp->if_ierrors++; 1702 if (err == MVGBE_RX_OVERRUN_ERROR) 1703 ifp->if_ierrors++; 1704 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1705 ifp->if_ierrors++; 1706 if (err == MVGBE_RX_RESOURCE_ERROR) 1707 ifp->if_ierrors++; 1708 #else 1709 ifp->if_ierrors++; 1710 #endif 1711 mvgbe_newbuf(sc, cur, m, dmamap); 1712 continue; 1713 } 1714 1715 if (total_len <= MVGBE_RX_CSUM_MIN_BYTE) /* XXX documented? */ 1716 goto sw_csum; 1717 1718 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1719 /* Check IPv4 header checksum */ 1720 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1721 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 1722 m->m_pkthdr.csum_flags |= 1723 M_CSUM_IPv4_BAD; 1724 /* Check TCPv4/UDPv4 checksum */ 1725 if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1726 MVGBE_RX_L4_TYPE_TCP) 1727 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1728 else if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1729 MVGBE_RX_L4_TYPE_UDP) 1730 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1731 if (!(rxstat & MVGBE_RX_L4_CHECKSUM)) 1732 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1733 } 1734 sw_csum: 1735 1736 /* 1737 * Try to allocate a new jumbo buffer. If that 1738 * fails, copy the packet to mbufs and put the 1739 * jumbo buffer back in the ring so it can be 1740 * re-used. If allocating mbufs fails, then we 1741 * have to drop the packet. 1742 */ 1743 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 1744 struct mbuf *m0; 1745 1746 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 1747 mvgbe_newbuf(sc, cur, m, dmamap); 1748 if (m0 == NULL) { 1749 aprint_error_ifnet(ifp, 1750 "no receive buffers available --" 1751 " packet dropped!\n"); 1752 ifp->if_ierrors++; 1753 continue; 1754 } 1755 m = m0; 1756 } else { 1757 m->m_pkthdr.rcvif = ifp; 1758 m->m_pkthdr.len = m->m_len = total_len; 1759 } 1760 1761 /* Skip on first 2byte (HW header) */ 1762 m_adj(m, MVGBE_HWHEADER_SIZE); 1763 m->m_flags |= M_HASFCS; 1764 1765 ifp->if_ipackets++; 1766 1767 bpf_mtap(ifp, m); 1768 1769 /* pass it on. */ 1770 (*ifp->if_input)(ifp, m); 1771 } 1772 } 1773 1774 static void 1775 mvgbe_txeof(struct mvgbe_softc *sc) 1776 { 1777 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1778 struct mvgbe_tx_desc *cur_tx; 1779 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1780 struct mvgbe_txmap_entry *entry; 1781 int idx; 1782 1783 DPRINTFN(3, ("mvgbe_txeof\n")); 1784 1785 /* 1786 * Go through our tx ring and free mbufs for those 1787 * frames that have been sent. 1788 */ 1789 idx = cdata->mvgbe_tx_cons; 1790 while (idx != cdata->mvgbe_tx_prod) { 1791 MVGBE_CDTXSYNC(sc, idx, 1, 1792 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1793 1794 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 1795 #ifdef MVGBE_DEBUG 1796 if (mvgbe_debug >= 3) 1797 mvgbe_dump_txdesc(cur_tx, idx); 1798 #endif 1799 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1800 MVGBE_BUFFER_OWNED_BY_DMA) { 1801 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 1802 break; 1803 } 1804 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 1805 ifp->if_opackets++; 1806 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 1807 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 1808 1809 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 1810 ifp->if_collisions++; 1811 if (err == MVGBE_TX_UNDERRUN_ERROR) 1812 ifp->if_oerrors++; 1813 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 1814 ifp->if_collisions++; 1815 } 1816 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 1817 entry = cdata->mvgbe_tx_map[idx]; 1818 1819 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 1820 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 1821 1822 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 1823 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1824 1825 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 1826 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 1827 cdata->mvgbe_tx_map[idx] = NULL; 1828 } 1829 cdata->mvgbe_tx_cnt--; 1830 idx = MVGBE_TX_RING_NEXT(idx); 1831 } 1832 if (cdata->mvgbe_tx_cnt == 0) 1833 ifp->if_timer = 0; 1834 1835 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 1836 ifp->if_flags &= ~IFF_OACTIVE; 1837 1838 cdata->mvgbe_tx_cons = idx; 1839 } 1840 1841 static uint8_t 1842 mvgbe_crc8(const uint8_t *data, size_t size) 1843 { 1844 int bit; 1845 uint8_t byte; 1846 uint8_t crc = 0; 1847 const uint8_t poly = 0x07; 1848 1849 while(size--) 1850 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 1851 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 1852 1853 return crc; 1854 } 1855 1856 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 1857 1858 static void 1859 mvgbe_filter_setup(struct mvgbe_softc *sc) 1860 { 1861 struct ethercom *ec = &sc->sc_ethercom; 1862 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 1863 struct ether_multi *enm; 1864 struct ether_multistep step; 1865 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 1866 uint32_t pxc; 1867 int i; 1868 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 1869 1870 memset(dfut, 0, sizeof(dfut)); 1871 memset(dfsmt, 0, sizeof(dfsmt)); 1872 memset(dfomt, 0, sizeof(dfomt)); 1873 1874 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1875 goto allmulti; 1876 } 1877 1878 ETHER_FIRST_MULTI(step, ec, enm); 1879 while (enm != NULL) { 1880 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1881 /* ranges are complex and somewhat rare */ 1882 goto allmulti; 1883 } 1884 /* chip handles some IPv4 multicast specially */ 1885 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 1886 i = enm->enm_addrlo[5]; 1887 dfsmt[i>>2] = 1888 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1889 } else { 1890 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 1891 dfomt[i>>2] = 1892 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1893 } 1894 1895 ETHER_NEXT_MULTI(step, enm); 1896 } 1897 goto set; 1898 1899 allmulti: 1900 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1901 for (i = 0; i < MVGBE_NDFSMT; i++) { 1902 dfsmt[i] = dfomt[i] = 1903 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1904 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1905 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1906 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1907 } 1908 } 1909 1910 set: 1911 pxc = MVGBE_READ(sc, MVGBE_PXC); 1912 pxc &= ~MVGBE_PXC_UPM; 1913 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 1914 if (ifp->if_flags & IFF_BROADCAST) { 1915 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 1916 } 1917 if (ifp->if_flags & IFF_PROMISC) { 1918 pxc |= MVGBE_PXC_UPM; 1919 } 1920 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 1921 1922 /* Set Destination Address Filter Unicast Table */ 1923 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 1924 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1925 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 1926 1927 /* Set Destination Address Filter Multicast Tables */ 1928 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 1929 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 1930 } 1931 1932 #ifdef MVGBE_DEBUG 1933 static void 1934 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 1935 { 1936 #define DESC_PRINT(X) \ 1937 if (X) \ 1938 printf("txdesc[%d]." #X "=%#x\n", idx, X); 1939 1940 #if BYTE_ORDER == BIG_ENDIAN 1941 DESC_PRINT(desc->bytecnt); 1942 DESC_PRINT(desc->l4ichk); 1943 DESC_PRINT(desc->cmdsts); 1944 DESC_PRINT(desc->nextdescptr); 1945 DESC_PRINT(desc->bufptr); 1946 #else /* LITTLE_ENDIAN */ 1947 DESC_PRINT(desc->cmdsts); 1948 DESC_PRINT(desc->l4ichk); 1949 DESC_PRINT(desc->bytecnt); 1950 DESC_PRINT(desc->bufptr); 1951 DESC_PRINT(desc->nextdescptr); 1952 #endif 1953 #undef DESC_PRINT 1954 } 1955 #endif 1956
Indexes created Wed Oct 01 07:09:59 GMT 2025