if_mvgbe.c revision 1.16.2.1
1 /* $NetBSD: if_mvgbe.c,v 1.16.2.1 2012/11/20 22:26:03 riz Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.16.2.1 2012/11/20 22:26:03 riz Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/device.h> 34 #include <sys/endian.h> 35 #include <sys/errno.h> 36 #include <sys/kernel.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 #include <sys/sockio.h> 40 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 #include <dev/marvell/mvgbereg.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/in_systm.h> 51 #include <netinet/ip.h> 52 53 #include <net/bpf.h> 54 #include <sys/rnd.h> 55 56 #include <dev/mii/mii.h> 57 #include <dev/mii/miivar.h> 58 59 #include "locators.h" 60 61 /* #define MVGBE_DEBUG 3 */ 62 #ifdef MVGBE_DEBUG 63 #define DPRINTF(x) if (mvgbe_debug) printf x 64 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 65 int mvgbe_debug = MVGBE_DEBUG; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n,x) 69 #endif 70 71 72 #define MVGBE_READ(sc, reg) \ 73 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 74 #define MVGBE_WRITE(sc, reg, val) \ 75 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 76 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 77 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 78 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 79 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 80 81 #define MVGBE_TX_RING_CNT 256 82 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 83 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 84 #define MVGBE_RX_RING_CNT 256 85 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 86 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 87 88 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 89 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 90 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 91 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 92 93 #define MVGBE_JSLOTS 384 /* XXXX */ 94 #define MVGBE_JLEN \ 95 ((MVGBE_MRU + MVGBE_HWHEADER_SIZE + MVGBE_RXBUF_ALIGN - 1) & \ 96 ~MVGBE_RXBUF_MASK) 97 #define MVGBE_NTXSEG 30 98 #define MVGBE_JPAGESZ PAGE_SIZE 99 #define MVGBE_RESID \ 100 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 101 #define MVGBE_JMEM \ 102 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 103 104 #define MVGBE_TX_RING_ADDR(sc, i) \ 105 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 106 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 107 108 #define MVGBE_RX_RING_ADDR(sc, i) \ 109 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 110 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 111 112 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 113 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 114 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 115 116 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 117 do { \ 118 int __x, __n; \ 119 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 120 \ 121 __x = (x); \ 122 __n = (n); \ 123 \ 124 /* If it will wrap around, sync to the end of the ring. */ \ 125 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 126 bus_dmamap_sync((sc)->sc_dmat, \ 127 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 128 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 129 __n -= (MVGBE_TX_RING_CNT - __x); \ 130 __x = 0; \ 131 } \ 132 \ 133 /* Now sync whatever is left. */ \ 134 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 135 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 136 } while (0 /*CONSTCOND*/) 137 138 #define MVGBE_CDRXSYNC(sc, x, ops) \ 139 do { \ 140 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 141 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 142 } while (/*CONSTCOND*/0) 143 144 145 struct mvgbe_jpool_entry { 146 int slot; 147 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 148 }; 149 150 struct mvgbe_chain { 151 void *mvgbe_desc; 152 struct mbuf *mvgbe_mbuf; 153 struct mvgbe_chain *mvgbe_next; 154 }; 155 156 struct mvgbe_txmap_entry { 157 bus_dmamap_t dmamap; 158 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 159 }; 160 161 struct mvgbe_chain_data { 162 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 163 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 164 int mvgbe_tx_prod; 165 int mvgbe_tx_cons; 166 int mvgbe_tx_cnt; 167 168 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 169 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 170 bus_dmamap_t mvgbe_rx_jumbo_map; 171 int mvgbe_rx_prod; 172 int mvgbe_rx_cons; 173 int mvgbe_rx_cnt; 174 175 /* Stick the jumbo mem management stuff here too. */ 176 void *mvgbe_jslots[MVGBE_JSLOTS]; 177 void *mvgbe_jumbo_buf; 178 }; 179 180 struct mvgbe_ring_data { 181 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 182 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 183 }; 184 185 struct mvgbec_softc { 186 device_t sc_dev; 187 188 bus_space_tag_t sc_iot; 189 bus_space_handle_t sc_ioh; 190 191 kmutex_t sc_mtx; 192 193 int sc_flags; 194 }; 195 196 struct mvgbe_softc { 197 device_t sc_dev; 198 int sc_port; 199 200 bus_space_tag_t sc_iot; 201 bus_space_handle_t sc_ioh; 202 bus_space_handle_t sc_dafh; /* dest address filter handle */ 203 bus_dma_tag_t sc_dmat; 204 205 struct ethercom sc_ethercom; 206 struct mii_data sc_mii; 207 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 208 209 callout_t sc_tick_ch; /* tick callout */ 210 211 struct mvgbe_chain_data sc_cdata; 212 struct mvgbe_ring_data *sc_rdata; 213 bus_dmamap_t sc_ring_map; 214 int sc_if_flags; 215 int sc_wdogsoft; 216 217 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 218 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 219 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 220 221 krndsource_t sc_rnd_source; 222 }; 223 224 225 /* Gigabit Ethernet Unit Global part functions */ 226 227 static int mvgbec_match(device_t, struct cfdata *, void *); 228 static void mvgbec_attach(device_t, device_t, void *); 229 230 static int mvgbec_print(void *, const char *); 231 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 232 233 /* MII funcstions */ 234 static int mvgbec_miibus_readreg(device_t, int, int); 235 static void mvgbec_miibus_writereg(device_t, int, int, int); 236 static void mvgbec_miibus_statchg(device_t); 237 238 static void mvgbec_wininit(struct mvgbec_softc *); 239 240 /* Gigabit Ethernet Port part functions */ 241 242 static int mvgbe_match(device_t, struct cfdata *, void *); 243 static void mvgbe_attach(device_t, device_t, void *); 244 245 static void mvgbe_tick(void *); 246 static int mvgbe_intr(void *); 247 248 static void mvgbe_start(struct ifnet *); 249 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 250 static int mvgbe_init(struct ifnet *); 251 static void mvgbe_stop(struct ifnet *, int); 252 static void mvgbe_watchdog(struct ifnet *); 253 254 static int mvgbe_ifflags_cb(struct ethercom *); 255 256 static int mvgbe_mediachange(struct ifnet *); 257 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 258 259 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 260 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 261 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 262 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 263 static void *mvgbe_jalloc(struct mvgbe_softc *); 264 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 265 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 266 static void mvgbe_rxeof(struct mvgbe_softc *); 267 static void mvgbe_txeof(struct mvgbe_softc *); 268 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 269 static void mvgbe_filter_setup(struct mvgbe_softc *); 270 #ifdef MVGBE_DEBUG 271 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 272 #endif 273 274 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 275 mvgbec_match, mvgbec_attach, NULL, NULL); 276 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 277 mvgbec_match, mvgbec_attach, NULL, NULL); 278 279 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 280 mvgbe_match, mvgbe_attach, NULL, NULL); 281 282 device_t mvgbec0 = NULL; 283 284 struct mvgbe_port { 285 int model; 286 int unit; 287 int ports; 288 int irqs[3]; 289 int flags; 290 #define FLAGS_FIX_TQTB (1 << 0) 291 #define FLAGS_FIX_MTU (1 << 1) 292 } mvgbe_ports[] = { 293 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 294 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 295 #if 0 296 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 297 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 298 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 299 #endif 300 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 301 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, FLAGS_FIX_MTU }, 302 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, FLAGS_FIX_MTU }, 303 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, FLAGS_FIX_MTU }, 304 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, FLAGS_FIX_MTU }, 305 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, FLAGS_FIX_MTU }, 306 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, FLAGS_FIX_MTU }, 307 308 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 309 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 310 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 14 }, FLAGS_FIX_TQTB }, 311 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 312 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB }, 313 314 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 315 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 316 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 317 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 318 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB }, 319 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB }, 320 }; 321 322 323 /* ARGSUSED */ 324 static int 325 mvgbec_match(device_t parent, cfdata_t match, void *aux) 326 { 327 struct marvell_attach_args *mva = aux; 328 int i; 329 330 if (strcmp(mva->mva_name, match->cf_name) != 0) 331 return 0; 332 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 333 return 0; 334 335 for (i = 0; i < __arraycount(mvgbe_ports); i++) 336 if (mva->mva_model == mvgbe_ports[i].model) { 337 mva->mva_size = MVGBE_SIZE; 338 return 1; 339 } 340 return 0; 341 } 342 343 /* ARGSUSED */ 344 static void 345 mvgbec_attach(device_t parent, device_t self, void *aux) 346 { 347 struct mvgbec_softc *csc = device_private(self); 348 struct marvell_attach_args *mva = aux, gbea; 349 struct mvgbe_softc *port; 350 struct mii_softc *mii; 351 device_t child; 352 uint32_t phyaddr; 353 int i, j; 354 355 aprint_naive("\n"); 356 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 357 358 csc->sc_dev = self; 359 csc->sc_iot = mva->mva_iot; 360 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 361 mva->mva_size, &csc->sc_ioh)) { 362 aprint_error_dev(self, "Cannot map registers\n"); 363 return; 364 } 365 366 if (mvgbec0 == NULL) 367 mvgbec0 = self; 368 369 phyaddr = 0; 370 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 371 372 mutex_init(&csc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 373 374 /* Disable and clear Gigabit Ethernet Unit interrupts */ 375 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 376 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 377 378 mvgbec_wininit(csc); 379 380 memset(&gbea, 0, sizeof(gbea)); 381 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 382 if (mvgbe_ports[i].model != mva->mva_model || 383 mvgbe_ports[i].unit != mva->mva_unit) 384 continue; 385 386 csc->sc_flags = mvgbe_ports[i].flags; 387 388 for (j = 0; j < mvgbe_ports[i].ports; j++) { 389 gbea.mva_name = "mvgbe"; 390 gbea.mva_model = mva->mva_model; 391 gbea.mva_iot = csc->sc_iot; 392 gbea.mva_ioh = csc->sc_ioh; 393 gbea.mva_unit = j; 394 gbea.mva_dmat = mva->mva_dmat; 395 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 396 child = config_found_sm_loc(csc->sc_dev, "mvgbec", NULL, 397 &gbea, mvgbec_print, mvgbec_search); 398 if (child) { 399 port = device_private(child); 400 mii = LIST_FIRST(&port->sc_mii.mii_phys); 401 phyaddr |= MVGBE_PHYADDR_PHYAD(j, mii->mii_phy); 402 } 403 } 404 break; 405 } 406 MVGBE_WRITE(csc, MVGBE_PHYADDR, phyaddr); 407 } 408 409 static int 410 mvgbec_print(void *aux, const char *pnp) 411 { 412 struct marvell_attach_args *gbea = aux; 413 414 if (pnp) 415 aprint_normal("%s at %s port %d", 416 gbea->mva_name, pnp, gbea->mva_unit); 417 else { 418 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 419 aprint_normal(" port %d", gbea->mva_unit); 420 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 421 aprint_normal(" irq %d", gbea->mva_irq); 422 } 423 return UNCONF; 424 } 425 426 /* ARGSUSED */ 427 static int 428 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 429 { 430 struct marvell_attach_args *gbea = aux; 431 432 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 433 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 434 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 435 436 return config_match(parent, cf, aux); 437 } 438 439 static int 440 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 441 { 442 struct mvgbe_softc *sc = device_private(dev); 443 struct mvgbec_softc *csc; 444 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 445 uint32_t smi, val; 446 int i; 447 448 if (mvgbec0 == NULL) { 449 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 450 return -1; 451 } 452 csc = device_private(mvgbec0); 453 454 mutex_enter(&csc->sc_mtx); 455 456 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 457 DELAY(1); 458 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 459 break; 460 } 461 if (i == MVGBE_PHY_TIMEOUT) { 462 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 463 mutex_exit(&csc->sc_mtx); 464 return -1; 465 } 466 467 smi = 468 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 469 MVGBE_WRITE(csc, MVGBE_SMI, smi); 470 471 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 472 DELAY(1); 473 smi = MVGBE_READ(csc, MVGBE_SMI); 474 if (smi & MVGBE_SMI_READVALID) 475 break; 476 } 477 478 mutex_exit(&csc->sc_mtx); 479 480 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 481 i, MVGBE_PHY_TIMEOUT)); 482 483 val = smi & MVGBE_SMI_DATA_MASK; 484 485 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 486 phy, reg, val)); 487 488 return val; 489 } 490 491 static void 492 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 493 { 494 struct mvgbe_softc *sc = device_private(dev); 495 struct mvgbec_softc *csc; 496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 497 uint32_t smi; 498 int i; 499 500 if (mvgbec0 == NULL) { 501 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 502 return; 503 } 504 csc = device_private(mvgbec0); 505 506 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 507 phy, reg, val)); 508 509 mutex_enter(&csc->sc_mtx); 510 511 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 512 DELAY(1); 513 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 514 break; 515 } 516 if (i == MVGBE_PHY_TIMEOUT) { 517 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 518 mutex_exit(&csc->sc_mtx); 519 return; 520 } 521 522 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 523 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 524 MVGBE_WRITE(csc, MVGBE_SMI, smi); 525 526 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 527 DELAY(1); 528 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 529 break; 530 } 531 532 mutex_exit(&csc->sc_mtx); 533 534 if (i == MVGBE_PHY_TIMEOUT) 535 aprint_error_ifnet(ifp, "phy write timed out\n"); 536 } 537 538 static void 539 mvgbec_miibus_statchg(device_t dev) 540 { 541 542 /* nothing to do */ 543 } 544 545 546 static void 547 mvgbec_wininit(struct mvgbec_softc *sc) 548 { 549 device_t pdev = device_parent(sc->sc_dev); 550 uint64_t base; 551 uint32_t en, ac, size; 552 int window, target, attr, rv, i; 553 static int tags[] = { 554 MARVELL_TAG_SDRAM_CS0, 555 MARVELL_TAG_SDRAM_CS1, 556 MARVELL_TAG_SDRAM_CS2, 557 MARVELL_TAG_SDRAM_CS3, 558 559 MARVELL_TAG_UNDEFINED, 560 }; 561 562 /* First disable all address decode windows */ 563 en = MVGBE_BARE_EN_MASK; 564 MVGBE_WRITE(sc, MVGBE_BARE, en); 565 566 ac = 0; 567 for (window = 0, i = 0; 568 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 569 rv = marvell_winparams_by_tag(pdev, tags[i], 570 &target, &attr, &base, &size); 571 if (rv != 0 || size == 0) 572 continue; 573 574 if (base > 0xffffffffULL) { 575 if (window >= MVGBE_NREMAP) { 576 aprint_error_dev(sc->sc_dev, 577 "can't remap window %d\n", window); 578 continue; 579 } 580 MVGBE_WRITE(sc, MVGBE_HA(window), 581 (base >> 32) & 0xffffffff); 582 } 583 584 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 585 MVGBE_BASEADDR_TARGET(target) | 586 MVGBE_BASEADDR_ATTR(attr) | 587 MVGBE_BASEADDR_BASE(base)); 588 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 589 590 en &= ~(1 << window); 591 /* set full access (r/w) */ 592 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 593 window++; 594 } 595 /* allow to access decode window */ 596 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 597 598 MVGBE_WRITE(sc, MVGBE_BARE, en); 599 } 600 601 602 /* ARGSUSED */ 603 static int 604 mvgbe_match(device_t parent, cfdata_t match, void *aux) 605 { 606 struct marvell_attach_args *mva = aux; 607 uint32_t pbase, maddrh, maddrl; 608 609 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 610 maddrh = 611 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 612 maddrl = 613 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 614 if ((maddrh | maddrl) == 0) 615 return 0; 616 617 return 1; 618 } 619 620 /* ARGSUSED */ 621 static void 622 mvgbe_attach(device_t parent, device_t self, void *aux) 623 { 624 struct mvgbe_softc *sc = device_private(self); 625 struct marvell_attach_args *mva = aux; 626 struct mvgbe_txmap_entry *entry; 627 struct ifnet *ifp; 628 bus_dma_segment_t seg; 629 bus_dmamap_t dmamap; 630 int rseg, i; 631 uint32_t maddrh, maddrl; 632 void *kva; 633 634 aprint_naive("\n"); 635 aprint_normal("\n"); 636 637 sc->sc_dev = self; 638 sc->sc_port = mva->mva_unit; 639 sc->sc_iot = mva->mva_iot; 640 callout_init(&sc->sc_tick_ch, 0); 641 callout_setfunc(&sc->sc_tick_ch, mvgbe_tick, sc); 642 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 643 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 644 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 645 aprint_error_dev(self, "Cannot map registers\n"); 646 return; 647 } 648 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 649 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 650 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 651 aprint_error_dev(self, 652 "Cannot map destination address filter registers\n"); 653 return; 654 } 655 sc->sc_dmat = mva->mva_dmat; 656 657 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 658 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 659 sc->sc_enaddr[0] = maddrh >> 24; 660 sc->sc_enaddr[1] = maddrh >> 16; 661 sc->sc_enaddr[2] = maddrh >> 8; 662 sc->sc_enaddr[3] = maddrh >> 0; 663 sc->sc_enaddr[4] = maddrl >> 8; 664 sc->sc_enaddr[5] = maddrl >> 0; 665 aprint_normal_dev(self, "Ethernet address %s\n", 666 ether_sprintf(sc->sc_enaddr)); 667 668 /* clear all ethernet port interrupts */ 669 MVGBE_WRITE(sc, MVGBE_IC, 0); 670 MVGBE_WRITE(sc, MVGBE_ICE, 0); 671 672 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 673 674 /* Allocate the descriptor queues. */ 675 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 676 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 677 aprint_error_dev(self, "can't alloc rx buffers\n"); 678 return; 679 } 680 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 681 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 682 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 683 (u_long)sizeof(struct mvgbe_ring_data)); 684 goto fail1; 685 } 686 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 687 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 688 &sc->sc_ring_map)) { 689 aprint_error_dev(self, "can't create dma map\n"); 690 goto fail2; 691 } 692 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 693 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 694 aprint_error_dev(self, "can't load dma map\n"); 695 goto fail3; 696 } 697 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 698 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 699 700 SIMPLEQ_INIT(&sc->sc_txmap_head); 701 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 702 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 703 704 if (bus_dmamap_create(sc->sc_dmat, 705 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 706 BUS_DMA_NOWAIT, &dmamap)) { 707 aprint_error_dev(self, "Can't create TX dmamap\n"); 708 goto fail4; 709 } 710 711 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 712 if (!entry) { 713 aprint_error_dev(self, "Can't alloc txmap entry\n"); 714 bus_dmamap_destroy(sc->sc_dmat, dmamap); 715 goto fail4; 716 } 717 entry->dmamap = dmamap; 718 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 719 } 720 721 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 722 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 723 724 /* 725 * We can support 802.1Q VLAN-sized frames and jumbo 726 * Ethernet frames. 727 */ 728 sc->sc_ethercom.ec_capabilities |= 729 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 730 731 /* Try to allocate memory for jumbo buffers. */ 732 if (mvgbe_alloc_jumbo_mem(sc)) { 733 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 734 goto fail4; 735 } 736 737 ifp = &sc->sc_ethercom.ec_if; 738 ifp->if_softc = sc; 739 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 740 ifp->if_start = mvgbe_start; 741 ifp->if_ioctl = mvgbe_ioctl; 742 ifp->if_init = mvgbe_init; 743 ifp->if_stop = mvgbe_stop; 744 ifp->if_watchdog = mvgbe_watchdog; 745 /* 746 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 747 */ 748 sc->sc_ethercom.ec_if.if_capabilities |= 749 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 750 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 751 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 752 /* 753 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 754 */ 755 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 756 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 757 IFQ_SET_READY(&ifp->if_snd); 758 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 759 760 mvgbe_stop(ifp, 0); 761 762 /* 763 * Do MII setup. 764 */ 765 sc->sc_mii.mii_ifp = ifp; 766 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 767 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 768 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 769 770 sc->sc_ethercom.ec_mii = &sc->sc_mii; 771 ifmedia_init(&sc->sc_mii.mii_media, 0, 772 mvgbe_mediachange, mvgbe_mediastatus); 773 mii_attach(self, &sc->sc_mii, 0xffffffff, 774 MII_PHY_ANY, parent == mvgbec0 ? 0 : 1, 0); 775 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 776 aprint_error_dev(self, "no PHY found!\n"); 777 ifmedia_add(&sc->sc_mii.mii_media, 778 IFM_ETHER|IFM_MANUAL, 0, NULL); 779 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 780 } else 781 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 782 783 /* 784 * Call MI attach routines. 785 */ 786 if_attach(ifp); 787 788 ether_ifattach(ifp, sc->sc_enaddr); 789 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 790 791 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 792 RND_TYPE_NET, 0); 793 794 return; 795 796 fail4: 797 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 798 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 799 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 800 } 801 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 802 fail3: 803 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 804 fail2: 805 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 806 fail1: 807 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 808 return; 809 } 810 811 812 static void 813 mvgbe_tick(void *arg) 814 { 815 struct mvgbe_softc *sc = arg; 816 struct mii_data *mii = &sc->sc_mii; 817 int s; 818 819 s = splnet(); 820 mii_tick(mii); 821 /* Need more work */ 822 splx(s); 823 824 callout_schedule(&sc->sc_tick_ch, hz); 825 } 826 827 static int 828 mvgbe_intr(void *arg) 829 { 830 struct mvgbe_softc *sc = arg; 831 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 832 uint32_t ic, ice, datum = 0; 833 int claimed = 0; 834 835 for (;;) { 836 ice = MVGBE_READ(sc, MVGBE_ICE); 837 ic = MVGBE_READ(sc, MVGBE_IC); 838 839 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 840 if (ic == 0 && ice == 0) 841 break; 842 843 datum = datum ^ ic ^ ice; 844 845 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 846 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 847 848 claimed = 1; 849 850 if (!(ifp->if_flags & IFF_RUNNING)) 851 break; 852 853 if (ice & MVGBE_ICE_LINKCHG) { 854 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 855 /* Enable port RX and TX. */ 856 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 857 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 858 } else { 859 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 860 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 861 } 862 863 /* Notify link change event to mii layer */ 864 mii_pollstat(&sc->sc_mii); 865 } 866 867 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 868 mvgbe_rxeof(sc); 869 870 if (ice & (MVGBE_ICE_TXBUF | MVGBE_ICE_TXERR)) 871 mvgbe_txeof(sc); 872 } 873 874 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 875 mvgbe_start(ifp); 876 877 rnd_add_uint32(&sc->sc_rnd_source, datum); 878 879 return claimed; 880 } 881 882 static void 883 mvgbe_start(struct ifnet *ifp) 884 { 885 struct mvgbe_softc *sc = ifp->if_softc; 886 struct mbuf *m_head = NULL; 887 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 888 int pkts = 0; 889 890 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 891 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 892 893 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 894 return; 895 /* If Link is DOWN, can't start TX */ 896 if (!(MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP)) 897 return; 898 899 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 900 IFQ_POLL(&ifp->if_snd, m_head); 901 if (m_head == NULL) 902 break; 903 904 /* 905 * Pack the data into the transmit ring. If we 906 * don't have room, set the OACTIVE flag and wait 907 * for the NIC to drain the ring. 908 */ 909 if (mvgbe_encap(sc, m_head, &idx)) { 910 ifp->if_flags |= IFF_OACTIVE; 911 break; 912 } 913 914 /* now we are committed to transmit the packet */ 915 IFQ_DEQUEUE(&ifp->if_snd, m_head); 916 pkts++; 917 918 /* 919 * If there's a BPF listener, bounce a copy of this frame 920 * to him. 921 */ 922 bpf_mtap(ifp, m_head); 923 } 924 if (pkts == 0) 925 return; 926 927 /* Transmit at Queue 0 */ 928 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 929 sc->sc_cdata.mvgbe_tx_prod = idx; 930 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 931 932 /* 933 * Set a timeout in case the chip goes out to lunch. 934 */ 935 ifp->if_timer = 1; 936 sc->sc_wdogsoft = 1; 937 } 938 } 939 940 static int 941 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 942 { 943 struct mvgbe_softc *sc = ifp->if_softc; 944 struct ifreq *ifr = data; 945 int s, error = 0; 946 947 s = splnet(); 948 949 switch (cmd) { 950 case SIOCGIFMEDIA: 951 case SIOCSIFMEDIA: 952 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 953 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 954 break; 955 default: 956 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 957 error = ether_ioctl(ifp, cmd, data); 958 if (error == ENETRESET) { 959 if (ifp->if_flags & IFF_RUNNING) { 960 mvgbe_filter_setup(sc); 961 } 962 error = 0; 963 } 964 break; 965 } 966 967 splx(s); 968 969 return error; 970 } 971 972 int mvgbe_rximt = 0; 973 int mvgbe_tximt = 0; 974 975 static int 976 mvgbe_init(struct ifnet *ifp) 977 { 978 struct mvgbe_softc *sc = ifp->if_softc; 979 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 980 struct mii_data *mii = &sc->sc_mii; 981 uint32_t reg; 982 int i; 983 984 DPRINTFN(2, ("mvgbe_init\n")); 985 986 /* Cancel pending I/O and free all RX/TX buffers. */ 987 mvgbe_stop(ifp, 0); 988 989 /* clear all ethernet port interrupts */ 990 MVGBE_WRITE(sc, MVGBE_IC, 0); 991 MVGBE_WRITE(sc, MVGBE_ICE, 0); 992 993 /* Init TX/RX descriptors */ 994 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 995 aprint_error_ifnet(ifp, 996 "initialization failed: no memory for tx buffers\n"); 997 return ENOBUFS; 998 } 999 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 1000 aprint_error_ifnet(ifp, 1001 "initialization failed: no memory for rx buffers\n"); 1002 return ENOBUFS; 1003 } 1004 1005 if (csc->sc_flags & FLAGS_FIX_MTU) 1006 MVGBE_WRITE(sc, MVGBE_MTU, 0); /* hw reset value is wrong */ 1007 MVGBE_WRITE(sc, MVGBE_PSC, 1008 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 1009 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 1010 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 1011 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 1012 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 1013 /* XXXX: mvgbe(4) always use RGMII. */ 1014 MVGBE_WRITE(sc, MVGBE_PSC1, 1015 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 1016 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 1017 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 1018 1019 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 1020 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1021 1022 if (csc->sc_flags & FLAGS_FIX_TQTB) { 1023 /* 1024 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1025 * And offset 0x72704 must be programmed to 0x03ffffff. 1026 * Queue 1 through 7 must be programmed to 0x0. 1027 */ 1028 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1029 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1030 for (i = 1; i < 8; i++) { 1031 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1032 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1033 } 1034 } else 1035 for (i = 1; i < 8; i++) { 1036 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1037 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1038 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1039 } 1040 1041 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1042 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1043 MVGBE_WRITE(sc, MVGBE_SDC, 1044 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1045 #if BYTE_ORDER == LITTLE_ENDIAN 1046 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1047 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1048 #endif 1049 MVGBE_SDC_IPGINTRX(mvgbe_rximt) | 1050 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1051 MVGBE_WRITE(sc, MVGBE_PTFUT, MVGBE_PTFUT_IPGINTTX(mvgbe_tximt)); 1052 1053 mvgbe_filter_setup(sc); 1054 1055 mii_mediachg(mii); 1056 1057 /* Enable port */ 1058 reg = MVGBE_READ(sc, MVGBE_PSC); 1059 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1060 1061 /* If Link is UP, Start RX and TX traffic */ 1062 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 1063 /* Enable port RX/TX. */ 1064 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1065 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 1066 } 1067 1068 /* Enable interrupt masks */ 1069 MVGBE_WRITE(sc, MVGBE_PIM, 1070 MVGBE_IC_RXBUF | 1071 MVGBE_IC_EXTEND | 1072 MVGBE_IC_RXBUFQ_MASK | 1073 MVGBE_IC_RXERROR | 1074 MVGBE_IC_RXERRQ_MASK); 1075 MVGBE_WRITE(sc, MVGBE_PEIM, 1076 MVGBE_ICE_TXBUF | 1077 MVGBE_ICE_TXERR | 1078 MVGBE_ICE_LINKCHG); 1079 1080 callout_schedule(&sc->sc_tick_ch, hz); 1081 1082 ifp->if_flags |= IFF_RUNNING; 1083 ifp->if_flags &= ~IFF_OACTIVE; 1084 1085 return 0; 1086 } 1087 1088 /* ARGSUSED */ 1089 static void 1090 mvgbe_stop(struct ifnet *ifp, int disable) 1091 { 1092 struct mvgbe_softc *sc = ifp->if_softc; 1093 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 1094 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1095 uint32_t reg; 1096 int i, cnt; 1097 1098 DPRINTFN(2, ("mvgbe_stop\n")); 1099 1100 callout_stop(&sc->sc_tick_ch); 1101 1102 /* Stop Rx port activity. Check port Rx activity. */ 1103 reg = MVGBE_READ(sc, MVGBE_RQC); 1104 if (reg & MVGBE_RQC_ENQ_MASK) 1105 /* Issue stop command for active channels only */ 1106 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1107 1108 /* Stop Tx port activity. Check port Tx activity. */ 1109 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ) 1110 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 1111 1112 /* Force link down */ 1113 reg = MVGBE_READ(sc, MVGBE_PSC); 1114 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1115 1116 #define RX_DISABLE_TIMEOUT 0x1000000 1117 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1118 /* Wait for all Rx activity to terminate. */ 1119 cnt = 0; 1120 do { 1121 if (cnt >= RX_DISABLE_TIMEOUT) { 1122 aprint_error_ifnet(ifp, 1123 "timeout for RX stopped. rqc 0x%x\n", reg); 1124 break; 1125 } 1126 cnt++; 1127 1128 /* 1129 * Check Receive Queue Command register that all Rx queues 1130 * are stopped 1131 */ 1132 reg = MVGBE_READ(sc, MVGBE_RQC); 1133 } while (reg & 0xff); 1134 1135 /* Double check to verify that TX FIFO is empty */ 1136 cnt = 0; 1137 while (1) { 1138 do { 1139 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1140 aprint_error_ifnet(ifp, 1141 "timeout for TX FIFO empty. status 0x%x\n", 1142 reg); 1143 break; 1144 } 1145 cnt++; 1146 1147 reg = MVGBE_READ(sc, MVGBE_PS); 1148 } while 1149 (!(reg & MVGBE_PS_TXFIFOEMP) || reg & MVGBE_PS_TXINPROG); 1150 1151 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1152 break; 1153 1154 /* Double check */ 1155 reg = MVGBE_READ(sc, MVGBE_PS); 1156 if (reg & MVGBE_PS_TXFIFOEMP && !(reg & MVGBE_PS_TXINPROG)) 1157 break; 1158 else 1159 aprint_error_ifnet(ifp, 1160 "TX FIFO empty double check failed." 1161 " %d loops, status 0x%x\n", cnt, reg); 1162 } 1163 1164 /* Reset the Enable bit in the Port Serial Control Register */ 1165 reg = MVGBE_READ(sc, MVGBE_PSC); 1166 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1167 1168 /* 1169 * Disable and clear interrupts 1170 * 0) controller interrupt 1171 * 1) port interrupt cause 1172 * 2) port interrupt mask 1173 */ 1174 MVGBE_WRITE(csc, MVGBE_EUIM, 0); 1175 MVGBE_WRITE(csc, MVGBE_EUIC, 0); 1176 MVGBE_WRITE(sc, MVGBE_IC, 0); 1177 MVGBE_WRITE(sc, MVGBE_ICE, 0); 1178 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1179 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1180 1181 /* Free RX and TX mbufs still in the queues. */ 1182 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1183 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1184 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1185 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1186 } 1187 } 1188 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1189 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1190 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1191 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1192 } 1193 } 1194 1195 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1196 } 1197 1198 static void 1199 mvgbe_watchdog(struct ifnet *ifp) 1200 { 1201 struct mvgbe_softc *sc = ifp->if_softc; 1202 1203 /* 1204 * Reclaim first as there is a possibility of losing Tx completion 1205 * interrupts. 1206 */ 1207 mvgbe_txeof(sc); 1208 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1209 if (sc->sc_wdogsoft) { 1210 /* 1211 * There is race condition between CPU and DMA 1212 * engine. When DMA engine encounters queue end, 1213 * it clears MVGBE_TQC_ENQ bit. 1214 */ 1215 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 1216 ifp->if_timer = 5; 1217 sc->sc_wdogsoft = 0; 1218 } else { 1219 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1220 1221 ifp->if_oerrors++; 1222 1223 mvgbe_init(ifp); 1224 } 1225 } 1226 } 1227 1228 static int 1229 mvgbe_ifflags_cb(struct ethercom *ec) 1230 { 1231 struct ifnet *ifp = &ec->ec_if; 1232 struct mvgbe_softc *sc = ifp->if_softc; 1233 int change = ifp->if_flags ^ sc->sc_if_flags; 1234 1235 if (change != 0) 1236 sc->sc_if_flags = ifp->if_flags; 1237 1238 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1239 return ENETRESET; 1240 1241 if ((change & IFF_PROMISC) != 0) 1242 mvgbe_filter_setup(sc); 1243 1244 return 0; 1245 } 1246 1247 /* 1248 * Set media options. 1249 */ 1250 static int 1251 mvgbe_mediachange(struct ifnet *ifp) 1252 { 1253 return ether_mediachange(ifp); 1254 } 1255 1256 /* 1257 * Report current media status. 1258 */ 1259 static void 1260 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1261 { 1262 ether_mediastatus(ifp, ifmr); 1263 } 1264 1265 1266 static int 1267 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1268 { 1269 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1270 struct mvgbe_ring_data *rd = sc->sc_rdata; 1271 int i; 1272 1273 memset(rd->mvgbe_rx_ring, 0, 1274 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1275 1276 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1277 cd->mvgbe_rx_chain[i].mvgbe_desc = 1278 &rd->mvgbe_rx_ring[i]; 1279 if (i == MVGBE_RX_RING_CNT - 1) { 1280 cd->mvgbe_rx_chain[i].mvgbe_next = 1281 &cd->mvgbe_rx_chain[0]; 1282 rd->mvgbe_rx_ring[i].nextdescptr = 1283 MVGBE_RX_RING_ADDR(sc, 0); 1284 } else { 1285 cd->mvgbe_rx_chain[i].mvgbe_next = 1286 &cd->mvgbe_rx_chain[i + 1]; 1287 rd->mvgbe_rx_ring[i].nextdescptr = 1288 MVGBE_RX_RING_ADDR(sc, i + 1); 1289 } 1290 } 1291 1292 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1293 if (mvgbe_newbuf(sc, i, NULL, 1294 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1295 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1296 "failed alloc of %dth mbuf\n", i); 1297 return ENOBUFS; 1298 } 1299 } 1300 sc->sc_cdata.mvgbe_rx_prod = 0; 1301 sc->sc_cdata.mvgbe_rx_cons = 0; 1302 1303 return 0; 1304 } 1305 1306 static int 1307 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1308 { 1309 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1310 struct mvgbe_ring_data *rd = sc->sc_rdata; 1311 int i; 1312 1313 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1314 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1315 1316 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1317 cd->mvgbe_tx_chain[i].mvgbe_desc = 1318 &rd->mvgbe_tx_ring[i]; 1319 if (i == MVGBE_TX_RING_CNT - 1) { 1320 cd->mvgbe_tx_chain[i].mvgbe_next = 1321 &cd->mvgbe_tx_chain[0]; 1322 rd->mvgbe_tx_ring[i].nextdescptr = 1323 MVGBE_TX_RING_ADDR(sc, 0); 1324 } else { 1325 cd->mvgbe_tx_chain[i].mvgbe_next = 1326 &cd->mvgbe_tx_chain[i + 1]; 1327 rd->mvgbe_tx_ring[i].nextdescptr = 1328 MVGBE_TX_RING_ADDR(sc, i + 1); 1329 } 1330 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1331 } 1332 1333 sc->sc_cdata.mvgbe_tx_prod = 0; 1334 sc->sc_cdata.mvgbe_tx_cons = 0; 1335 sc->sc_cdata.mvgbe_tx_cnt = 0; 1336 1337 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1338 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1339 1340 return 0; 1341 } 1342 1343 static int 1344 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1345 bus_dmamap_t dmamap) 1346 { 1347 struct mbuf *m_new = NULL; 1348 struct mvgbe_chain *c; 1349 struct mvgbe_rx_desc *r; 1350 int align; 1351 vaddr_t offset; 1352 1353 if (m == NULL) { 1354 void *buf = NULL; 1355 1356 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1357 if (m_new == NULL) { 1358 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1359 "no memory for rx list -- packet dropped!\n"); 1360 return ENOBUFS; 1361 } 1362 1363 /* Allocate the jumbo buffer */ 1364 buf = mvgbe_jalloc(sc); 1365 if (buf == NULL) { 1366 m_freem(m_new); 1367 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1368 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1369 return ENOBUFS; 1370 } 1371 1372 /* Attach the buffer to the mbuf */ 1373 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1374 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1375 } else { 1376 /* 1377 * We're re-using a previously allocated mbuf; 1378 * be sure to re-init pointers and lengths to 1379 * default values. 1380 */ 1381 m_new = m; 1382 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1383 m_new->m_data = m_new->m_ext.ext_buf; 1384 } 1385 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1386 if (align != 0) { 1387 DPRINTFN(1,("align = %d\n", align)); 1388 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1389 } 1390 1391 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1392 r = c->mvgbe_desc; 1393 c->mvgbe_mbuf = m_new; 1394 offset = (vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf; 1395 r->bufptr = dmamap->dm_segs[0].ds_addr + offset; 1396 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1397 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1398 1399 /* Invalidate RX buffer */ 1400 bus_dmamap_sync(sc->sc_dmat, dmamap, offset, r->bufsize, 1401 BUS_DMASYNC_PREREAD); 1402 1403 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1404 1405 return 0; 1406 } 1407 1408 /* 1409 * Memory management for jumbo frames. 1410 */ 1411 1412 static int 1413 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1414 { 1415 char *ptr, *kva; 1416 bus_dma_segment_t seg; 1417 int i, rseg, state, error; 1418 struct mvgbe_jpool_entry *entry; 1419 1420 state = error = 0; 1421 1422 /* Grab a big chunk o' storage. */ 1423 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1424 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1425 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1426 return ENOBUFS; 1427 } 1428 1429 state = 1; 1430 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1431 (void **)&kva, BUS_DMA_NOWAIT)) { 1432 aprint_error_dev(sc->sc_dev, 1433 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1434 error = ENOBUFS; 1435 goto out; 1436 } 1437 1438 state = 2; 1439 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1440 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1441 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1442 error = ENOBUFS; 1443 goto out; 1444 } 1445 1446 state = 3; 1447 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1448 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1449 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1450 error = ENOBUFS; 1451 goto out; 1452 } 1453 1454 state = 4; 1455 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1456 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1457 1458 LIST_INIT(&sc->sc_jfree_listhead); 1459 LIST_INIT(&sc->sc_jinuse_listhead); 1460 1461 /* 1462 * Now divide it up into 9K pieces and save the addresses 1463 * in an array. 1464 */ 1465 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1466 for (i = 0; i < MVGBE_JSLOTS; i++) { 1467 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1468 ptr += MVGBE_JLEN; 1469 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1470 if (entry == NULL) { 1471 aprint_error_dev(sc->sc_dev, 1472 "no memory for jumbo buffer queue!\n"); 1473 error = ENOBUFS; 1474 goto out; 1475 } 1476 entry->slot = i; 1477 if (i) 1478 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1479 jpool_entries); 1480 else 1481 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1482 jpool_entries); 1483 } 1484 out: 1485 if (error != 0) { 1486 switch (state) { 1487 case 4: 1488 bus_dmamap_unload(sc->sc_dmat, 1489 sc->sc_cdata.mvgbe_rx_jumbo_map); 1490 case 3: 1491 bus_dmamap_destroy(sc->sc_dmat, 1492 sc->sc_cdata.mvgbe_rx_jumbo_map); 1493 case 2: 1494 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1495 case 1: 1496 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1497 break; 1498 default: 1499 break; 1500 } 1501 } 1502 1503 return error; 1504 } 1505 1506 /* 1507 * Allocate a jumbo buffer. 1508 */ 1509 static void * 1510 mvgbe_jalloc(struct mvgbe_softc *sc) 1511 { 1512 struct mvgbe_jpool_entry *entry; 1513 1514 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1515 1516 if (entry == NULL) 1517 return NULL; 1518 1519 LIST_REMOVE(entry, jpool_entries); 1520 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1521 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1522 } 1523 1524 /* 1525 * Release a jumbo buffer. 1526 */ 1527 static void 1528 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1529 { 1530 struct mvgbe_jpool_entry *entry; 1531 struct mvgbe_softc *sc; 1532 int i, s; 1533 1534 /* Extract the softc struct pointer. */ 1535 sc = (struct mvgbe_softc *)arg; 1536 1537 if (sc == NULL) 1538 panic("%s: can't find softc pointer!", __func__); 1539 1540 /* calculate the slot this buffer belongs to */ 1541 1542 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1543 1544 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1545 panic("%s: asked to free buffer that we don't manage!", 1546 __func__); 1547 1548 s = splvm(); 1549 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1550 if (entry == NULL) 1551 panic("%s: buffer not in use!", __func__); 1552 entry->slot = i; 1553 LIST_REMOVE(entry, jpool_entries); 1554 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1555 1556 if (__predict_true(m != NULL)) 1557 pool_cache_put(mb_cache, m); 1558 splx(s); 1559 } 1560 1561 static int 1562 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1563 uint32_t *txidx) 1564 { 1565 struct mvgbe_tx_desc *f = NULL; 1566 struct mvgbe_txmap_entry *entry; 1567 bus_dma_segment_t *txseg; 1568 bus_dmamap_t txmap; 1569 uint32_t first, current, last, cmdsts = 0; 1570 int m_csumflags, i; 1571 bool needs_defrag = false; 1572 1573 DPRINTFN(3, ("mvgbe_encap\n")); 1574 1575 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1576 if (entry == NULL) { 1577 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1578 return ENOBUFS; 1579 } 1580 txmap = entry->dmamap; 1581 1582 first = current = last = *txidx; 1583 1584 /* 1585 * Preserve m_pkthdr.csum_flags here since m_head might be 1586 * updated by m_defrag() 1587 */ 1588 m_csumflags = m_head->m_pkthdr.csum_flags; 1589 1590 do_defrag: 1591 if (__predict_false(needs_defrag == true)) { 1592 /* A small unaligned segment was detected. */ 1593 struct mbuf *m_new; 1594 m_new = m_defrag(m_head, M_DONTWAIT); 1595 if (m_new == NULL) 1596 return EFBIG; 1597 m_head = m_new; 1598 } 1599 1600 /* 1601 * Start packing the mbufs in this chain into 1602 * the fragment pointers. Stop when we run out 1603 * of fragments or hit the end of the mbuf chain. 1604 */ 1605 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1606 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1607 return ENOBUFS; 1608 } 1609 1610 txseg = txmap->dm_segs; 1611 1612 if (__predict_true(needs_defrag == false)) { 1613 /* 1614 * Detect rarely encountered DMA limitation. 1615 */ 1616 for (i = 0; i < txmap->dm_nsegs; i++) { 1617 if (((txseg[i].ds_addr & 7) != 0) && 1618 (txseg[i].ds_len <= 8) && 1619 (txseg[i].ds_len >= 1) 1620 ) { 1621 txseg = NULL; 1622 bus_dmamap_unload(sc->sc_dmat, txmap); 1623 needs_defrag = true; 1624 goto do_defrag; 1625 } 1626 } 1627 } 1628 1629 /* Sync the DMA map. */ 1630 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1631 BUS_DMASYNC_PREWRITE); 1632 1633 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1634 MVGBE_TX_RING_CNT) { 1635 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1636 bus_dmamap_unload(sc->sc_dmat, txmap); 1637 return ENOBUFS; 1638 } 1639 1640 1641 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1642 1643 for (i = 0; i < txmap->dm_nsegs; i++) { 1644 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1645 f->bufptr = txseg[i].ds_addr; 1646 f->bytecnt = txseg[i].ds_len; 1647 if (i != 0) 1648 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1649 last = current; 1650 current = MVGBE_TX_RING_NEXT(current); 1651 } 1652 1653 if (m_csumflags & M_CSUM_IPv4) 1654 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1655 if (m_csumflags & M_CSUM_TCPv4) 1656 cmdsts |= 1657 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1658 if (m_csumflags & M_CSUM_UDPv4) 1659 cmdsts |= 1660 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1661 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1662 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1663 1664 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1665 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1666 } 1667 if (txmap->dm_nsegs == 1) 1668 f->cmdsts = cmdsts | 1669 MVGBE_TX_GENERATE_CRC | 1670 MVGBE_TX_ENABLE_INTERRUPT | 1671 MVGBE_TX_ZERO_PADDING | 1672 MVGBE_TX_FIRST_DESC | 1673 MVGBE_TX_LAST_DESC; 1674 else { 1675 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1676 f->cmdsts = cmdsts | 1677 MVGBE_TX_GENERATE_CRC | 1678 MVGBE_TX_FIRST_DESC; 1679 1680 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1681 f->cmdsts = 1682 MVGBE_BUFFER_OWNED_BY_DMA | 1683 MVGBE_TX_ENABLE_INTERRUPT | 1684 MVGBE_TX_ZERO_PADDING | 1685 MVGBE_TX_LAST_DESC; 1686 1687 /* Sync descriptors except first */ 1688 MVGBE_CDTXSYNC(sc, 1689 (MVGBE_TX_RING_CNT - 1 == *txidx) ? 0 : (*txidx) + 1, 1690 txmap->dm_nsegs - 1, 1691 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1692 } 1693 1694 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1695 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1696 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1697 1698 /* Finally, sync first descriptor */ 1699 sc->sc_rdata->mvgbe_tx_ring[first].cmdsts |= 1700 MVGBE_BUFFER_OWNED_BY_DMA; 1701 MVGBE_CDTXSYNC(sc, *txidx, 1, 1702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1703 1704 sc->sc_cdata.mvgbe_tx_cnt += i; 1705 *txidx = current; 1706 1707 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1708 1709 return 0; 1710 } 1711 1712 static void 1713 mvgbe_rxeof(struct mvgbe_softc *sc) 1714 { 1715 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1716 struct mvgbe_rx_desc *cur_rx; 1717 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1718 struct mbuf *m; 1719 bus_dmamap_t dmamap; 1720 uint32_t rxstat; 1721 uint16_t bufsize; 1722 int idx, cur, total_len; 1723 1724 idx = sc->sc_cdata.mvgbe_rx_prod; 1725 1726 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1727 1728 for (;;) { 1729 cur = idx; 1730 1731 /* Sync the descriptor */ 1732 MVGBE_CDRXSYNC(sc, idx, 1733 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1734 1735 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1736 1737 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1738 MVGBE_BUFFER_OWNED_BY_DMA) { 1739 /* Invalidate the descriptor -- it's not ready yet */ 1740 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1741 sc->sc_cdata.mvgbe_rx_prod = idx; 1742 break; 1743 } 1744 #ifdef DIAGNOSTIC 1745 if ((cur_rx->cmdsts & 1746 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1747 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1748 panic( 1749 "mvgbe_rxeof: buffer size is smaller than packet"); 1750 #endif 1751 1752 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1753 1754 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1755 BUS_DMASYNC_POSTREAD); 1756 1757 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1758 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1759 total_len = cur_rx->bytecnt - ETHER_CRC_LEN; 1760 rxstat = cur_rx->cmdsts; 1761 bufsize = cur_rx->bufsize; 1762 1763 cdata->mvgbe_rx_map[idx] = NULL; 1764 1765 idx = MVGBE_RX_RING_NEXT(idx); 1766 1767 if (rxstat & MVGBE_ERROR_SUMMARY) { 1768 #if 0 1769 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1770 1771 if (err == MVGBE_RX_CRC_ERROR) 1772 ifp->if_ierrors++; 1773 if (err == MVGBE_RX_OVERRUN_ERROR) 1774 ifp->if_ierrors++; 1775 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1776 ifp->if_ierrors++; 1777 if (err == MVGBE_RX_RESOURCE_ERROR) 1778 ifp->if_ierrors++; 1779 #else 1780 ifp->if_ierrors++; 1781 #endif 1782 mvgbe_newbuf(sc, cur, m, dmamap); 1783 continue; 1784 } 1785 1786 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1787 int flgs = 0; 1788 1789 /* Check IPv4 header checksum */ 1790 flgs |= M_CSUM_IPv4; 1791 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 1792 flgs |= M_CSUM_IPv4_BAD; 1793 else if ((bufsize & MVGBE_RX_IP_FRAGMENT) == 0) { 1794 /* 1795 * Check TCPv4/UDPv4 checksum for 1796 * non-fragmented packet only. 1797 * 1798 * It seemd that sometimes 1799 * MVGBE_RX_L4_CHECKSUM_OK bit was set to 0 1800 * even if the checksum is correct and the 1801 * packet was not fragmented. So we don't set 1802 * M_CSUM_TCP_UDP_BAD even if csum bit is 0. 1803 */ 1804 1805 if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1806 MVGBE_RX_L4_TYPE_TCP) && 1807 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 1808 flgs |= M_CSUM_TCPv4; 1809 else if (((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1810 MVGBE_RX_L4_TYPE_UDP) && 1811 ((rxstat & MVGBE_RX_L4_CHECKSUM_OK) != 0)) 1812 flgs |= M_CSUM_UDPv4; 1813 } 1814 m->m_pkthdr.csum_flags = flgs; 1815 } 1816 1817 /* 1818 * Try to allocate a new jumbo buffer. If that 1819 * fails, copy the packet to mbufs and put the 1820 * jumbo buffer back in the ring so it can be 1821 * re-used. If allocating mbufs fails, then we 1822 * have to drop the packet. 1823 */ 1824 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 1825 struct mbuf *m0; 1826 1827 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 1828 mvgbe_newbuf(sc, cur, m, dmamap); 1829 if (m0 == NULL) { 1830 aprint_error_ifnet(ifp, 1831 "no receive buffers available --" 1832 " packet dropped!\n"); 1833 ifp->if_ierrors++; 1834 continue; 1835 } 1836 m = m0; 1837 } else { 1838 m->m_pkthdr.rcvif = ifp; 1839 m->m_pkthdr.len = m->m_len = total_len; 1840 } 1841 1842 /* Skip on first 2byte (HW header) */ 1843 m_adj(m, MVGBE_HWHEADER_SIZE); 1844 1845 ifp->if_ipackets++; 1846 1847 bpf_mtap(ifp, m); 1848 1849 /* pass it on. */ 1850 (*ifp->if_input)(ifp, m); 1851 } 1852 } 1853 1854 static void 1855 mvgbe_txeof(struct mvgbe_softc *sc) 1856 { 1857 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1858 struct mvgbe_tx_desc *cur_tx; 1859 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1860 struct mvgbe_txmap_entry *entry; 1861 int idx; 1862 1863 DPRINTFN(3, ("mvgbe_txeof\n")); 1864 1865 /* 1866 * Go through our tx ring and free mbufs for those 1867 * frames that have been sent. 1868 */ 1869 idx = cdata->mvgbe_tx_cons; 1870 while (idx != cdata->mvgbe_tx_prod) { 1871 MVGBE_CDTXSYNC(sc, idx, 1, 1872 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1873 1874 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 1875 #ifdef MVGBE_DEBUG 1876 if (mvgbe_debug >= 3) 1877 mvgbe_dump_txdesc(cur_tx, idx); 1878 #endif 1879 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1880 MVGBE_BUFFER_OWNED_BY_DMA) { 1881 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 1882 break; 1883 } 1884 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 1885 ifp->if_opackets++; 1886 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 1887 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 1888 1889 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 1890 ifp->if_collisions++; 1891 if (err == MVGBE_TX_UNDERRUN_ERROR) 1892 ifp->if_oerrors++; 1893 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 1894 ifp->if_collisions++; 1895 } 1896 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 1897 entry = cdata->mvgbe_tx_map[idx]; 1898 1899 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 1900 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 1901 1902 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 1903 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1904 1905 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 1906 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 1907 cdata->mvgbe_tx_map[idx] = NULL; 1908 } 1909 cdata->mvgbe_tx_cnt--; 1910 idx = MVGBE_TX_RING_NEXT(idx); 1911 } 1912 if (cdata->mvgbe_tx_cnt == 0) 1913 ifp->if_timer = 0; 1914 1915 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 1916 ifp->if_flags &= ~IFF_OACTIVE; 1917 1918 cdata->mvgbe_tx_cons = idx; 1919 } 1920 1921 static uint8_t 1922 mvgbe_crc8(const uint8_t *data, size_t size) 1923 { 1924 int bit; 1925 uint8_t byte; 1926 uint8_t crc = 0; 1927 const uint8_t poly = 0x07; 1928 1929 while(size--) 1930 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 1931 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 1932 1933 return crc; 1934 } 1935 1936 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 1937 1938 static void 1939 mvgbe_filter_setup(struct mvgbe_softc *sc) 1940 { 1941 struct ethercom *ec = &sc->sc_ethercom; 1942 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 1943 struct ether_multi *enm; 1944 struct ether_multistep step; 1945 uint32_t dfut[MVGBE_NDFUT], dfsmt[MVGBE_NDFSMT], dfomt[MVGBE_NDFOMT]; 1946 uint32_t pxc; 1947 int i; 1948 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 1949 1950 memset(dfut, 0, sizeof(dfut)); 1951 memset(dfsmt, 0, sizeof(dfsmt)); 1952 memset(dfomt, 0, sizeof(dfomt)); 1953 1954 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1955 goto allmulti; 1956 } 1957 1958 ETHER_FIRST_MULTI(step, ec, enm); 1959 while (enm != NULL) { 1960 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1961 /* ranges are complex and somewhat rare */ 1962 goto allmulti; 1963 } 1964 /* chip handles some IPv4 multicast specially */ 1965 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 1966 i = enm->enm_addrlo[5]; 1967 dfsmt[i>>2] = 1968 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1969 } else { 1970 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 1971 dfomt[i>>2] = 1972 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1973 } 1974 1975 ETHER_NEXT_MULTI(step, enm); 1976 } 1977 goto set; 1978 1979 allmulti: 1980 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1981 for (i = 0; i < MVGBE_NDFSMT; i++) { 1982 dfsmt[i] = dfomt[i] = 1983 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1984 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1985 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1986 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1987 } 1988 } 1989 1990 set: 1991 pxc = MVGBE_READ(sc, MVGBE_PXC); 1992 pxc &= ~MVGBE_PXC_UPM; 1993 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 1994 if (ifp->if_flags & IFF_BROADCAST) { 1995 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 1996 } 1997 if (ifp->if_flags & IFF_PROMISC) { 1998 pxc |= MVGBE_PXC_UPM; 1999 } 2000 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 2001 2002 /* Set Destination Address Filter Unicast Table */ 2003 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 2004 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 2005 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 2006 2007 /* Set Destination Address Filter Multicast Tables */ 2008 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 2009 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 2010 } 2011 2012 #ifdef MVGBE_DEBUG 2013 static void 2014 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 2015 { 2016 #define DESC_PRINT(X) \ 2017 if (X) \ 2018 printf("txdesc[%d]." #X "=%#x\n", idx, X); 2019 2020 #if BYTE_ORDER == BIG_ENDIAN 2021 DESC_PRINT(desc->bytecnt); 2022 DESC_PRINT(desc->l4ichk); 2023 DESC_PRINT(desc->cmdsts); 2024 DESC_PRINT(desc->nextdescptr); 2025 DESC_PRINT(desc->bufptr); 2026 #else /* LITTLE_ENDIAN */ 2027 DESC_PRINT(desc->cmdsts); 2028 DESC_PRINT(desc->l4ichk); 2029 DESC_PRINT(desc->bytecnt); 2030 DESC_PRINT(desc->bufptr); 2031 DESC_PRINT(desc->nextdescptr); 2032 #endif 2033 #undef DESC_PRINT 2034 } 2035 #endif 2036
Indexes created Wed Oct 22 13:09:56 GMT 2025