if_mvgbe.c revision 1.2.2.3
1 /* $NetBSD: if_mvgbe.c,v 1.2.2.3 2010/10/09 03:32:08 yamt Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.2.2.3 2010/10/09 03:32:08 yamt Exp $"); 29 30 #include "rnd.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/endian.h> 36 #include <sys/errno.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 #include <sys/sockio.h> 40 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 #include <dev/marvell/mvgbereg.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/in_systm.h> 51 #include <netinet/ip.h> 52 53 #include <net/bpf.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include "locators.h" 62 63 /* #define MVGBE_DEBUG 3 */ 64 #ifdef MVGBE_DEBUG 65 #define DPRINTF(x) if (mvgbe_debug) printf x 66 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 67 int mvgbe_debug = MVGBE_DEBUG; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n,x) 71 #endif 72 73 74 #define MVGBE_READ(sc, reg) \ 75 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 76 #define MVGBE_WRITE(sc, reg, val) \ 77 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 78 #define MVGBE_READ_FILTER(sc, reg) \ 79 bus_space_read_4((sc)->sc_iot, (sc)->sc_dafh, (reg)) 80 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 81 bus_space_set_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 82 83 #define MVGBE_TX_RING_CNT 256 84 #define MVGBE_RX_RING_CNT 256 85 86 #define MVGBE_JSLOTS 384 /* XXXX */ 87 #define MVGBE_JLEN (MVGBE_MRU + MVGBE_BUF_ALIGN) 88 #define MVGBE_NTXSEG 30 89 #define MVGBE_JPAGESZ PAGE_SIZE 90 #define MVGBE_RESID \ 91 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 92 #define MVGBE_JMEM \ 93 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 94 95 #define MVGBE_TX_RING_ADDR(sc, i) \ 96 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 97 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 98 99 #define MVGBE_RX_RING_ADDR(sc, i) \ 100 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 101 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 102 103 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 104 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 105 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 106 107 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 108 do { \ 109 int __x, __n; \ 110 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 111 \ 112 __x = (x); \ 113 __n = (n); \ 114 \ 115 /* If it will wrap around, sync to the end of the ring. */ \ 116 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 117 bus_dmamap_sync((sc)->sc_dmat, \ 118 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 119 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 120 __n -= (MVGBE_TX_RING_CNT - __x); \ 121 __x = 0; \ 122 } \ 123 \ 124 /* Now sync whatever is left. */ \ 125 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 126 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 127 } while (0 /*CONSTCOND*/) 128 129 #define MVGBE_CDRXSYNC(sc, x, ops) \ 130 do { \ 131 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 132 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 133 } while (/*CONSTCOND*/0) 134 135 136 struct mvgbe_jpool_entry { 137 int slot; 138 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 139 }; 140 141 struct mvgbe_chain { 142 void *mvgbe_desc; 143 struct mbuf *mvgbe_mbuf; 144 struct mvgbe_chain *mvgbe_next; 145 }; 146 147 struct mvgbe_txmap_entry { 148 bus_dmamap_t dmamap; 149 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 150 }; 151 152 struct mvgbe_chain_data { 153 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 154 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 155 int mvgbe_tx_prod; 156 int mvgbe_tx_cons; 157 int mvgbe_tx_cnt; 158 159 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 160 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 161 bus_dmamap_t mvgbe_rx_jumbo_map; 162 int mvgbe_rx_prod; 163 int mvgbe_rx_cons; 164 int mvgbe_rx_cnt; 165 166 /* Stick the jumbo mem management stuff here too. */ 167 void *mvgbe_jslots[MVGBE_JSLOTS]; 168 void *mvgbe_jumbo_buf; 169 }; 170 171 struct mvgbe_ring_data { 172 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 173 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 174 }; 175 176 struct mvgbec_softc { 177 device_t sc_dev; 178 179 bus_space_tag_t sc_iot; 180 bus_space_handle_t sc_ioh; 181 182 kmutex_t sc_mtx; 183 184 int sc_fix_tqtb; 185 }; 186 187 struct mvgbe_softc { 188 device_t sc_dev; 189 int sc_port; 190 191 bus_space_tag_t sc_iot; 192 bus_space_handle_t sc_ioh; 193 bus_space_handle_t sc_dafh; /* dest address filter handle */ 194 bus_dma_tag_t sc_dmat; 195 196 struct ethercom sc_ethercom; 197 struct mii_data sc_mii; 198 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 199 200 struct mvgbe_chain_data sc_cdata; 201 struct mvgbe_ring_data *sc_rdata; 202 bus_dmamap_t sc_ring_map; 203 int sc_if_flags; 204 205 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 206 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 207 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 208 209 #if NRND > 0 210 rndsource_element_t sc_rnd_source; 211 #endif 212 }; 213 214 215 /* Gigabit Ethernet Unit Global part functions */ 216 217 static int mvgbec_match(device_t, struct cfdata *, void *); 218 static void mvgbec_attach(device_t, device_t, void *); 219 220 static int mvgbec_print(void *, const char *); 221 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 222 223 /* MII funcstions */ 224 static int mvgbec_miibus_readreg(device_t, int, int); 225 static void mvgbec_miibus_writereg(device_t, int, int, int); 226 static void mvgbec_miibus_statchg(device_t); 227 228 static void mvgbec_wininit(struct mvgbec_softc *); 229 230 /* Gigabit Ethernet Port part functions */ 231 232 static int mvgbe_match(device_t, struct cfdata *, void *); 233 static void mvgbe_attach(device_t, device_t, void *); 234 235 static int mvgbe_intr(void *); 236 237 static void mvgbe_start(struct ifnet *); 238 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 239 static int mvgbe_init(struct ifnet *); 240 static void mvgbe_stop(struct ifnet *, int); 241 static void mvgbe_watchdog(struct ifnet *); 242 243 /* MII funcstions */ 244 static int mvgbe_ifmedia_upd(struct ifnet *); 245 static void mvgbe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 246 247 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 248 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 249 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 250 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 251 static void *mvgbe_jalloc(struct mvgbe_softc *); 252 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 253 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 254 static void mvgbe_rxeof(struct mvgbe_softc *); 255 static void mvgbe_txeof(struct mvgbe_softc *); 256 static void mvgbe_setmulti(struct mvgbe_softc *); 257 #ifdef MVGBE_DEBUG 258 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 259 #endif 260 261 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 262 mvgbec_match, mvgbec_attach, NULL, NULL); 263 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 264 mvgbec_match, mvgbec_attach, NULL, NULL); 265 266 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 267 mvgbe_match, mvgbe_attach, NULL, NULL); 268 269 270 struct mvgbe_port { 271 int model; 272 int unit; 273 int ports; 274 int irqs[3]; 275 int flags; 276 #define FLAGS_FIX_TQTB (1 << 0) 277 } mvgbe_ports[] = { 278 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 279 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 280 #if 0 281 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 282 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 283 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 284 #endif 285 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, 0 }, 286 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, 0 }, 287 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, 0 }, 288 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, 0 }, 289 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, 0 }, 290 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, 0 }, 291 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, 0 }, 292 293 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 294 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 295 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 14 }, FLAGS_FIX_TQTB }, 296 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 297 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 14 }, FLAGS_FIX_TQTB }, 298 299 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 300 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 301 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 302 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 303 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB }, 304 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB }, 305 }; 306 307 308 /* ARGSUSED */ 309 static int 310 mvgbec_match(device_t parent, struct cfdata *match, void *aux) 311 { 312 struct marvell_attach_args *mva = aux; 313 int i; 314 315 if (strcmp(mva->mva_name, match->cf_name) != 0) 316 return 0; 317 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 318 return 0; 319 320 for (i = 0; i < __arraycount(mvgbe_ports); i++) 321 if (mva->mva_model == mvgbe_ports[i].model) { 322 mva->mva_size = MVGBE_SIZE; 323 return 1; 324 } 325 return 0; 326 } 327 328 /* ARGSUSED */ 329 static void 330 mvgbec_attach(device_t parent, device_t self, void *aux) 331 { 332 struct mvgbec_softc *sc = device_private(self); 333 struct marvell_attach_args *mva = aux, gbea; 334 struct mvgbe_softc *port; 335 struct mii_softc *mii; 336 device_t child; 337 uint32_t phyaddr; 338 int i, j; 339 340 aprint_naive("\n"); 341 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 342 343 sc->sc_dev = self; 344 sc->sc_iot = mva->mva_iot; 345 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 346 mva->mva_size, &sc->sc_ioh)) { 347 aprint_error_dev(self, "Cannot map registers\n"); 348 return; 349 } 350 phyaddr = 0; 351 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 352 353 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 354 355 /* Disable and clear Gigabit Ethernet Unit interrupts */ 356 MVGBE_WRITE(sc, MVGBE_EUIM, 0); 357 MVGBE_WRITE(sc, MVGBE_EUIC, 0); 358 359 mvgbec_wininit(sc); 360 361 memset(&gbea, 0, sizeof(gbea)); 362 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 363 if (mvgbe_ports[i].model != mva->mva_model || 364 mvgbe_ports[i].unit != mva->mva_unit) 365 continue; 366 367 sc->sc_fix_tqtb = mvgbe_ports[i].flags & FLAGS_FIX_TQTB; 368 369 for (j = 0; j < mvgbe_ports[i].ports; j++) { 370 gbea.mva_name = "mvgbe"; 371 gbea.mva_model = mva->mva_model; 372 gbea.mva_iot = sc->sc_iot; 373 gbea.mva_ioh = sc->sc_ioh; 374 gbea.mva_unit = j; 375 gbea.mva_dmat = mva->mva_dmat; 376 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 377 child = config_found_sm_loc(sc->sc_dev, "mvgbec", NULL, 378 &gbea, mvgbec_print, mvgbec_search); 379 if (child) { 380 port = device_private(child); 381 mii = LIST_FIRST(&port->sc_mii.mii_phys); 382 phyaddr |= MVGBE_PHYADDR_PHYAD(j, mii->mii_phy); 383 } 384 } 385 break; 386 } 387 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 388 } 389 390 static int 391 mvgbec_print(void *aux, const char *pnp) 392 { 393 struct marvell_attach_args *gbea = aux; 394 395 if (pnp) 396 aprint_normal("%s at %s port %d", 397 gbea->mva_name, pnp, gbea->mva_unit); 398 else { 399 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 400 aprint_normal(" port %d", gbea->mva_unit); 401 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 402 aprint_normal(" irq %d", gbea->mva_irq); 403 } 404 return UNCONF; 405 } 406 407 /* ARGSUSED */ 408 static int 409 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 410 { 411 struct marvell_attach_args *gbea = aux; 412 413 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 414 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 415 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 416 417 return config_match(parent, cf, aux); 418 } 419 420 static int 421 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 422 { 423 struct mvgbe_softc *sc = device_private(dev); 424 struct mvgbec_softc *csc = device_private(device_parent(dev)); 425 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 426 uint32_t smi, val; 427 int i; 428 429 mutex_enter(&csc->sc_mtx); 430 431 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 432 DELAY(1); 433 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 434 break; 435 } 436 if (i == MVGBE_PHY_TIMEOUT) { 437 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 438 mutex_exit(&csc->sc_mtx); 439 return -1; 440 } 441 442 smi = 443 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 444 MVGBE_WRITE(csc, MVGBE_SMI, smi); 445 446 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 447 DELAY(1); 448 smi = MVGBE_READ(csc, MVGBE_SMI); 449 if (smi & MVGBE_SMI_READVALID) 450 break; 451 } 452 453 mutex_exit(&csc->sc_mtx); 454 455 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 456 i, MVGBE_PHY_TIMEOUT)); 457 458 val = smi & MVGBE_SMI_DATA_MASK; 459 460 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 461 phy, reg, val)); 462 463 return val; 464 } 465 466 static void 467 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 468 { 469 struct mvgbe_softc *sc = device_private(dev); 470 struct mvgbec_softc *csc = device_private(device_parent(dev)); 471 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 472 uint32_t smi; 473 int i; 474 475 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 476 phy, reg, val)); 477 478 mutex_enter(&csc->sc_mtx); 479 480 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 481 DELAY(1); 482 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 483 break; 484 } 485 if (i == MVGBE_PHY_TIMEOUT) { 486 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 487 mutex_exit(&csc->sc_mtx); 488 return; 489 } 490 491 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 492 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 493 MVGBE_WRITE(csc, MVGBE_SMI, smi); 494 495 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 496 DELAY(1); 497 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 498 break; 499 } 500 501 mutex_exit(&csc->sc_mtx); 502 503 if (i == MVGBE_PHY_TIMEOUT) 504 aprint_error_ifnet(ifp, "phy write timed out\n"); 505 } 506 507 static void 508 mvgbec_miibus_statchg(device_t dev) 509 { 510 511 /* nothing to do */ 512 } 513 514 515 static void 516 mvgbec_wininit(struct mvgbec_softc *sc) 517 { 518 device_t pdev = device_parent(sc->sc_dev); 519 uint64_t base; 520 uint32_t en, ac, size; 521 int window, target, attr, rv, i; 522 static int tags[] = { 523 MARVELL_TAG_SDRAM_CS0, 524 MARVELL_TAG_SDRAM_CS1, 525 MARVELL_TAG_SDRAM_CS2, 526 MARVELL_TAG_SDRAM_CS3, 527 528 MARVELL_TAG_UNDEFINED, 529 }; 530 531 /* First disable all address decode windows */ 532 en = MVGBE_BARE_EN_MASK; 533 MVGBE_WRITE(sc, MVGBE_BARE, en); 534 535 ac = 0; 536 for (window = 0, i = 0; 537 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 538 rv = marvell_winparams_by_tag(pdev, tags[i], 539 &target, &attr, &base, &size); 540 if (rv != 0 || size == 0) 541 continue; 542 543 if (base > 0xffffffffULL) { 544 if (window >= MVGBE_NREMAP) { 545 aprint_error_dev(sc->sc_dev, 546 "can't remap window %d\n", window); 547 continue; 548 } 549 MVGBE_WRITE(sc, MVGBE_HA(window), 550 (base >> 32) & 0xffffffff); 551 } 552 553 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 554 MVGBE_BASEADDR_TARGET(target) | 555 MVGBE_BASEADDR_ATTR(attr) | 556 MVGBE_BASEADDR_BASE(base)); 557 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 558 559 en &= ~(1 << window); 560 /* set full access (r/w) */ 561 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 562 window++; 563 } 564 /* allow to access decode window */ 565 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 566 567 MVGBE_WRITE(sc, MVGBE_BARE, en); 568 } 569 570 571 /* ARGSUSED */ 572 static int 573 mvgbe_match(device_t parent, struct cfdata *match, void *aux) 574 { 575 struct marvell_attach_args *mva = aux; 576 uint32_t pbase, maddrh, maddrl; 577 578 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 579 maddrh = 580 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 581 maddrl = 582 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 583 if ((maddrh | maddrl) == 0) 584 return 0; 585 586 return 1; 587 } 588 589 /* ARGSUSED */ 590 static void 591 mvgbe_attach(device_t parent, device_t self, void *aux) 592 { 593 struct mvgbe_softc *sc = device_private(self); 594 struct marvell_attach_args *mva = aux; 595 struct mvgbe_txmap_entry *entry; 596 struct ifnet *ifp; 597 bus_dma_segment_t seg; 598 bus_dmamap_t dmamap; 599 int rseg, i; 600 uint32_t maddrh, maddrl; 601 void *kva; 602 603 aprint_naive("\n"); 604 aprint_normal("\n"); 605 606 sc->sc_dev = self; 607 sc->sc_port = mva->mva_unit; 608 sc->sc_iot = mva->mva_iot; 609 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 610 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 611 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 612 aprint_error_dev(self, "Cannot map registers\n"); 613 return; 614 } 615 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 616 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 617 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 618 aprint_error_dev(self, 619 "Cannot map destination address filter registers\n"); 620 return; 621 } 622 sc->sc_dmat = mva->mva_dmat; 623 624 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 625 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 626 sc->sc_enaddr[0] = maddrh >> 24; 627 sc->sc_enaddr[1] = maddrh >> 16; 628 sc->sc_enaddr[2] = maddrh >> 8; 629 sc->sc_enaddr[3] = maddrh >> 0; 630 sc->sc_enaddr[4] = maddrl >> 8; 631 sc->sc_enaddr[5] = maddrl >> 0; 632 aprint_normal_dev(self, "Ethernet address %s\n", 633 ether_sprintf(sc->sc_enaddr)); 634 635 /* clear all ethernet port interrupts */ 636 MVGBE_WRITE(sc, MVGBE_IC, 0); 637 MVGBE_WRITE(sc, MVGBE_ICE, 0); 638 639 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 640 641 /* Allocate the descriptor queues. */ 642 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 643 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 644 aprint_error_dev(self, "can't alloc rx buffers\n"); 645 return; 646 } 647 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 648 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 649 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 650 (u_long)sizeof(struct mvgbe_ring_data)); 651 goto fail1; 652 } 653 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 654 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 655 &sc->sc_ring_map)) { 656 aprint_error_dev(self, "can't create dma map\n"); 657 goto fail2; 658 } 659 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 660 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 661 aprint_error_dev(self, "can't load dma map\n"); 662 goto fail3; 663 } 664 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 665 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 666 667 SIMPLEQ_INIT(&sc->sc_txmap_head); 668 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 669 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 670 671 if (bus_dmamap_create(sc->sc_dmat, 672 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 673 BUS_DMA_NOWAIT, &dmamap)) { 674 aprint_error_dev(self, "Can't create TX dmamap\n"); 675 goto fail4; 676 } 677 678 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 679 if (!entry) { 680 aprint_error_dev(self, "Can't alloc txmap entry\n"); 681 bus_dmamap_destroy(sc->sc_dmat, dmamap); 682 goto fail4; 683 } 684 entry->dmamap = dmamap; 685 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 686 } 687 688 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 689 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 690 691 #if 0 692 /* 693 * We can support 802.1Q VLAN-sized frames and jumbo 694 * Ethernet frames. 695 */ 696 sc->sc_ethercom.ec_capabilities |= 697 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 698 #else 699 /* XXXX: We don't know the usage of VLAN. */ 700 sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 701 #endif 702 703 /* Try to allocate memory for jumbo buffers. */ 704 if (mvgbe_alloc_jumbo_mem(sc)) { 705 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 706 goto fail4; 707 } 708 709 ifp = &sc->sc_ethercom.ec_if; 710 ifp->if_softc = sc; 711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 712 ifp->if_start = mvgbe_start; 713 ifp->if_ioctl = mvgbe_ioctl; 714 ifp->if_init = mvgbe_init; 715 ifp->if_stop = mvgbe_stop; 716 ifp->if_watchdog = mvgbe_watchdog; 717 /* 718 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 719 */ 720 sc->sc_ethercom.ec_if.if_capabilities |= 721 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 722 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 723 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 724 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 725 IFQ_SET_READY(&ifp->if_snd); 726 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 727 728 mvgbe_stop(ifp, 0); 729 730 /* 731 * Do MII setup. 732 */ 733 sc->sc_mii.mii_ifp = ifp; 734 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 735 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 736 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 737 738 sc->sc_ethercom.ec_mii = &sc->sc_mii; 739 ifmedia_init(&sc->sc_mii.mii_media, 0, 740 mvgbe_ifmedia_upd, mvgbe_ifmedia_sts); 741 mii_attach(self, &sc->sc_mii, 0xffffffff, 742 MII_PHY_ANY, MII_OFFSET_ANY, 0); 743 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 744 aprint_error_dev(self, "no PHY found!\n"); 745 ifmedia_add(&sc->sc_mii.mii_media, 746 IFM_ETHER|IFM_MANUAL, 0, NULL); 747 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 748 } else 749 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 750 751 /* 752 * Call MI attach routines. 753 */ 754 if_attach(ifp); 755 756 ether_ifattach(ifp, sc->sc_enaddr); 757 758 #if NRND > 0 759 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 760 RND_TYPE_NET, 0); 761 #endif 762 763 return; 764 765 fail4: 766 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 767 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 768 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 769 } 770 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 771 fail3: 772 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 773 fail2: 774 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 775 fail1: 776 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 777 return; 778 } 779 780 781 static int 782 mvgbe_intr(void *arg) 783 { 784 struct mvgbe_softc *sc = arg; 785 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 786 uint32_t ic, ice, datum = 0; 787 int claimed = 0; 788 789 for (;;) { 790 ice = MVGBE_READ(sc, MVGBE_ICE); 791 ic = MVGBE_READ(sc, MVGBE_IC); 792 793 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 794 if (ic == 0 && ice == 0) 795 break; 796 797 datum = datum ^ ic ^ ice; 798 799 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 800 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 801 802 claimed = 1; 803 804 if (ice & MVGBE_ICE_LINKCHG) { 805 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 806 /* Enable port RX and TX. */ 807 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 808 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 809 } else { 810 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 811 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 812 } 813 } 814 815 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 816 mvgbe_rxeof(sc); 817 818 if (ice & (MVGBE_ICE_TXBUF | MVGBE_ICE_TXERR)) 819 mvgbe_txeof(sc); 820 } 821 822 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 823 mvgbe_start(ifp); 824 825 #if NRND > 0 826 if (RND_ENABLED(&sc->sc_rnd_source)) 827 rnd_add_uint32(&sc->sc_rnd_source, datum); 828 #endif 829 830 return claimed; 831 } 832 833 static void 834 mvgbe_start(struct ifnet *ifp) 835 { 836 struct mvgbe_softc *sc = ifp->if_softc; 837 struct mbuf *m_head = NULL; 838 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 839 int pkts = 0; 840 841 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 842 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 843 844 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 845 return; 846 /* If Link is DOWN, can't start TX */ 847 if (!(MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP)) 848 return; 849 850 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 851 IFQ_POLL(&ifp->if_snd, m_head); 852 if (m_head == NULL) 853 break; 854 855 /* 856 * Pack the data into the transmit ring. If we 857 * don't have room, set the OACTIVE flag and wait 858 * for the NIC to drain the ring. 859 */ 860 if (mvgbe_encap(sc, m_head, &idx)) { 861 ifp->if_flags |= IFF_OACTIVE; 862 break; 863 } 864 865 /* now we are committed to transmit the packet */ 866 IFQ_DEQUEUE(&ifp->if_snd, m_head); 867 pkts++; 868 869 /* 870 * If there's a BPF listener, bounce a copy of this frame 871 * to him. 872 */ 873 if (ifp->if_bpf) 874 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 875 } 876 if (pkts == 0) 877 return; 878 879 /* Transmit at Queue 0 */ 880 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 881 sc->sc_cdata.mvgbe_tx_prod = idx; 882 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 883 884 /* 885 * Set a timeout in case the chip goes out to lunch. 886 */ 887 ifp->if_timer = 5; 888 } 889 } 890 891 static int 892 mvgbe_ioctl(struct ifnet *ifp, u_long command, void *data) 893 { 894 struct mvgbe_softc *sc = ifp->if_softc; 895 struct ifreq *ifr = data; 896 struct mii_data *mii; 897 int s, error = 0; 898 899 s = splnet(); 900 901 switch (command) { 902 case SIOCSIFFLAGS: 903 DPRINTFN(2, ("mvgbe_ioctl IFFLAGS\n")); 904 if (ifp->if_flags & IFF_UP) 905 mvgbe_init(ifp); 906 else 907 if (ifp->if_flags & IFF_RUNNING) 908 mvgbe_stop(ifp, 0); 909 sc->sc_if_flags = ifp->if_flags; 910 error = 0; 911 break; 912 913 case SIOCGIFMEDIA: 914 case SIOCSIFMEDIA: 915 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 916 mii = &sc->sc_mii; 917 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 918 break; 919 920 default: 921 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 922 error = ether_ioctl(ifp, command, data); 923 if (error == ENETRESET) { 924 if (ifp->if_flags & IFF_RUNNING) { 925 mvgbe_setmulti(sc); 926 DPRINTFN(2, 927 ("mvgbe_ioctl setmulti called\n")); 928 } 929 error = 0; 930 } 931 break; 932 } 933 934 splx(s); 935 936 return error; 937 } 938 939 static int 940 mvgbe_init(struct ifnet *ifp) 941 { 942 struct mvgbe_softc *sc = ifp->if_softc; 943 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 944 struct mii_data *mii = &sc->sc_mii; 945 uint32_t reg; 946 int i, s; 947 948 DPRINTFN(2, ("mvgbe_init\n")); 949 950 s = splnet(); 951 952 if (ifp->if_flags & IFF_RUNNING) { 953 splx(s); 954 return 0; 955 } 956 957 /* Cancel pending I/O and free all RX/TX buffers. */ 958 mvgbe_stop(ifp, 0); 959 960 /* clear all ethernet port interrupts */ 961 MVGBE_WRITE(sc, MVGBE_IC, 0); 962 MVGBE_WRITE(sc, MVGBE_ICE, 0); 963 964 /* Init TX/RX descriptors */ 965 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 966 aprint_error_ifnet(ifp, 967 "initialization failed: no memory for tx buffers\n"); 968 splx(s); 969 return ENOBUFS; 970 } 971 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 972 aprint_error_ifnet(ifp, 973 "initialization failed: no memory for rx buffers\n"); 974 splx(s); 975 return ENOBUFS; 976 } 977 978 MVGBE_WRITE(sc, MVGBE_PSC, 979 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 980 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 981 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 982 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9700) | /* Always 9700 OK */ 983 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 984 /* XXXX: mvgbe(4) always use RGMII. */ 985 MVGBE_WRITE(sc, MVGBE_PSC1, 986 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 987 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 988 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 989 990 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 991 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 992 993 if (csc->sc_fix_tqtb) { 994 /* 995 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 996 * And offset 0x72704 must be programmed to 0x03ffffff. 997 * Queue 1 through 7 must be programmed to 0x0. 998 */ 999 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1000 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1001 for (i = 1; i < 8; i++) { 1002 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1003 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1004 } 1005 } else 1006 for (i = 1; i < 8; i++) { 1007 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1008 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1009 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1010 } 1011 1012 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1013 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1014 MVGBE_WRITE(sc, MVGBE_SDC, 1015 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1016 #if BYTE_ORDER == LITTLE_ENDIAN 1017 MVGBE_SDC_BLMR | /* Big/Litlle Endian Receive Mode: No swap */ 1018 MVGBE_SDC_BLMT | /* Big/Litlle Endian Transmit Mode: No swap */ 1019 #endif 1020 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1021 1022 mii_mediachg(mii); 1023 1024 /* Enable port */ 1025 reg = MVGBE_READ(sc, MVGBE_PSC); 1026 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1027 1028 /* If Link is UP, Start RX and TX traffic */ 1029 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 1030 /* Enable port RX/TX. */ 1031 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1032 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 1033 } 1034 1035 /* Enable interrupt masks */ 1036 MVGBE_WRITE(sc, MVGBE_PIM, 1037 MVGBE_IC_RXBUF | 1038 MVGBE_IC_EXTEND | 1039 MVGBE_IC_RXBUFQ_MASK | 1040 MVGBE_IC_RXERROR | 1041 MVGBE_IC_RXERRQ_MASK); 1042 MVGBE_WRITE(sc, MVGBE_PEIM, 1043 MVGBE_ICE_TXBUF | 1044 MVGBE_ICE_TXERR | 1045 MVGBE_ICE_LINKCHG); 1046 1047 ifp->if_flags |= IFF_RUNNING; 1048 ifp->if_flags &= ~IFF_OACTIVE; 1049 1050 splx(s); 1051 1052 return 0; 1053 } 1054 1055 /* ARGSUSED */ 1056 static void 1057 mvgbe_stop(struct ifnet *ifp, int disable) 1058 { 1059 struct mvgbe_softc *sc = ifp->if_softc; 1060 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1061 uint32_t reg; 1062 int i, cnt; 1063 1064 DPRINTFN(2, ("mvgbe_stop\n")); 1065 1066 /* Stop Rx port activity. Check port Rx activity. */ 1067 reg = MVGBE_READ(sc, MVGBE_RQC); 1068 if (reg & MVGBE_RQC_ENQ_MASK) 1069 /* Issue stop command for active channels only */ 1070 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1071 1072 /* Stop Tx port activity. Check port Tx activity. */ 1073 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ) 1074 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 1075 1076 /* Force link down */ 1077 reg = MVGBE_READ(sc, MVGBE_PSC); 1078 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1079 1080 #define RX_DISABLE_TIMEOUT 0x1000000 1081 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1082 /* Wait for all Rx activity to terminate. */ 1083 cnt = 0; 1084 do { 1085 if (cnt >= RX_DISABLE_TIMEOUT) { 1086 aprint_error_ifnet(ifp, 1087 "timeout for RX stopped. rqc 0x%x\n", reg); 1088 break; 1089 } 1090 cnt++; 1091 1092 /* 1093 * Check Receive Queue Command register that all Rx queues 1094 * are stopped 1095 */ 1096 reg = MVGBE_READ(sc, MVGBE_RQC); 1097 } while (reg & 0xff); 1098 1099 /* Double check to verify that TX FIFO is empty */ 1100 cnt = 0; 1101 while (1) { 1102 do { 1103 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1104 aprint_error_ifnet(ifp, 1105 "timeout for TX FIFO empty. status 0x%x\n", 1106 reg); 1107 break; 1108 } 1109 cnt++; 1110 1111 reg = MVGBE_READ(sc, MVGBE_PS); 1112 } while 1113 (!(reg & MVGBE_PS_TXFIFOEMP) || reg & MVGBE_PS_TXINPROG); 1114 1115 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1116 break; 1117 1118 /* Double check */ 1119 reg = MVGBE_READ(sc, MVGBE_PS); 1120 if (reg & MVGBE_PS_TXFIFOEMP && !(reg & MVGBE_PS_TXINPROG)) 1121 break; 1122 else 1123 aprint_error_ifnet(ifp, 1124 "TX FIFO empty double check failed." 1125 " %d loops, status 0x%x\n", cnt, reg); 1126 } 1127 1128 /* Reset the Enable bit in the Port Serial Control Register */ 1129 reg = MVGBE_READ(sc, MVGBE_PSC); 1130 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1131 1132 /* Disable interrupts */ 1133 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1134 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1135 1136 /* Free RX and TX mbufs still in the queues. */ 1137 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1138 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1139 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1140 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1141 } 1142 } 1143 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1144 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1145 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1146 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1147 } 1148 } 1149 1150 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1151 } 1152 1153 static void 1154 mvgbe_watchdog(struct ifnet *ifp) 1155 { 1156 struct mvgbe_softc *sc = ifp->if_softc; 1157 1158 /* 1159 * Reclaim first as there is a possibility of losing Tx completion 1160 * interrupts. 1161 */ 1162 mvgbe_txeof(sc); 1163 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1164 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1165 1166 ifp->if_oerrors++; 1167 1168 mvgbe_init(ifp); 1169 } 1170 } 1171 1172 1173 /* 1174 * Set media options. 1175 */ 1176 static int 1177 mvgbe_ifmedia_upd(struct ifnet *ifp) 1178 { 1179 struct mvgbe_softc *sc = ifp->if_softc; 1180 1181 mii_mediachg(&sc->sc_mii); 1182 return 0; 1183 } 1184 1185 /* 1186 * Report current media status. 1187 */ 1188 static void 1189 mvgbe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1190 { 1191 struct mvgbe_softc *sc = ifp->if_softc; 1192 1193 mii_pollstat(&sc->sc_mii); 1194 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1195 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1196 } 1197 1198 1199 static int 1200 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1201 { 1202 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1203 struct mvgbe_ring_data *rd = sc->sc_rdata; 1204 int i; 1205 1206 bzero((char *)rd->mvgbe_rx_ring, 1207 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1208 1209 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1210 cd->mvgbe_rx_chain[i].mvgbe_desc = 1211 &rd->mvgbe_rx_ring[i]; 1212 if (i == MVGBE_RX_RING_CNT - 1) { 1213 cd->mvgbe_rx_chain[i].mvgbe_next = 1214 &cd->mvgbe_rx_chain[0]; 1215 rd->mvgbe_rx_ring[i].nextdescptr = 1216 MVGBE_RX_RING_ADDR(sc, 0); 1217 } else { 1218 cd->mvgbe_rx_chain[i].mvgbe_next = 1219 &cd->mvgbe_rx_chain[i + 1]; 1220 rd->mvgbe_rx_ring[i].nextdescptr = 1221 MVGBE_RX_RING_ADDR(sc, i + 1); 1222 } 1223 } 1224 1225 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1226 if (mvgbe_newbuf(sc, i, NULL, 1227 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1228 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1229 "failed alloc of %dth mbuf\n", i); 1230 return ENOBUFS; 1231 } 1232 } 1233 sc->sc_cdata.mvgbe_rx_prod = 0; 1234 sc->sc_cdata.mvgbe_rx_cons = 0; 1235 1236 return 0; 1237 } 1238 1239 static int 1240 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1241 { 1242 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1243 struct mvgbe_ring_data *rd = sc->sc_rdata; 1244 int i; 1245 1246 bzero((char *)sc->sc_rdata->mvgbe_tx_ring, 1247 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1248 1249 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1250 cd->mvgbe_tx_chain[i].mvgbe_desc = 1251 &rd->mvgbe_tx_ring[i]; 1252 if (i == MVGBE_TX_RING_CNT - 1) { 1253 cd->mvgbe_tx_chain[i].mvgbe_next = 1254 &cd->mvgbe_tx_chain[0]; 1255 rd->mvgbe_tx_ring[i].nextdescptr = 1256 MVGBE_TX_RING_ADDR(sc, 0); 1257 } else { 1258 cd->mvgbe_tx_chain[i].mvgbe_next = 1259 &cd->mvgbe_tx_chain[i + 1]; 1260 rd->mvgbe_tx_ring[i].nextdescptr = 1261 MVGBE_TX_RING_ADDR(sc, i + 1); 1262 } 1263 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1264 } 1265 1266 sc->sc_cdata.mvgbe_tx_prod = 0; 1267 sc->sc_cdata.mvgbe_tx_cons = 0; 1268 sc->sc_cdata.mvgbe_tx_cnt = 0; 1269 1270 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1271 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1272 1273 return 0; 1274 } 1275 1276 static int 1277 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1278 bus_dmamap_t dmamap) 1279 { 1280 struct mbuf *m_new = NULL; 1281 struct mvgbe_chain *c; 1282 struct mvgbe_rx_desc *r; 1283 int align; 1284 1285 if (m == NULL) { 1286 void *buf = NULL; 1287 1288 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1289 if (m_new == NULL) { 1290 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1291 "no memory for rx list -- packet dropped!\n"); 1292 return ENOBUFS; 1293 } 1294 1295 /* Allocate the jumbo buffer */ 1296 buf = mvgbe_jalloc(sc); 1297 if (buf == NULL) { 1298 m_freem(m_new); 1299 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1300 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1301 return ENOBUFS; 1302 } 1303 1304 /* Attach the buffer to the mbuf */ 1305 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1306 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1307 } else { 1308 /* 1309 * We're re-using a previously allocated mbuf; 1310 * be sure to re-init pointers and lengths to 1311 * default values. 1312 */ 1313 m_new = m; 1314 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1315 m_new->m_data = m_new->m_ext.ext_buf; 1316 } 1317 align = (u_long)m_new->m_data & MVGBE_BUF_MASK; 1318 if (align != 0) 1319 m_adj(m_new, MVGBE_BUF_ALIGN - align); 1320 1321 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1322 r = c->mvgbe_desc; 1323 c->mvgbe_mbuf = m_new; 1324 r->bufptr = dmamap->dm_segs[0].ds_addr + 1325 (((vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf)); 1326 r->bufsize = MVGBE_JLEN & ~MVGBE_BUF_MASK; 1327 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1328 1329 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1330 1331 return 0; 1332 } 1333 1334 /* 1335 * Memory management for jumbo frames. 1336 */ 1337 1338 static int 1339 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1340 { 1341 char *ptr, *kva; 1342 bus_dma_segment_t seg; 1343 int i, rseg, state, error; 1344 struct mvgbe_jpool_entry *entry; 1345 1346 state = error = 0; 1347 1348 /* Grab a big chunk o' storage. */ 1349 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1350 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1351 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1352 return ENOBUFS; 1353 } 1354 1355 state = 1; 1356 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1357 (void **)&kva, BUS_DMA_NOWAIT)) { 1358 aprint_error_dev(sc->sc_dev, 1359 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1360 error = ENOBUFS; 1361 goto out; 1362 } 1363 1364 state = 2; 1365 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1366 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1367 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1368 error = ENOBUFS; 1369 goto out; 1370 } 1371 1372 state = 3; 1373 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1374 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1375 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1376 error = ENOBUFS; 1377 goto out; 1378 } 1379 1380 state = 4; 1381 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1382 DPRINTFN(1,("mvgbe_jumbo_buf = 0x%p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1383 1384 LIST_INIT(&sc->sc_jfree_listhead); 1385 LIST_INIT(&sc->sc_jinuse_listhead); 1386 1387 /* 1388 * Now divide it up into 9K pieces and save the addresses 1389 * in an array. 1390 */ 1391 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1392 for (i = 0; i < MVGBE_JSLOTS; i++) { 1393 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1394 ptr += MVGBE_JLEN; 1395 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1396 if (entry == NULL) { 1397 aprint_error_dev(sc->sc_dev, 1398 "no memory for jumbo buffer queue!\n"); 1399 error = ENOBUFS; 1400 goto out; 1401 } 1402 entry->slot = i; 1403 if (i) 1404 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1405 jpool_entries); 1406 else 1407 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1408 jpool_entries); 1409 } 1410 out: 1411 if (error != 0) { 1412 switch (state) { 1413 case 4: 1414 bus_dmamap_unload(sc->sc_dmat, 1415 sc->sc_cdata.mvgbe_rx_jumbo_map); 1416 case 3: 1417 bus_dmamap_destroy(sc->sc_dmat, 1418 sc->sc_cdata.mvgbe_rx_jumbo_map); 1419 case 2: 1420 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1421 case 1: 1422 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1423 break; 1424 default: 1425 break; 1426 } 1427 } 1428 1429 return error; 1430 } 1431 1432 /* 1433 * Allocate a jumbo buffer. 1434 */ 1435 static void * 1436 mvgbe_jalloc(struct mvgbe_softc *sc) 1437 { 1438 struct mvgbe_jpool_entry *entry; 1439 1440 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1441 1442 if (entry == NULL) 1443 return NULL; 1444 1445 LIST_REMOVE(entry, jpool_entries); 1446 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1447 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1448 } 1449 1450 /* 1451 * Release a jumbo buffer. 1452 */ 1453 static void 1454 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1455 { 1456 struct mvgbe_jpool_entry *entry; 1457 struct mvgbe_softc *sc; 1458 int i, s; 1459 1460 /* Extract the softc struct pointer. */ 1461 sc = (struct mvgbe_softc *)arg; 1462 1463 if (sc == NULL) 1464 panic("%s: can't find softc pointer!", __func__); 1465 1466 /* calculate the slot this buffer belongs to */ 1467 1468 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1469 1470 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1471 panic("%s: asked to free buffer that we don't manage!", 1472 __func__); 1473 1474 s = splvm(); 1475 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1476 if (entry == NULL) 1477 panic("%s: buffer not in use!", __func__); 1478 entry->slot = i; 1479 LIST_REMOVE(entry, jpool_entries); 1480 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1481 1482 if (__predict_true(m != NULL)) 1483 pool_cache_put(mb_cache, m); 1484 splx(s); 1485 } 1486 1487 static int 1488 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1489 uint32_t *txidx) 1490 { 1491 struct mvgbe_tx_desc *f = NULL; 1492 struct mvgbe_txmap_entry *entry; 1493 bus_dma_segment_t *txseg; 1494 bus_dmamap_t txmap; 1495 uint32_t first, current, last, cmdsts = 0; 1496 int m_csumflags, i; 1497 1498 DPRINTFN(3, ("mvgbe_encap\n")); 1499 1500 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1501 if (entry == NULL) { 1502 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1503 return ENOBUFS; 1504 } 1505 txmap = entry->dmamap; 1506 1507 first = current = last = *txidx; 1508 1509 /* 1510 * Preserve m_pkthdr.csum_flags here since m_head might be 1511 * updated by m_defrag() 1512 */ 1513 m_csumflags = m_head->m_pkthdr.csum_flags; 1514 1515 /* 1516 * Start packing the mbufs in this chain into 1517 * the fragment pointers. Stop when we run out 1518 * of fragments or hit the end of the mbuf chain. 1519 */ 1520 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1521 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1522 return ENOBUFS; 1523 } 1524 1525 /* Sync the DMA map. */ 1526 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1527 BUS_DMASYNC_PREWRITE); 1528 1529 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1530 MVGBE_TX_RING_CNT) { 1531 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1532 bus_dmamap_unload(sc->sc_dmat, txmap); 1533 return ENOBUFS; 1534 } 1535 1536 txseg = txmap->dm_segs; 1537 1538 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1539 1540 for (i = 0; i < txmap->dm_nsegs; i++) { 1541 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1542 f->bufptr = txseg[i].ds_addr; 1543 f->bytecnt = txseg[i].ds_len; 1544 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1545 last = current; 1546 current = (current + 1) % MVGBE_TX_RING_CNT; 1547 } 1548 1549 if (m_csumflags & M_CSUM_IPv4) 1550 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1551 if (m_csumflags & M_CSUM_TCPv4) 1552 cmdsts |= 1553 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1554 if (m_csumflags & M_CSUM_UDPv4) 1555 cmdsts |= 1556 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1557 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1558 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1559 1560 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1561 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1562 } 1563 if (txmap->dm_nsegs == 1) 1564 f->cmdsts = cmdsts | 1565 MVGBE_BUFFER_OWNED_BY_DMA | 1566 MVGBE_TX_GENERATE_CRC | 1567 MVGBE_TX_ENABLE_INTERRUPT | 1568 MVGBE_TX_ZERO_PADDING | 1569 MVGBE_TX_FIRST_DESC | 1570 MVGBE_TX_LAST_DESC; 1571 else { 1572 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1573 f->cmdsts = cmdsts | 1574 MVGBE_BUFFER_OWNED_BY_DMA | 1575 MVGBE_TX_GENERATE_CRC | 1576 MVGBE_TX_FIRST_DESC; 1577 1578 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1579 f->cmdsts = 1580 MVGBE_BUFFER_OWNED_BY_DMA | 1581 MVGBE_TX_ENABLE_INTERRUPT | 1582 MVGBE_TX_ZERO_PADDING | 1583 MVGBE_TX_LAST_DESC; 1584 } 1585 1586 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1587 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1588 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1589 1590 /* Sync descriptors before handing to chip */ 1591 MVGBE_CDTXSYNC(sc, *txidx, txmap->dm_nsegs, 1592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1593 1594 sc->sc_cdata.mvgbe_tx_cnt += i; 1595 *txidx = current; 1596 1597 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1598 1599 return 0; 1600 } 1601 1602 static void 1603 mvgbe_rxeof(struct mvgbe_softc *sc) 1604 { 1605 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1606 struct mvgbe_rx_desc *cur_rx; 1607 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1608 struct mbuf *m; 1609 bus_dmamap_t dmamap; 1610 uint32_t rxstat; 1611 int idx, cur, total_len; 1612 1613 idx = sc->sc_cdata.mvgbe_rx_prod; 1614 1615 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1616 1617 for (;;) { 1618 cur = idx; 1619 1620 /* Sync the descriptor */ 1621 MVGBE_CDRXSYNC(sc, idx, 1622 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1623 1624 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1625 1626 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1627 MVGBE_BUFFER_OWNED_BY_DMA) { 1628 /* Invalidate the descriptor -- it's not ready yet */ 1629 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1630 sc->sc_cdata.mvgbe_rx_prod = idx; 1631 break; 1632 } 1633 #ifdef DIAGNOSTIC 1634 if ((cur_rx->cmdsts & 1635 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1636 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1637 panic( 1638 "mvgbe_rxeof: buffer size is smaller than packet"); 1639 #endif 1640 1641 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1642 1643 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1644 BUS_DMASYNC_POSTREAD); 1645 1646 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1647 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1648 total_len = cur_rx->bytecnt; 1649 rxstat = cur_rx->cmdsts; 1650 1651 cdata->mvgbe_rx_map[idx] = NULL; 1652 1653 idx = (idx + 1) % MVGBE_RX_RING_CNT; 1654 1655 if (rxstat & MVGBE_ERROR_SUMMARY) { 1656 #if 0 1657 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1658 1659 if (err == MVGBE_RX_CRC_ERROR) 1660 ifp->if_ierrors++; 1661 if (err == MVGBE_RX_OVERRUN_ERROR) 1662 ifp->if_ierrors++; 1663 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1664 ifp->if_ierrors++; 1665 if (err == MVGBE_RX_RESOURCE_ERROR) 1666 ifp->if_ierrors++; 1667 #else 1668 ifp->if_ierrors++; 1669 #endif 1670 mvgbe_newbuf(sc, cur, m, dmamap); 1671 continue; 1672 } 1673 1674 if (total_len > MVGBE_RX_CSUM_MIN_BYTE) { 1675 /* Check IP header checksum */ 1676 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1677 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1678 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 1679 m->m_pkthdr.csum_flags |= 1680 M_CSUM_IPv4_BAD; 1681 } 1682 /* Check TCP/UDP checksum */ 1683 if (rxstat & MVGBE_RX_L4_TYPE_TCP) 1684 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1685 else if (rxstat & MVGBE_RX_L4_TYPE_UDP) 1686 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1687 if (!(rxstat & MVGBE_RX_L4_CHECKSUM)) 1688 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1689 } 1690 1691 /* 1692 * Try to allocate a new jumbo buffer. If that 1693 * fails, copy the packet to mbufs and put the 1694 * jumbo buffer back in the ring so it can be 1695 * re-used. If allocating mbufs fails, then we 1696 * have to drop the packet. 1697 */ 1698 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 1699 struct mbuf *m0; 1700 1701 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 1702 mvgbe_newbuf(sc, cur, m, dmamap); 1703 if (m0 == NULL) { 1704 aprint_error_ifnet(ifp, 1705 "no receive buffers available --" 1706 " packet dropped!\n"); 1707 ifp->if_ierrors++; 1708 continue; 1709 } 1710 m = m0; 1711 } else { 1712 m->m_pkthdr.rcvif = ifp; 1713 m->m_pkthdr.len = m->m_len = total_len; 1714 } 1715 1716 /* Skip on first 2byte (HW header) */ 1717 m_adj(m, MVGBE_HWHEADER_SIZE); 1718 m->m_flags |= M_HASFCS; 1719 1720 ifp->if_ipackets++; 1721 1722 if (ifp->if_bpf) 1723 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1724 1725 /* pass it on. */ 1726 (*ifp->if_input)(ifp, m); 1727 } 1728 } 1729 1730 static void 1731 mvgbe_txeof(struct mvgbe_softc *sc) 1732 { 1733 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1734 struct mvgbe_tx_desc *cur_tx; 1735 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1736 struct mvgbe_txmap_entry *entry; 1737 int idx; 1738 1739 DPRINTFN(3, ("mvgbe_txeof\n")); 1740 1741 /* 1742 * Go through our tx ring and free mbufs for those 1743 * frames that have been sent. 1744 */ 1745 idx = cdata->mvgbe_tx_cons; 1746 while (idx != cdata->mvgbe_tx_prod) { 1747 MVGBE_CDTXSYNC(sc, idx, 1, 1748 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1749 1750 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 1751 #ifdef MVGBE_DEBUG 1752 if (mvgbe_debug >= 3) 1753 mvgbe_dump_txdesc(cur_tx, idx); 1754 #endif 1755 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1756 MVGBE_BUFFER_OWNED_BY_DMA) { 1757 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 1758 break; 1759 } 1760 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 1761 ifp->if_opackets++; 1762 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 1763 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 1764 1765 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 1766 ifp->if_collisions++; 1767 if (err == MVGBE_TX_UNDERRUN_ERROR) 1768 ifp->if_oerrors++; 1769 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 1770 ifp->if_collisions++; 1771 } 1772 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 1773 entry = cdata->mvgbe_tx_map[idx]; 1774 1775 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 1776 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 1777 1778 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 1779 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1780 1781 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 1782 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 1783 cdata->mvgbe_tx_map[idx] = NULL; 1784 } 1785 cdata->mvgbe_tx_cnt--; 1786 idx = (idx + 1) % MVGBE_TX_RING_CNT; 1787 } 1788 if (cdata->mvgbe_tx_cnt == 0) 1789 ifp->if_timer = 0; 1790 1791 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 1792 ifp->if_flags &= ~IFF_OACTIVE; 1793 1794 cdata->mvgbe_tx_cons = idx; 1795 } 1796 1797 static void 1798 mvgbe_setmulti(struct mvgbe_softc *sc) 1799 { 1800 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 1801 uint32_t pxc, dfut, upm = 0, filter = 0; 1802 uint8_t ln = sc->sc_enaddr[5] & 0xf; /* last nibble */ 1803 1804 if (ifp->if_flags & IFF_PROMISC) { 1805 upm = MVGBE_PXC_UPM; 1806 filter = 1807 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1808 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1809 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1810 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1811 } else if (ifp->if_flags & IFF_ALLMULTI) { 1812 filter = 1813 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1814 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1815 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1816 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1817 } 1818 1819 /* Set Unicast Promiscuous mode */ 1820 pxc = MVGBE_READ(sc, MVGBE_PXC); 1821 pxc &= ~MVGBE_PXC_UPM; 1822 pxc |= upm; 1823 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 1824 1825 /* Set Destination Address Filter Multicast Tables */ 1826 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, filter, MVGBE_NDFSMT); 1827 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, filter, MVGBE_NDFOMT); 1828 1829 if (ifp->if_flags & IFF_PROMISC) { 1830 /* necessary ? */ 1831 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, filter, MVGBE_NDFUT); 1832 return; 1833 } 1834 1835 /* Set Destination Address Filter Unicast Table */ 1836 dfut = MVGBE_READ_FILTER(sc, MVGBE_DFUT + (ln & 0x0c)); 1837 dfut &= ~MVGBE_DF(ln & 0x03, MVGBE_DF_QUEUE_MASK);; 1838 dfut |= MVGBE_DF(ln & 0x03, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1839 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT + (ln & 0x0c), dfut, 1); 1840 } 1841 1842 #ifdef MVGBE_DEBUG 1843 static void 1844 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 1845 { 1846 #define DESC_PRINT(X) \ 1847 if (X) \ 1848 printf("txdesc[%d]." #X "=%#x\n", idx, X); 1849 1850 #if BYTE_ORDER == BIG_ENDIAN 1851 DESC_PRINT(desc->bytecnt); 1852 DESC_PRINT(desc->l4ichk); 1853 DESC_PRINT(desc->cmdsts); 1854 DESC_PRINT(desc->nextdescptr); 1855 DESC_PRINT(desc->bufptr); 1856 #else /* LITTLE_ENDIAN */ 1857 DESC_PRINT(desc->cmdsts); 1858 DESC_PRINT(desc->l4ichk); 1859 DESC_PRINT(desc->bytecnt); 1860 DESC_PRINT(desc->bufptr); 1861 DESC_PRINT(desc->nextdescptr); 1862 #endif 1863 #undef DESC_PRINT 1864 printf("txdesc[%d].desc->returninfo=%#lx\n", idx, desc->returninfo); 1865 printf("txdesc[%d].desc->alignbufptr=%p\n", idx, desc->alignbufptr); 1866 } 1867 #endif 1868
Indexes created Wed Oct 22 13:09:56 GMT 2025