if_mvgbe.c revision 1.6
1 /* $NetBSD: if_mvgbe.c,v 1.6 2011/03/05 18:28:13 christos Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.6 2011/03/05 18:28:13 christos Exp $"); 29 30 #include "rnd.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/endian.h> 36 #include <sys/errno.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 #include <sys/sockio.h> 40 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 #include <dev/marvell/mvgbereg.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/in_systm.h> 51 #include <netinet/ip.h> 52 53 #include <net/bpf.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include "locators.h" 62 63 /* #define MVGBE_DEBUG 3 */ 64 #ifdef MVGBE_DEBUG 65 #define DPRINTF(x) if (mvgbe_debug) printf x 66 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 67 int mvgbe_debug = MVGBE_DEBUG; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n,x) 71 #endif 72 73 74 #define MVGBE_READ(sc, reg) \ 75 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 76 #define MVGBE_WRITE(sc, reg, val) \ 77 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 78 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 79 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 80 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 81 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 82 83 #define MVGBE_TX_RING_CNT 256 84 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 85 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 86 #define MVGBE_RX_RING_CNT 256 87 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 88 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 89 90 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 91 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 92 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 93 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 94 95 #define MVGBE_JSLOTS 384 /* XXXX */ 96 #define MVGBE_JLEN ((MVGBE_MRU + MVGBE_RXBUF_ALIGN)&~MVGBE_RXBUF_MASK) 97 #define MVGBE_NTXSEG 30 98 #define MVGBE_JPAGESZ PAGE_SIZE 99 #define MVGBE_RESID \ 100 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 101 #define MVGBE_JMEM \ 102 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 103 104 #define MVGBE_TX_RING_ADDR(sc, i) \ 105 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 106 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 107 108 #define MVGBE_RX_RING_ADDR(sc, i) \ 109 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 110 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 111 112 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 113 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 114 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 115 116 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 117 do { \ 118 int __x, __n; \ 119 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 120 \ 121 __x = (x); \ 122 __n = (n); \ 123 \ 124 /* If it will wrap around, sync to the end of the ring. */ \ 125 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 126 bus_dmamap_sync((sc)->sc_dmat, \ 127 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 128 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 129 __n -= (MVGBE_TX_RING_CNT - __x); \ 130 __x = 0; \ 131 } \ 132 \ 133 /* Now sync whatever is left. */ \ 134 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 135 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 136 } while (0 /*CONSTCOND*/) 137 138 #define MVGBE_CDRXSYNC(sc, x, ops) \ 139 do { \ 140 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 141 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 142 } while (/*CONSTCOND*/0) 143 144 145 struct mvgbe_jpool_entry { 146 int slot; 147 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 148 }; 149 150 struct mvgbe_chain { 151 void *mvgbe_desc; 152 struct mbuf *mvgbe_mbuf; 153 struct mvgbe_chain *mvgbe_next; 154 }; 155 156 struct mvgbe_txmap_entry { 157 bus_dmamap_t dmamap; 158 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 159 }; 160 161 struct mvgbe_chain_data { 162 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 163 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 164 int mvgbe_tx_prod; 165 int mvgbe_tx_cons; 166 int mvgbe_tx_cnt; 167 168 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 169 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 170 bus_dmamap_t mvgbe_rx_jumbo_map; 171 int mvgbe_rx_prod; 172 int mvgbe_rx_cons; 173 int mvgbe_rx_cnt; 174 175 /* Stick the jumbo mem management stuff here too. */ 176 void *mvgbe_jslots[MVGBE_JSLOTS]; 177 void *mvgbe_jumbo_buf; 178 }; 179 180 struct mvgbe_ring_data { 181 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 182 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 183 }; 184 185 struct mvgbec_softc { 186 device_t sc_dev; 187 int sc_unit; 188 189 bus_space_tag_t sc_iot; 190 bus_space_handle_t sc_ioh; 191 192 kmutex_t sc_mtx; 193 194 int sc_fix_tqtb; 195 }; 196 197 struct mvgbe_softc { 198 device_t sc_dev; 199 int sc_port; 200 201 bus_space_tag_t sc_iot; 202 bus_space_handle_t sc_ioh; 203 bus_space_handle_t sc_dafh; /* dest address filter handle */ 204 bus_dma_tag_t sc_dmat; 205 206 struct ethercom sc_ethercom; 207 struct mii_data sc_mii; 208 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 209 210 struct mvgbe_chain_data sc_cdata; 211 struct mvgbe_ring_data *sc_rdata; 212 bus_dmamap_t sc_ring_map; 213 int sc_if_flags; 214 215 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 216 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 217 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 218 219 #if NRND > 0 220 rndsource_element_t sc_rnd_source; 221 #endif 222 }; 223 224 225 /* Gigabit Ethernet Unit Global part functions */ 226 227 static int mvgbec_match(device_t, struct cfdata *, void *); 228 static void mvgbec_attach(device_t, device_t, void *); 229 230 static int mvgbec_print(void *, const char *); 231 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 232 233 /* MII funcstions */ 234 static int mvgbec_miibus_readreg(device_t, int, int); 235 static void mvgbec_miibus_writereg(device_t, int, int, int); 236 static void mvgbec_miibus_statchg(device_t); 237 238 static void mvgbec_wininit(struct mvgbec_softc *); 239 240 /* Gigabit Ethernet Port part functions */ 241 242 static int mvgbe_match(device_t, struct cfdata *, void *); 243 static void mvgbe_attach(device_t, device_t, void *); 244 245 static int mvgbe_intr(void *); 246 247 static void mvgbe_start(struct ifnet *); 248 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 249 static int mvgbe_init(struct ifnet *); 250 static void mvgbe_stop(struct ifnet *, int); 251 static void mvgbe_watchdog(struct ifnet *); 252 253 static int mvgbe_ifflags_cb(struct ethercom *); 254 255 static int mvgbe_mediachange(struct ifnet *); 256 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 257 258 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 259 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 260 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 261 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 262 static void *mvgbe_jalloc(struct mvgbe_softc *); 263 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 264 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 265 static void mvgbe_rxeof(struct mvgbe_softc *); 266 static void mvgbe_txeof(struct mvgbe_softc *); 267 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 268 static void mvgbe_filter_setup(struct mvgbe_softc *); 269 #ifdef MVGBE_DEBUG 270 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 271 #endif 272 273 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 274 mvgbec_match, mvgbec_attach, NULL, NULL); 275 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 276 mvgbec_match, mvgbec_attach, NULL, NULL); 277 278 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 279 mvgbe_match, mvgbe_attach, NULL, NULL); 280 281 device_t mvgbec0 = NULL; 282 283 struct mvgbe_port { 284 int model; 285 int unit; 286 int ports; 287 int irqs[3]; 288 int flags; 289 #define FLAGS_FIX_TQTB (1 << 0) 290 } mvgbe_ports[] = { 291 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 292 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 293 #if 0 294 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 295 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 296 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 297 #endif 298 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, 0 }, 299 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, 0 }, 300 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, 0 }, 301 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, 0 }, 302 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, 0 }, 303 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, 0 }, 304 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, 0 }, 305 306 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 307 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 308 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 14 }, FLAGS_FIX_TQTB }, 309 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 310 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB }, 311 312 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 313 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 314 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 315 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 316 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB }, 317 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB }, 318 }; 319 320 321 /* ARGSUSED */ 322 static int 323 mvgbec_match(device_t parent, struct cfdata *match, void *aux) 324 { 325 struct marvell_attach_args *mva = aux; 326 int i; 327 328 if (strcmp(mva->mva_name, match->cf_name) != 0) 329 return 0; 330 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 331 return 0; 332 333 for (i = 0; i < __arraycount(mvgbe_ports); i++) 334 if (mva->mva_model == mvgbe_ports[i].model) { 335 mva->mva_size = MVGBE_SIZE; 336 return 1; 337 } 338 return 0; 339 } 340 341 /* ARGSUSED */ 342 static void 343 mvgbec_attach(device_t parent, device_t self, void *aux) 344 { 345 struct mvgbec_softc *sc = device_private(self); 346 struct marvell_attach_args *mva = aux, gbea; 347 struct mvgbe_softc *port; 348 struct mii_softc *mii; 349 device_t child; 350 uint32_t phyaddr; 351 int i, j; 352 353 aprint_naive("\n"); 354 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 355 356 sc->sc_dev = self; 357 sc->sc_iot = mva->mva_iot; 358 sc->sc_unit = mva->mva_unit; 359 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 360 mva->mva_size, &sc->sc_ioh)) { 361 aprint_error_dev(self, "Cannot map registers\n"); 362 return; 363 } 364 365 if (sc->sc_unit == 0) { 366 mvgbec0 = self; 367 } 368 369 phyaddr = 0; 370 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 371 372 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 373 374 /* Disable and clear Gigabit Ethernet Unit interrupts */ 375 MVGBE_WRITE(sc, MVGBE_EUIM, 0); 376 MVGBE_WRITE(sc, MVGBE_EUIC, 0); 377 378 mvgbec_wininit(sc); 379 380 memset(&gbea, 0, sizeof(gbea)); 381 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 382 if (mvgbe_ports[i].model != mva->mva_model || 383 mvgbe_ports[i].unit != mva->mva_unit) 384 continue; 385 386 sc->sc_fix_tqtb = mvgbe_ports[i].flags & FLAGS_FIX_TQTB; 387 388 for (j = 0; j < mvgbe_ports[i].ports; j++) { 389 gbea.mva_name = "mvgbe"; 390 gbea.mva_model = mva->mva_model; 391 gbea.mva_iot = sc->sc_iot; 392 gbea.mva_ioh = sc->sc_ioh; 393 gbea.mva_unit = j; 394 gbea.mva_dmat = mva->mva_dmat; 395 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 396 child = config_found_sm_loc(sc->sc_dev, "mvgbec", NULL, 397 &gbea, mvgbec_print, mvgbec_search); 398 if (child) { 399 port = device_private(child); 400 mii = LIST_FIRST(&port->sc_mii.mii_phys); 401 phyaddr |= MVGBE_PHYADDR_PHYAD(j, mii->mii_phy); 402 } 403 } 404 break; 405 } 406 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 407 } 408 409 static int 410 mvgbec_print(void *aux, const char *pnp) 411 { 412 struct marvell_attach_args *gbea = aux; 413 414 if (pnp) 415 aprint_normal("%s at %s port %d", 416 gbea->mva_name, pnp, gbea->mva_unit); 417 else { 418 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 419 aprint_normal(" port %d", gbea->mva_unit); 420 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 421 aprint_normal(" irq %d", gbea->mva_irq); 422 } 423 return UNCONF; 424 } 425 426 /* ARGSUSED */ 427 static int 428 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 429 { 430 struct marvell_attach_args *gbea = aux; 431 432 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 433 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 434 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 435 436 return config_match(parent, cf, aux); 437 } 438 439 static int 440 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 441 { 442 struct mvgbe_softc *sc = device_private(dev); 443 struct mvgbec_softc *csc; 444 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 445 uint32_t smi, val; 446 int i; 447 448 if (mvgbec0 == NULL) { 449 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 450 return -1; 451 } 452 csc = device_private(mvgbec0); 453 454 mutex_enter(&csc->sc_mtx); 455 456 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 457 DELAY(1); 458 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 459 break; 460 } 461 if (i == MVGBE_PHY_TIMEOUT) { 462 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 463 mutex_exit(&csc->sc_mtx); 464 return -1; 465 } 466 467 smi = 468 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 469 MVGBE_WRITE(csc, MVGBE_SMI, smi); 470 471 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 472 DELAY(1); 473 smi = MVGBE_READ(csc, MVGBE_SMI); 474 if (smi & MVGBE_SMI_READVALID) 475 break; 476 } 477 478 mutex_exit(&csc->sc_mtx); 479 480 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 481 i, MVGBE_PHY_TIMEOUT)); 482 483 val = smi & MVGBE_SMI_DATA_MASK; 484 485 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 486 phy, reg, val)); 487 488 return val; 489 } 490 491 static void 492 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 493 { 494 struct mvgbe_softc *sc = device_private(dev); 495 struct mvgbec_softc *csc; 496 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 497 uint32_t smi; 498 int i; 499 500 if (mvgbec0 == NULL) { 501 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 502 return; 503 } 504 csc = device_private(mvgbec0); 505 506 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 507 phy, reg, val)); 508 509 mutex_enter(&csc->sc_mtx); 510 511 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 512 DELAY(1); 513 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 514 break; 515 } 516 if (i == MVGBE_PHY_TIMEOUT) { 517 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 518 mutex_exit(&csc->sc_mtx); 519 return; 520 } 521 522 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 523 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 524 MVGBE_WRITE(csc, MVGBE_SMI, smi); 525 526 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 527 DELAY(1); 528 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 529 break; 530 } 531 532 mutex_exit(&csc->sc_mtx); 533 534 if (i == MVGBE_PHY_TIMEOUT) 535 aprint_error_ifnet(ifp, "phy write timed out\n"); 536 } 537 538 static void 539 mvgbec_miibus_statchg(device_t dev) 540 { 541 542 /* nothing to do */ 543 } 544 545 546 static void 547 mvgbec_wininit(struct mvgbec_softc *sc) 548 { 549 device_t pdev = device_parent(sc->sc_dev); 550 uint64_t base; 551 uint32_t en, ac, size; 552 int window, target, attr, rv, i; 553 static int tags[] = { 554 MARVELL_TAG_SDRAM_CS0, 555 MARVELL_TAG_SDRAM_CS1, 556 MARVELL_TAG_SDRAM_CS2, 557 MARVELL_TAG_SDRAM_CS3, 558 559 MARVELL_TAG_UNDEFINED, 560 }; 561 562 /* First disable all address decode windows */ 563 en = MVGBE_BARE_EN_MASK; 564 MVGBE_WRITE(sc, MVGBE_BARE, en); 565 566 ac = 0; 567 for (window = 0, i = 0; 568 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 569 rv = marvell_winparams_by_tag(pdev, tags[i], 570 &target, &attr, &base, &size); 571 if (rv != 0 || size == 0) 572 continue; 573 574 if (base > 0xffffffffULL) { 575 if (window >= MVGBE_NREMAP) { 576 aprint_error_dev(sc->sc_dev, 577 "can't remap window %d\n", window); 578 continue; 579 } 580 MVGBE_WRITE(sc, MVGBE_HA(window), 581 (base >> 32) & 0xffffffff); 582 } 583 584 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 585 MVGBE_BASEADDR_TARGET(target) | 586 MVGBE_BASEADDR_ATTR(attr) | 587 MVGBE_BASEADDR_BASE(base)); 588 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 589 590 en &= ~(1 << window); 591 /* set full access (r/w) */ 592 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 593 window++; 594 } 595 /* allow to access decode window */ 596 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 597 598 MVGBE_WRITE(sc, MVGBE_BARE, en); 599 } 600 601 602 /* ARGSUSED */ 603 static int 604 mvgbe_match(device_t parent, struct cfdata *match, void *aux) 605 { 606 struct marvell_attach_args *mva = aux; 607 uint32_t pbase, maddrh, maddrl; 608 609 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 610 maddrh = 611 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 612 maddrl = 613 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 614 if ((maddrh | maddrl) == 0) 615 return 0; 616 617 return 1; 618 } 619 620 /* ARGSUSED */ 621 static void 622 mvgbe_attach(device_t parent, device_t self, void *aux) 623 { 624 struct mvgbe_softc *sc = device_private(self); 625 struct mvgbec_softc *csc = device_private(parent); 626 struct marvell_attach_args *mva = aux; 627 struct mvgbe_txmap_entry *entry; 628 struct ifnet *ifp; 629 bus_dma_segment_t seg; 630 bus_dmamap_t dmamap; 631 int rseg, i; 632 uint32_t maddrh, maddrl; 633 void *kva; 634 635 aprint_naive("\n"); 636 aprint_normal("\n"); 637 638 sc->sc_dev = self; 639 sc->sc_port = mva->mva_unit; 640 sc->sc_iot = mva->mva_iot; 641 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 642 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 643 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 644 aprint_error_dev(self, "Cannot map registers\n"); 645 return; 646 } 647 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 648 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 649 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 650 aprint_error_dev(self, 651 "Cannot map destination address filter registers\n"); 652 return; 653 } 654 sc->sc_dmat = mva->mva_dmat; 655 656 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 657 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 658 sc->sc_enaddr[0] = maddrh >> 24; 659 sc->sc_enaddr[1] = maddrh >> 16; 660 sc->sc_enaddr[2] = maddrh >> 8; 661 sc->sc_enaddr[3] = maddrh >> 0; 662 sc->sc_enaddr[4] = maddrl >> 8; 663 sc->sc_enaddr[5] = maddrl >> 0; 664 aprint_normal_dev(self, "Ethernet address %s\n", 665 ether_sprintf(sc->sc_enaddr)); 666 667 /* clear all ethernet port interrupts */ 668 MVGBE_WRITE(sc, MVGBE_IC, 0); 669 MVGBE_WRITE(sc, MVGBE_ICE, 0); 670 671 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 672 673 /* Allocate the descriptor queues. */ 674 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 675 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 676 aprint_error_dev(self, "can't alloc rx buffers\n"); 677 return; 678 } 679 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 680 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 681 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 682 (u_long)sizeof(struct mvgbe_ring_data)); 683 goto fail1; 684 } 685 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 686 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 687 &sc->sc_ring_map)) { 688 aprint_error_dev(self, "can't create dma map\n"); 689 goto fail2; 690 } 691 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 692 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 693 aprint_error_dev(self, "can't load dma map\n"); 694 goto fail3; 695 } 696 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 697 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 698 699 SIMPLEQ_INIT(&sc->sc_txmap_head); 700 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 701 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 702 703 if (bus_dmamap_create(sc->sc_dmat, 704 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 705 BUS_DMA_NOWAIT, &dmamap)) { 706 aprint_error_dev(self, "Can't create TX dmamap\n"); 707 goto fail4; 708 } 709 710 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 711 if (!entry) { 712 aprint_error_dev(self, "Can't alloc txmap entry\n"); 713 bus_dmamap_destroy(sc->sc_dmat, dmamap); 714 goto fail4; 715 } 716 entry->dmamap = dmamap; 717 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 718 } 719 720 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 721 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 722 723 /* 724 * We can support 802.1Q VLAN-sized frames and jumbo 725 * Ethernet frames. 726 */ 727 sc->sc_ethercom.ec_capabilities |= 728 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 729 730 /* Try to allocate memory for jumbo buffers. */ 731 if (mvgbe_alloc_jumbo_mem(sc)) { 732 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 733 goto fail4; 734 } 735 736 ifp = &sc->sc_ethercom.ec_if; 737 ifp->if_softc = sc; 738 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 739 ifp->if_start = mvgbe_start; 740 ifp->if_ioctl = mvgbe_ioctl; 741 ifp->if_init = mvgbe_init; 742 ifp->if_stop = mvgbe_stop; 743 ifp->if_watchdog = mvgbe_watchdog; 744 /* 745 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 746 */ 747 sc->sc_ethercom.ec_if.if_capabilities |= 748 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 749 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 750 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 751 /* 752 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 753 */ 754 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 755 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 756 IFQ_SET_READY(&ifp->if_snd); 757 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 758 759 mvgbe_stop(ifp, 0); 760 761 /* 762 * Do MII setup. 763 */ 764 sc->sc_mii.mii_ifp = ifp; 765 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 766 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 767 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 768 769 sc->sc_ethercom.ec_mii = &sc->sc_mii; 770 ifmedia_init(&sc->sc_mii.mii_media, 0, 771 mvgbe_mediachange, mvgbe_mediastatus); 772 mii_attach(self, &sc->sc_mii, 0xffffffff, 773 csc->sc_unit, MII_OFFSET_ANY, 0); 774 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 775 aprint_error_dev(self, "no PHY found!\n"); 776 ifmedia_add(&sc->sc_mii.mii_media, 777 IFM_ETHER|IFM_MANUAL, 0, NULL); 778 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 779 } else 780 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 781 782 /* 783 * Call MI attach routines. 784 */ 785 if_attach(ifp); 786 787 ether_ifattach(ifp, sc->sc_enaddr); 788 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 789 790 #if NRND > 0 791 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 792 RND_TYPE_NET, 0); 793 #endif 794 795 return; 796 797 fail4: 798 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 799 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 800 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 801 } 802 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 803 fail3: 804 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 805 fail2: 806 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 807 fail1: 808 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 809 return; 810 } 811 812 813 static int 814 mvgbe_intr(void *arg) 815 { 816 struct mvgbe_softc *sc = arg; 817 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 818 uint32_t ic, ice, datum = 0; 819 int claimed = 0; 820 821 for (;;) { 822 ice = MVGBE_READ(sc, MVGBE_ICE); 823 ic = MVGBE_READ(sc, MVGBE_IC); 824 825 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 826 if (ic == 0 && ice == 0) 827 break; 828 829 datum = datum ^ ic ^ ice; 830 831 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 832 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 833 834 claimed = 1; 835 836 if (ice & MVGBE_ICE_LINKCHG) { 837 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 838 /* Enable port RX and TX. */ 839 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 840 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 841 } else { 842 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 843 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 844 } 845 } 846 847 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 848 mvgbe_rxeof(sc); 849 850 if (ice & (MVGBE_ICE_TXBUF | MVGBE_ICE_TXERR)) 851 mvgbe_txeof(sc); 852 } 853 854 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 855 mvgbe_start(ifp); 856 857 #if NRND > 0 858 if (RND_ENABLED(&sc->sc_rnd_source)) 859 rnd_add_uint32(&sc->sc_rnd_source, datum); 860 #endif 861 862 return claimed; 863 } 864 865 static void 866 mvgbe_start(struct ifnet *ifp) 867 { 868 struct mvgbe_softc *sc = ifp->if_softc; 869 struct mbuf *m_head = NULL; 870 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 871 int pkts = 0; 872 873 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 874 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 875 876 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 877 return; 878 /* If Link is DOWN, can't start TX */ 879 if (!(MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP)) 880 return; 881 882 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 883 IFQ_POLL(&ifp->if_snd, m_head); 884 if (m_head == NULL) 885 break; 886 887 /* 888 * Pack the data into the transmit ring. If we 889 * don't have room, set the OACTIVE flag and wait 890 * for the NIC to drain the ring. 891 */ 892 if (mvgbe_encap(sc, m_head, &idx)) { 893 ifp->if_flags |= IFF_OACTIVE; 894 break; 895 } 896 897 /* now we are committed to transmit the packet */ 898 IFQ_DEQUEUE(&ifp->if_snd, m_head); 899 pkts++; 900 901 /* 902 * If there's a BPF listener, bounce a copy of this frame 903 * to him. 904 */ 905 if (ifp->if_bpf) 906 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 907 } 908 if (pkts == 0) 909 return; 910 911 /* Transmit at Queue 0 */ 912 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 913 sc->sc_cdata.mvgbe_tx_prod = idx; 914 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 915 916 /* 917 * Set a timeout in case the chip goes out to lunch. 918 */ 919 ifp->if_timer = 5; 920 } 921 } 922 923 static int 924 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 925 { 926 struct mvgbe_softc *sc = ifp->if_softc; 927 struct ifreq *ifr = data; 928 int s, error = 0; 929 930 s = splnet(); 931 932 switch (cmd) { 933 case SIOCGIFMEDIA: 934 case SIOCSIFMEDIA: 935 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 936 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 937 break; 938 default: 939 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 940 error = ether_ioctl(ifp, cmd, data); 941 if (error == ENETRESET) { 942 if (ifp->if_flags & IFF_RUNNING) { 943 mvgbe_filter_setup(sc); 944 } 945 error = 0; 946 } 947 break; 948 } 949 950 splx(s); 951 952 return error; 953 } 954 955 int mvgbe_rximt = 0; 956 int mvgbe_tximt = 0; 957 958 static int 959 mvgbe_init(struct ifnet *ifp) 960 { 961 struct mvgbe_softc *sc = ifp->if_softc; 962 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 963 struct mii_data *mii = &sc->sc_mii; 964 uint32_t reg; 965 int i; 966 967 DPRINTFN(2, ("mvgbe_init\n")); 968 969 /* Cancel pending I/O and free all RX/TX buffers. */ 970 mvgbe_stop(ifp, 0); 971 972 /* clear all ethernet port interrupts */ 973 MVGBE_WRITE(sc, MVGBE_IC, 0); 974 MVGBE_WRITE(sc, MVGBE_ICE, 0); 975 976 /* Init TX/RX descriptors */ 977 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 978 aprint_error_ifnet(ifp, 979 "initialization failed: no memory for tx buffers\n"); 980 return ENOBUFS; 981 } 982 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 983 aprint_error_ifnet(ifp, 984 "initialization failed: no memory for rx buffers\n"); 985 return ENOBUFS; 986 } 987 988 MVGBE_WRITE(sc, MVGBE_PSC, 989 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 990 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 991 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 992 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 993 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 994 /* XXXX: mvgbe(4) always use RGMII. */ 995 MVGBE_WRITE(sc, MVGBE_PSC1, 996 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 997 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 998 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 999 1000 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 1001 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 1002 1003 if (csc->sc_fix_tqtb) { 1004 /* 1005 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1006 * And offset 0x72704 must be programmed to 0x03ffffff. 1007 * Queue 1 through 7 must be programmed to 0x0. 1008 */ 1009 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1010 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1011 for (i = 1; i < 8; i++) { 1012 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1013 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1014 } 1015 } else 1016 for (i = 1; i < 8; i++) { 1017 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1018 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1019 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1020 } 1021 1022 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1023 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1024 MVGBE_WRITE(sc, MVGBE_SDC, 1025 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1026 #if BYTE_ORDER == LITTLE_ENDIAN 1027 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1028 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1029 #endif 1030 MVGBE_SDC_IPGINTRX(mvgbe_rximt) | 1031 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1032 MVGBE_WRITE(sc, MVGBE_PTFUT, MVGBE_PTFUT_IPGINTTX(mvgbe_tximt)); 1033 1034 mvgbe_filter_setup(sc); 1035 1036 mii_mediachg(mii); 1037 1038 /* Enable port */ 1039 reg = MVGBE_READ(sc, MVGBE_PSC); 1040 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1041 1042 /* If Link is UP, Start RX and TX traffic */ 1043 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 1044 /* Enable port RX/TX. */ 1045 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1046 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 1047 } 1048 1049 /* Enable interrupt masks */ 1050 MVGBE_WRITE(sc, MVGBE_PIM, 1051 MVGBE_IC_RXBUF | 1052 MVGBE_IC_EXTEND | 1053 MVGBE_IC_RXBUFQ_MASK | 1054 MVGBE_IC_RXERROR | 1055 MVGBE_IC_RXERRQ_MASK); 1056 MVGBE_WRITE(sc, MVGBE_PEIM, 1057 MVGBE_ICE_TXBUF | 1058 MVGBE_ICE_TXERR | 1059 MVGBE_ICE_LINKCHG); 1060 1061 ifp->if_flags |= IFF_RUNNING; 1062 ifp->if_flags &= ~IFF_OACTIVE; 1063 1064 return 0; 1065 } 1066 1067 /* ARGSUSED */ 1068 static void 1069 mvgbe_stop(struct ifnet *ifp, int disable) 1070 { 1071 struct mvgbe_softc *sc = ifp->if_softc; 1072 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1073 uint32_t reg; 1074 int i, cnt; 1075 1076 DPRINTFN(2, ("mvgbe_stop\n")); 1077 1078 /* Stop Rx port activity. Check port Rx activity. */ 1079 reg = MVGBE_READ(sc, MVGBE_RQC); 1080 if (reg & MVGBE_RQC_ENQ_MASK) 1081 /* Issue stop command for active channels only */ 1082 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1083 1084 /* Stop Tx port activity. Check port Tx activity. */ 1085 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ) 1086 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 1087 1088 /* Force link down */ 1089 reg = MVGBE_READ(sc, MVGBE_PSC); 1090 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1091 1092 #define RX_DISABLE_TIMEOUT 0x1000000 1093 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1094 /* Wait for all Rx activity to terminate. */ 1095 cnt = 0; 1096 do { 1097 if (cnt >= RX_DISABLE_TIMEOUT) { 1098 aprint_error_ifnet(ifp, 1099 "timeout for RX stopped. rqc 0x%x\n", reg); 1100 break; 1101 } 1102 cnt++; 1103 1104 /* 1105 * Check Receive Queue Command register that all Rx queues 1106 * are stopped 1107 */ 1108 reg = MVGBE_READ(sc, MVGBE_RQC); 1109 } while (reg & 0xff); 1110 1111 /* Double check to verify that TX FIFO is empty */ 1112 cnt = 0; 1113 while (1) { 1114 do { 1115 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1116 aprint_error_ifnet(ifp, 1117 "timeout for TX FIFO empty. status 0x%x\n", 1118 reg); 1119 break; 1120 } 1121 cnt++; 1122 1123 reg = MVGBE_READ(sc, MVGBE_PS); 1124 } while 1125 (!(reg & MVGBE_PS_TXFIFOEMP) || reg & MVGBE_PS_TXINPROG); 1126 1127 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1128 break; 1129 1130 /* Double check */ 1131 reg = MVGBE_READ(sc, MVGBE_PS); 1132 if (reg & MVGBE_PS_TXFIFOEMP && !(reg & MVGBE_PS_TXINPROG)) 1133 break; 1134 else 1135 aprint_error_ifnet(ifp, 1136 "TX FIFO empty double check failed." 1137 " %d loops, status 0x%x\n", cnt, reg); 1138 } 1139 1140 /* Reset the Enable bit in the Port Serial Control Register */ 1141 reg = MVGBE_READ(sc, MVGBE_PSC); 1142 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1143 1144 /* Disable interrupts */ 1145 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1146 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1147 1148 /* Free RX and TX mbufs still in the queues. */ 1149 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1150 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1151 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1152 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1153 } 1154 } 1155 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1156 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1157 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1158 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1159 } 1160 } 1161 1162 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1163 } 1164 1165 static void 1166 mvgbe_watchdog(struct ifnet *ifp) 1167 { 1168 struct mvgbe_softc *sc = ifp->if_softc; 1169 1170 /* 1171 * Reclaim first as there is a possibility of losing Tx completion 1172 * interrupts. 1173 */ 1174 mvgbe_txeof(sc); 1175 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1176 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1177 1178 ifp->if_oerrors++; 1179 1180 mvgbe_init(ifp); 1181 } 1182 } 1183 1184 static int 1185 mvgbe_ifflags_cb(struct ethercom *ec) 1186 { 1187 struct ifnet *ifp = &ec->ec_if; 1188 struct mvgbe_softc *sc = ifp->if_softc; 1189 int change = ifp->if_flags ^ sc->sc_if_flags; 1190 1191 if (change != 0) 1192 sc->sc_if_flags = ifp->if_flags; 1193 1194 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1195 return ENETRESET; 1196 1197 if ((change & IFF_PROMISC) != 0) 1198 mvgbe_filter_setup(sc); 1199 1200 return 0; 1201 } 1202 1203 /* 1204 * Set media options. 1205 */ 1206 static int 1207 mvgbe_mediachange(struct ifnet *ifp) 1208 { 1209 return ether_mediachange(ifp); 1210 } 1211 1212 /* 1213 * Report current media status. 1214 */ 1215 static void 1216 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1217 { 1218 ether_mediastatus(ifp, ifmr); 1219 } 1220 1221 1222 static int 1223 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1224 { 1225 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1226 struct mvgbe_ring_data *rd = sc->sc_rdata; 1227 int i; 1228 1229 memset(rd->mvgbe_rx_ring, 0, 1230 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1231 1232 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1233 cd->mvgbe_rx_chain[i].mvgbe_desc = 1234 &rd->mvgbe_rx_ring[i]; 1235 if (i == MVGBE_RX_RING_CNT - 1) { 1236 cd->mvgbe_rx_chain[i].mvgbe_next = 1237 &cd->mvgbe_rx_chain[0]; 1238 rd->mvgbe_rx_ring[i].nextdescptr = 1239 MVGBE_RX_RING_ADDR(sc, 0); 1240 } else { 1241 cd->mvgbe_rx_chain[i].mvgbe_next = 1242 &cd->mvgbe_rx_chain[i + 1]; 1243 rd->mvgbe_rx_ring[i].nextdescptr = 1244 MVGBE_RX_RING_ADDR(sc, i + 1); 1245 } 1246 } 1247 1248 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1249 if (mvgbe_newbuf(sc, i, NULL, 1250 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1251 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1252 "failed alloc of %dth mbuf\n", i); 1253 return ENOBUFS; 1254 } 1255 } 1256 sc->sc_cdata.mvgbe_rx_prod = 0; 1257 sc->sc_cdata.mvgbe_rx_cons = 0; 1258 1259 return 0; 1260 } 1261 1262 static int 1263 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1264 { 1265 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1266 struct mvgbe_ring_data *rd = sc->sc_rdata; 1267 int i; 1268 1269 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1270 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1271 1272 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1273 cd->mvgbe_tx_chain[i].mvgbe_desc = 1274 &rd->mvgbe_tx_ring[i]; 1275 if (i == MVGBE_TX_RING_CNT - 1) { 1276 cd->mvgbe_tx_chain[i].mvgbe_next = 1277 &cd->mvgbe_tx_chain[0]; 1278 rd->mvgbe_tx_ring[i].nextdescptr = 1279 MVGBE_TX_RING_ADDR(sc, 0); 1280 } else { 1281 cd->mvgbe_tx_chain[i].mvgbe_next = 1282 &cd->mvgbe_tx_chain[i + 1]; 1283 rd->mvgbe_tx_ring[i].nextdescptr = 1284 MVGBE_TX_RING_ADDR(sc, i + 1); 1285 } 1286 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1287 } 1288 1289 sc->sc_cdata.mvgbe_tx_prod = 0; 1290 sc->sc_cdata.mvgbe_tx_cons = 0; 1291 sc->sc_cdata.mvgbe_tx_cnt = 0; 1292 1293 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1294 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1295 1296 return 0; 1297 } 1298 1299 static int 1300 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1301 bus_dmamap_t dmamap) 1302 { 1303 struct mbuf *m_new = NULL; 1304 struct mvgbe_chain *c; 1305 struct mvgbe_rx_desc *r; 1306 int align; 1307 1308 if (m == NULL) { 1309 void *buf = NULL; 1310 1311 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1312 if (m_new == NULL) { 1313 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1314 "no memory for rx list -- packet dropped!\n"); 1315 return ENOBUFS; 1316 } 1317 1318 /* Allocate the jumbo buffer */ 1319 buf = mvgbe_jalloc(sc); 1320 if (buf == NULL) { 1321 m_freem(m_new); 1322 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1323 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1324 return ENOBUFS; 1325 } 1326 1327 /* Attach the buffer to the mbuf */ 1328 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1329 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1330 } else { 1331 /* 1332 * We're re-using a previously allocated mbuf; 1333 * be sure to re-init pointers and lengths to 1334 * default values. 1335 */ 1336 m_new = m; 1337 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1338 m_new->m_data = m_new->m_ext.ext_buf; 1339 } 1340 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1341 if (align != 0) { 1342 DPRINTFN(1,("align = %d\n", align)); 1343 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1344 } 1345 1346 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1347 r = c->mvgbe_desc; 1348 c->mvgbe_mbuf = m_new; 1349 r->bufptr = dmamap->dm_segs[0].ds_addr + 1350 (((vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf)); 1351 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1352 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1353 1354 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1355 1356 return 0; 1357 } 1358 1359 /* 1360 * Memory management for jumbo frames. 1361 */ 1362 1363 static int 1364 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1365 { 1366 char *ptr, *kva; 1367 bus_dma_segment_t seg; 1368 int i, rseg, state, error; 1369 struct mvgbe_jpool_entry *entry; 1370 1371 state = error = 0; 1372 1373 /* Grab a big chunk o' storage. */ 1374 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1375 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1376 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1377 return ENOBUFS; 1378 } 1379 1380 state = 1; 1381 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1382 (void **)&kva, BUS_DMA_NOWAIT)) { 1383 aprint_error_dev(sc->sc_dev, 1384 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1385 error = ENOBUFS; 1386 goto out; 1387 } 1388 1389 state = 2; 1390 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1391 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1392 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1393 error = ENOBUFS; 1394 goto out; 1395 } 1396 1397 state = 3; 1398 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1399 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1400 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1401 error = ENOBUFS; 1402 goto out; 1403 } 1404 1405 state = 4; 1406 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1407 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1408 1409 LIST_INIT(&sc->sc_jfree_listhead); 1410 LIST_INIT(&sc->sc_jinuse_listhead); 1411 1412 /* 1413 * Now divide it up into 9K pieces and save the addresses 1414 * in an array. 1415 */ 1416 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1417 for (i = 0; i < MVGBE_JSLOTS; i++) { 1418 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1419 ptr += MVGBE_JLEN; 1420 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1421 if (entry == NULL) { 1422 aprint_error_dev(sc->sc_dev, 1423 "no memory for jumbo buffer queue!\n"); 1424 error = ENOBUFS; 1425 goto out; 1426 } 1427 entry->slot = i; 1428 if (i) 1429 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1430 jpool_entries); 1431 else 1432 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1433 jpool_entries); 1434 } 1435 out: 1436 if (error != 0) { 1437 switch (state) { 1438 case 4: 1439 bus_dmamap_unload(sc->sc_dmat, 1440 sc->sc_cdata.mvgbe_rx_jumbo_map); 1441 case 3: 1442 bus_dmamap_destroy(sc->sc_dmat, 1443 sc->sc_cdata.mvgbe_rx_jumbo_map); 1444 case 2: 1445 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1446 case 1: 1447 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1448 break; 1449 default: 1450 break; 1451 } 1452 } 1453 1454 return error; 1455 } 1456 1457 /* 1458 * Allocate a jumbo buffer. 1459 */ 1460 static void * 1461 mvgbe_jalloc(struct mvgbe_softc *sc) 1462 { 1463 struct mvgbe_jpool_entry *entry; 1464 1465 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1466 1467 if (entry == NULL) 1468 return NULL; 1469 1470 LIST_REMOVE(entry, jpool_entries); 1471 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1472 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1473 } 1474 1475 /* 1476 * Release a jumbo buffer. 1477 */ 1478 static void 1479 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1480 { 1481 struct mvgbe_jpool_entry *entry; 1482 struct mvgbe_softc *sc; 1483 int i, s; 1484 1485 /* Extract the softc struct pointer. */ 1486 sc = (struct mvgbe_softc *)arg; 1487 1488 if (sc == NULL) 1489 panic("%s: can't find softc pointer!", __func__); 1490 1491 /* calculate the slot this buffer belongs to */ 1492 1493 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1494 1495 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1496 panic("%s: asked to free buffer that we don't manage!", 1497 __func__); 1498 1499 s = splvm(); 1500 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1501 if (entry == NULL) 1502 panic("%s: buffer not in use!", __func__); 1503 entry->slot = i; 1504 LIST_REMOVE(entry, jpool_entries); 1505 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1506 1507 if (__predict_true(m != NULL)) 1508 pool_cache_put(mb_cache, m); 1509 splx(s); 1510 } 1511 1512 static int 1513 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1514 uint32_t *txidx) 1515 { 1516 struct mvgbe_tx_desc *f = NULL; 1517 struct mvgbe_txmap_entry *entry; 1518 bus_dma_segment_t *txseg; 1519 bus_dmamap_t txmap; 1520 uint32_t first, current, last, cmdsts = 0; 1521 int m_csumflags, i; 1522 1523 DPRINTFN(3, ("mvgbe_encap\n")); 1524 1525 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1526 if (entry == NULL) { 1527 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1528 return ENOBUFS; 1529 } 1530 txmap = entry->dmamap; 1531 1532 first = current = last = *txidx; 1533 1534 /* 1535 * Preserve m_pkthdr.csum_flags here since m_head might be 1536 * updated by m_defrag() 1537 */ 1538 m_csumflags = m_head->m_pkthdr.csum_flags; 1539 1540 /* 1541 * Start packing the mbufs in this chain into 1542 * the fragment pointers. Stop when we run out 1543 * of fragments or hit the end of the mbuf chain. 1544 */ 1545 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1546 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1547 return ENOBUFS; 1548 } 1549 1550 /* Sync the DMA map. */ 1551 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1552 BUS_DMASYNC_PREWRITE); 1553 1554 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1555 MVGBE_TX_RING_CNT) { 1556 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1557 bus_dmamap_unload(sc->sc_dmat, txmap); 1558 return ENOBUFS; 1559 } 1560 1561 txseg = txmap->dm_segs; 1562 1563 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1564 1565 for (i = 0; i < txmap->dm_nsegs; i++) { 1566 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1567 f->bufptr = txseg[i].ds_addr; 1568 f->bytecnt = txseg[i].ds_len; 1569 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1570 last = current; 1571 current = MVGBE_TX_RING_NEXT(current); 1572 } 1573 1574 if (m_csumflags & M_CSUM_IPv4) 1575 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1576 if (m_csumflags & M_CSUM_TCPv4) 1577 cmdsts |= 1578 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1579 if (m_csumflags & M_CSUM_UDPv4) 1580 cmdsts |= 1581 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1582 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1583 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1584 1585 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1586 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1587 } 1588 if (txmap->dm_nsegs == 1) 1589 f->cmdsts = cmdsts | 1590 MVGBE_BUFFER_OWNED_BY_DMA | 1591 MVGBE_TX_GENERATE_CRC | 1592 MVGBE_TX_ENABLE_INTERRUPT | 1593 MVGBE_TX_ZERO_PADDING | 1594 MVGBE_TX_FIRST_DESC | 1595 MVGBE_TX_LAST_DESC; 1596 else { 1597 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1598 f->cmdsts = cmdsts | 1599 MVGBE_BUFFER_OWNED_BY_DMA | 1600 MVGBE_TX_GENERATE_CRC | 1601 MVGBE_TX_FIRST_DESC; 1602 1603 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1604 f->cmdsts = 1605 MVGBE_BUFFER_OWNED_BY_DMA | 1606 MVGBE_TX_ENABLE_INTERRUPT | 1607 MVGBE_TX_ZERO_PADDING | 1608 MVGBE_TX_LAST_DESC; 1609 } 1610 1611 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1612 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1613 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1614 1615 /* Sync descriptors before handing to chip */ 1616 MVGBE_CDTXSYNC(sc, *txidx, txmap->dm_nsegs, 1617 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1618 1619 sc->sc_cdata.mvgbe_tx_cnt += i; 1620 *txidx = current; 1621 1622 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1623 1624 return 0; 1625 } 1626 1627 static void 1628 mvgbe_rxeof(struct mvgbe_softc *sc) 1629 { 1630 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1631 struct mvgbe_rx_desc *cur_rx; 1632 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1633 struct mbuf *m; 1634 bus_dmamap_t dmamap; 1635 uint32_t rxstat; 1636 int idx, cur, total_len; 1637 1638 idx = sc->sc_cdata.mvgbe_rx_prod; 1639 1640 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1641 1642 for (;;) { 1643 cur = idx; 1644 1645 /* Sync the descriptor */ 1646 MVGBE_CDRXSYNC(sc, idx, 1647 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1648 1649 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1650 1651 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1652 MVGBE_BUFFER_OWNED_BY_DMA) { 1653 /* Invalidate the descriptor -- it's not ready yet */ 1654 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1655 sc->sc_cdata.mvgbe_rx_prod = idx; 1656 break; 1657 } 1658 #ifdef DIAGNOSTIC 1659 if ((cur_rx->cmdsts & 1660 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1661 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1662 panic( 1663 "mvgbe_rxeof: buffer size is smaller than packet"); 1664 #endif 1665 1666 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1667 1668 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1669 BUS_DMASYNC_POSTREAD); 1670 1671 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1672 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1673 total_len = cur_rx->bytecnt; 1674 rxstat = cur_rx->cmdsts; 1675 1676 cdata->mvgbe_rx_map[idx] = NULL; 1677 1678 idx = MVGBE_RX_RING_NEXT(idx); 1679 1680 if (rxstat & MVGBE_ERROR_SUMMARY) { 1681 #if 0 1682 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1683 1684 if (err == MVGBE_RX_CRC_ERROR) 1685 ifp->if_ierrors++; 1686 if (err == MVGBE_RX_OVERRUN_ERROR) 1687 ifp->if_ierrors++; 1688 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1689 ifp->if_ierrors++; 1690 if (err == MVGBE_RX_RESOURCE_ERROR) 1691 ifp->if_ierrors++; 1692 #else 1693 ifp->if_ierrors++; 1694 #endif 1695 mvgbe_newbuf(sc, cur, m, dmamap); 1696 continue; 1697 } 1698 1699 if (total_len <= MVGBE_RX_CSUM_MIN_BYTE) /* XXX documented? */ 1700 goto sw_csum; 1701 1702 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1703 /* Check IPv4 header checksum */ 1704 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1705 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 1706 m->m_pkthdr.csum_flags |= 1707 M_CSUM_IPv4_BAD; 1708 /* Check TCPv4/UDPv4 checksum */ 1709 if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1710 MVGBE_RX_L4_TYPE_TCP) 1711 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1712 else if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1713 MVGBE_RX_L4_TYPE_UDP) 1714 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1715 if (!(rxstat & MVGBE_RX_L4_CHECKSUM)) 1716 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1717 } 1718 sw_csum: 1719 1720 /* 1721 * Try to allocate a new jumbo buffer. If that 1722 * fails, copy the packet to mbufs and put the 1723 * jumbo buffer back in the ring so it can be 1724 * re-used. If allocating mbufs fails, then we 1725 * have to drop the packet. 1726 */ 1727 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 1728 struct mbuf *m0; 1729 1730 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 1731 mvgbe_newbuf(sc, cur, m, dmamap); 1732 if (m0 == NULL) { 1733 aprint_error_ifnet(ifp, 1734 "no receive buffers available --" 1735 " packet dropped!\n"); 1736 ifp->if_ierrors++; 1737 continue; 1738 } 1739 m = m0; 1740 } else { 1741 m->m_pkthdr.rcvif = ifp; 1742 m->m_pkthdr.len = m->m_len = total_len; 1743 } 1744 1745 /* Skip on first 2byte (HW header) */ 1746 m_adj(m, MVGBE_HWHEADER_SIZE); 1747 m->m_flags |= M_HASFCS; 1748 1749 ifp->if_ipackets++; 1750 1751 if (ifp->if_bpf) 1752 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1753 1754 /* pass it on. */ 1755 (*ifp->if_input)(ifp, m); 1756 } 1757 } 1758 1759 static void 1760 mvgbe_txeof(struct mvgbe_softc *sc) 1761 { 1762 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1763 struct mvgbe_tx_desc *cur_tx; 1764 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1765 struct mvgbe_txmap_entry *entry; 1766 int idx; 1767 1768 DPRINTFN(3, ("mvgbe_txeof\n")); 1769 1770 /* 1771 * Go through our tx ring and free mbufs for those 1772 * frames that have been sent. 1773 */ 1774 idx = cdata->mvgbe_tx_cons; 1775 while (idx != cdata->mvgbe_tx_prod) { 1776 MVGBE_CDTXSYNC(sc, idx, 1, 1777 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1778 1779 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 1780 #ifdef MVGBE_DEBUG 1781 if (mvgbe_debug >= 3) 1782 mvgbe_dump_txdesc(cur_tx, idx); 1783 #endif 1784 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1785 MVGBE_BUFFER_OWNED_BY_DMA) { 1786 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 1787 break; 1788 } 1789 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 1790 ifp->if_opackets++; 1791 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 1792 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 1793 1794 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 1795 ifp->if_collisions++; 1796 if (err == MVGBE_TX_UNDERRUN_ERROR) 1797 ifp->if_oerrors++; 1798 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 1799 ifp->if_collisions++; 1800 } 1801 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 1802 entry = cdata->mvgbe_tx_map[idx]; 1803 1804 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 1805 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 1806 1807 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 1808 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1809 1810 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 1811 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 1812 cdata->mvgbe_tx_map[idx] = NULL; 1813 } 1814 cdata->mvgbe_tx_cnt--; 1815 idx = MVGBE_TX_RING_NEXT(idx); 1816 } 1817 if (cdata->mvgbe_tx_cnt == 0) 1818 ifp->if_timer = 0; 1819 1820 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 1821 ifp->if_flags &= ~IFF_OACTIVE; 1822 1823 cdata->mvgbe_tx_cons = idx; 1824 } 1825 1826 static uint8_t 1827 mvgbe_crc8(const uint8_t *data, size_t size) 1828 { 1829 int bit; 1830 uint8_t byte; 1831 uint8_t crc = 0; 1832 const uint8_t poly = 0x07; 1833 1834 while(size--) 1835 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 1836 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 1837 1838 return crc; 1839 } 1840 1841 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 1842 1843 static void 1844 mvgbe_filter_setup(struct mvgbe_softc *sc) 1845 { 1846 struct ethercom *ec = &sc->sc_ethercom; 1847 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 1848 struct ether_multi *enm; 1849 struct ether_multistep step; 1850 uint32_t *dfut, *dfsmt, *dfomt; 1851 uint32_t pxc; 1852 int i; 1853 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 1854 1855 dfut = kmem_zalloc(sizeof(*dfut) * MVGBE_NDFUT, KM_SLEEP); 1856 dfsmt = kmem_zalloc(sizeof(*dfsmt) * MVGBE_NDFSMT, KM_SLEEP); 1857 dfomt = kmem_zalloc(sizeof(*dfomt) * MVGBE_NDFOMT, KM_SLEEP); 1858 1859 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1860 goto allmulti; 1861 } 1862 1863 ETHER_FIRST_MULTI(step, ec, enm); 1864 while (enm != NULL) { 1865 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1866 /* ranges are complex and somewhat rare */ 1867 goto allmulti; 1868 } 1869 /* chip handles some IPv4 multicast specially */ 1870 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 1871 i = enm->enm_addrlo[5]; 1872 dfsmt[i>>2] = 1873 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1874 } else { 1875 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 1876 dfomt[i>>2] = 1877 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1878 } 1879 1880 ETHER_NEXT_MULTI(step, enm); 1881 } 1882 goto set; 1883 1884 allmulti: 1885 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1886 for (i = 0; i < MVGBE_NDFSMT; i++) { 1887 dfsmt[i] = dfomt[i] = 1888 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1889 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1890 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1891 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1892 } 1893 } 1894 1895 set: 1896 pxc = MVGBE_READ(sc, MVGBE_PXC); 1897 pxc &= ~MVGBE_PXC_UPM; 1898 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 1899 if (ifp->if_flags & IFF_BROADCAST) { 1900 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 1901 } 1902 if (ifp->if_flags & IFF_PROMISC) { 1903 pxc |= MVGBE_PXC_UPM; 1904 } 1905 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 1906 1907 /* Set Destination Address Filter Unicast Table */ 1908 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 1909 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1910 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 1911 1912 /* Set Destination Address Filter Multicast Tables */ 1913 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 1914 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 1915 1916 kmem_free(dfut, sizeof(dfut[0]) * MVGBE_NDFUT); 1917 kmem_free(dfsmt, sizeof(dfsmt[0]) * MVGBE_NDFSMT); 1918 kmem_free(dfomt, sizeof(dfsmt[0]) * MVGBE_NDFOMT); 1919 } 1920 1921 #ifdef MVGBE_DEBUG 1922 static void 1923 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 1924 { 1925 #define DESC_PRINT(X) \ 1926 if (X) \ 1927 printf("txdesc[%d]." #X "=%#x\n", idx, X); 1928 1929 #if BYTE_ORDER == BIG_ENDIAN 1930 DESC_PRINT(desc->bytecnt); 1931 DESC_PRINT(desc->l4ichk); 1932 DESC_PRINT(desc->cmdsts); 1933 DESC_PRINT(desc->nextdescptr); 1934 DESC_PRINT(desc->bufptr); 1935 #else /* LITTLE_ENDIAN */ 1936 DESC_PRINT(desc->cmdsts); 1937 DESC_PRINT(desc->l4ichk); 1938 DESC_PRINT(desc->bytecnt); 1939 DESC_PRINT(desc->bufptr); 1940 DESC_PRINT(desc->nextdescptr); 1941 #endif 1942 #undef DESC_PRINT 1943 } 1944 #endif 1945
Indexes created Wed Oct 01 13:09:50 GMT 2025