if_mvgbe.c revision 1.7
1 /* $NetBSD: if_mvgbe.c,v 1.7 2011/03/06 17:00:16 christos Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_mvgbe.c,v 1.7 2011/03/06 17:00:16 christos Exp $"); 29 30 #include "rnd.h" 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/endian.h> 36 #include <sys/errno.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 #include <sys/sockio.h> 40 41 #include <dev/marvell/marvellreg.h> 42 #include <dev/marvell/marvellvar.h> 43 #include <dev/marvell/mvgbereg.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/in_systm.h> 51 #include <netinet/ip.h> 52 53 #include <net/bpf.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include "locators.h" 62 63 /* #define MVGBE_DEBUG 3 */ 64 #ifdef MVGBE_DEBUG 65 #define DPRINTF(x) if (mvgbe_debug) printf x 66 #define DPRINTFN(n,x) if (mvgbe_debug >= (n)) printf x 67 int mvgbe_debug = MVGBE_DEBUG; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n,x) 71 #endif 72 73 74 #define MVGBE_READ(sc, reg) \ 75 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 76 #define MVGBE_WRITE(sc, reg, val) \ 77 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 78 #define MVGBE_READ_FILTER(sc, reg, val, c) \ 79 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 80 #define MVGBE_WRITE_FILTER(sc, reg, val, c) \ 81 bus_space_write_region_4((sc)->sc_iot, (sc)->sc_dafh, (reg), (val), (c)) 82 83 #define MVGBE_TX_RING_CNT 256 84 #define MVGBE_TX_RING_MSK (MVGBE_TX_RING_CNT - 1) 85 #define MVGBE_TX_RING_NEXT(x) (((x) + 1) & MVGBE_TX_RING_MSK) 86 #define MVGBE_RX_RING_CNT 256 87 #define MVGBE_RX_RING_MSK (MVGBE_RX_RING_CNT - 1) 88 #define MVGBE_RX_RING_NEXT(x) (((x) + 1) & MVGBE_RX_RING_MSK) 89 90 CTASSERT(MVGBE_TX_RING_CNT > 1 && MVGBE_TX_RING_NEXT(MVGBE_TX_RING_CNT) == 91 (MVGBE_TX_RING_CNT + 1) % MVGBE_TX_RING_CNT); 92 CTASSERT(MVGBE_RX_RING_CNT > 1 && MVGBE_RX_RING_NEXT(MVGBE_RX_RING_CNT) == 93 (MVGBE_RX_RING_CNT + 1) % MVGBE_RX_RING_CNT); 94 95 #define MVGBE_JSLOTS 384 /* XXXX */ 96 #define MVGBE_JLEN ((MVGBE_MRU + MVGBE_RXBUF_ALIGN)&~MVGBE_RXBUF_MASK) 97 #define MVGBE_NTXSEG 30 98 #define MVGBE_JPAGESZ PAGE_SIZE 99 #define MVGBE_RESID \ 100 (MVGBE_JPAGESZ - (MVGBE_JLEN * MVGBE_JSLOTS) % MVGBE_JPAGESZ) 101 #define MVGBE_JMEM \ 102 ((MVGBE_JLEN * MVGBE_JSLOTS) + MVGBE_RESID) 103 104 #define MVGBE_TX_RING_ADDR(sc, i) \ 105 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 106 offsetof(struct mvgbe_ring_data, mvgbe_tx_ring[(i)])) 107 108 #define MVGBE_RX_RING_ADDR(sc, i) \ 109 ((sc)->sc_ring_map->dm_segs[0].ds_addr + \ 110 offsetof(struct mvgbe_ring_data, mvgbe_rx_ring[(i)])) 111 112 #define MVGBE_CDOFF(x) offsetof(struct mvgbe_ring_data, x) 113 #define MVGBE_CDTXOFF(x) MVGBE_CDOFF(mvgbe_tx_ring[(x)]) 114 #define MVGBE_CDRXOFF(x) MVGBE_CDOFF(mvgbe_rx_ring[(x)]) 115 116 #define MVGBE_CDTXSYNC(sc, x, n, ops) \ 117 do { \ 118 int __x, __n; \ 119 const int __descsize = sizeof(struct mvgbe_tx_desc); \ 120 \ 121 __x = (x); \ 122 __n = (n); \ 123 \ 124 /* If it will wrap around, sync to the end of the ring. */ \ 125 if ((__x + __n) > MVGBE_TX_RING_CNT) { \ 126 bus_dmamap_sync((sc)->sc_dmat, \ 127 (sc)->sc_ring_map, MVGBE_CDTXOFF(__x), \ 128 __descsize * (MVGBE_TX_RING_CNT - __x), (ops)); \ 129 __n -= (MVGBE_TX_RING_CNT - __x); \ 130 __x = 0; \ 131 } \ 132 \ 133 /* Now sync whatever is left. */ \ 134 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 135 MVGBE_CDTXOFF((__x)), __descsize * __n, (ops)); \ 136 } while (0 /*CONSTCOND*/) 137 138 #define MVGBE_CDRXSYNC(sc, x, ops) \ 139 do { \ 140 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_ring_map, \ 141 MVGBE_CDRXOFF((x)), sizeof(struct mvgbe_rx_desc), (ops)); \ 142 } while (/*CONSTCOND*/0) 143 144 145 struct mvgbe_jpool_entry { 146 int slot; 147 LIST_ENTRY(mvgbe_jpool_entry) jpool_entries; 148 }; 149 150 struct mvgbe_chain { 151 void *mvgbe_desc; 152 struct mbuf *mvgbe_mbuf; 153 struct mvgbe_chain *mvgbe_next; 154 }; 155 156 struct mvgbe_txmap_entry { 157 bus_dmamap_t dmamap; 158 SIMPLEQ_ENTRY(mvgbe_txmap_entry) link; 159 }; 160 161 struct mvgbe_chain_data { 162 struct mvgbe_chain mvgbe_tx_chain[MVGBE_TX_RING_CNT]; 163 struct mvgbe_txmap_entry *mvgbe_tx_map[MVGBE_TX_RING_CNT]; 164 int mvgbe_tx_prod; 165 int mvgbe_tx_cons; 166 int mvgbe_tx_cnt; 167 168 struct mvgbe_chain mvgbe_rx_chain[MVGBE_RX_RING_CNT]; 169 bus_dmamap_t mvgbe_rx_map[MVGBE_RX_RING_CNT]; 170 bus_dmamap_t mvgbe_rx_jumbo_map; 171 int mvgbe_rx_prod; 172 int mvgbe_rx_cons; 173 int mvgbe_rx_cnt; 174 175 /* Stick the jumbo mem management stuff here too. */ 176 void *mvgbe_jslots[MVGBE_JSLOTS]; 177 void *mvgbe_jumbo_buf; 178 }; 179 180 struct mvgbe_ring_data { 181 struct mvgbe_tx_desc mvgbe_tx_ring[MVGBE_TX_RING_CNT]; 182 struct mvgbe_rx_desc mvgbe_rx_ring[MVGBE_RX_RING_CNT]; 183 }; 184 185 struct mvgbec_softc { 186 device_t sc_dev; 187 188 bus_space_tag_t sc_iot; 189 bus_space_handle_t sc_ioh; 190 191 kmutex_t sc_mtx; 192 193 int sc_fix_tqtb; 194 }; 195 196 struct mvgbe_softc { 197 device_t sc_dev; 198 int sc_port; 199 200 bus_space_tag_t sc_iot; 201 bus_space_handle_t sc_ioh; 202 bus_space_handle_t sc_dafh; /* dest address filter handle */ 203 bus_dma_tag_t sc_dmat; 204 205 struct ethercom sc_ethercom; 206 struct mii_data sc_mii; 207 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* station addr */ 208 209 struct mvgbe_chain_data sc_cdata; 210 struct mvgbe_ring_data *sc_rdata; 211 bus_dmamap_t sc_ring_map; 212 int sc_if_flags; 213 214 LIST_HEAD(__mvgbe_jfreehead, mvgbe_jpool_entry) sc_jfree_listhead; 215 LIST_HEAD(__mvgbe_jinusehead, mvgbe_jpool_entry) sc_jinuse_listhead; 216 SIMPLEQ_HEAD(__mvgbe_txmaphead, mvgbe_txmap_entry) sc_txmap_head; 217 218 #if NRND > 0 219 rndsource_element_t sc_rnd_source; 220 #endif 221 }; 222 223 224 /* Gigabit Ethernet Unit Global part functions */ 225 226 static int mvgbec_match(device_t, struct cfdata *, void *); 227 static void mvgbec_attach(device_t, device_t, void *); 228 229 static int mvgbec_print(void *, const char *); 230 static int mvgbec_search(device_t, cfdata_t, const int *, void *); 231 232 /* MII funcstions */ 233 static int mvgbec_miibus_readreg(device_t, int, int); 234 static void mvgbec_miibus_writereg(device_t, int, int, int); 235 static void mvgbec_miibus_statchg(device_t); 236 237 static void mvgbec_wininit(struct mvgbec_softc *); 238 239 /* Gigabit Ethernet Port part functions */ 240 241 static int mvgbe_match(device_t, struct cfdata *, void *); 242 static void mvgbe_attach(device_t, device_t, void *); 243 244 static int mvgbe_intr(void *); 245 246 static void mvgbe_start(struct ifnet *); 247 static int mvgbe_ioctl(struct ifnet *, u_long, void *); 248 static int mvgbe_init(struct ifnet *); 249 static void mvgbe_stop(struct ifnet *, int); 250 static void mvgbe_watchdog(struct ifnet *); 251 252 static int mvgbe_ifflags_cb(struct ethercom *); 253 254 static int mvgbe_mediachange(struct ifnet *); 255 static void mvgbe_mediastatus(struct ifnet *, struct ifmediareq *); 256 257 static int mvgbe_init_rx_ring(struct mvgbe_softc *); 258 static int mvgbe_init_tx_ring(struct mvgbe_softc *); 259 static int mvgbe_newbuf(struct mvgbe_softc *, int, struct mbuf *, bus_dmamap_t); 260 static int mvgbe_alloc_jumbo_mem(struct mvgbe_softc *); 261 static void *mvgbe_jalloc(struct mvgbe_softc *); 262 static void mvgbe_jfree(struct mbuf *, void *, size_t, void *); 263 static int mvgbe_encap(struct mvgbe_softc *, struct mbuf *, uint32_t *); 264 static void mvgbe_rxeof(struct mvgbe_softc *); 265 static void mvgbe_txeof(struct mvgbe_softc *); 266 static uint8_t mvgbe_crc8(const uint8_t *, size_t); 267 static void mvgbe_filter_setup(struct mvgbe_softc *); 268 #ifdef MVGBE_DEBUG 269 static void mvgbe_dump_txdesc(struct mvgbe_tx_desc *, int); 270 #endif 271 272 CFATTACH_DECL_NEW(mvgbec_gt, sizeof(struct mvgbec_softc), 273 mvgbec_match, mvgbec_attach, NULL, NULL); 274 CFATTACH_DECL_NEW(mvgbec_mbus, sizeof(struct mvgbec_softc), 275 mvgbec_match, mvgbec_attach, NULL, NULL); 276 277 CFATTACH_DECL_NEW(mvgbe, sizeof(struct mvgbe_softc), 278 mvgbe_match, mvgbe_attach, NULL, NULL); 279 280 device_t mvgbec0 = NULL; 281 282 struct mvgbe_port { 283 int model; 284 int unit; 285 int ports; 286 int irqs[3]; 287 int flags; 288 #define FLAGS_FIX_TQTB (1 << 0) 289 } mvgbe_ports[] = { 290 { MARVELL_DISCOVERY_II, 0, 3, { 32, 33, 34 }, 0 }, 291 { MARVELL_DISCOVERY_III, 0, 3, { 32, 33, 34 }, 0 }, 292 #if 0 293 { MARVELL_DISCOVERY_LT, 0, ?, { }, 0 }, 294 { MARVELL_DISCOVERY_V, 0, ?, { }, 0 }, 295 { MARVELL_DISCOVERY_VI, 0, ?, { }, 0 }, 296 #endif 297 { MARVELL_ORION_1_88F5082, 0, 1, { 21 }, 0 }, 298 { MARVELL_ORION_1_88F5180N, 0, 1, { 21 }, 0 }, 299 { MARVELL_ORION_1_88F5181, 0, 1, { 21 }, 0 }, 300 { MARVELL_ORION_1_88F5182, 0, 1, { 21 }, 0 }, 301 { MARVELL_ORION_2_88F5281, 0, 1, { 21 }, 0 }, 302 { MARVELL_ORION_1_88F6082, 0, 1, { 21 }, 0 }, 303 { MARVELL_ORION_1_88W8660, 0, 1, { 21 }, 0 }, 304 305 { MARVELL_KIRKWOOD_88F6180, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 306 { MARVELL_KIRKWOOD_88F6192, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 307 { MARVELL_KIRKWOOD_88F6192, 1, 1, { 14 }, FLAGS_FIX_TQTB }, 308 { MARVELL_KIRKWOOD_88F6281, 0, 1, { 11 }, FLAGS_FIX_TQTB }, 309 { MARVELL_KIRKWOOD_88F6281, 1, 1, { 15 }, FLAGS_FIX_TQTB }, 310 311 { MARVELL_MV78XX0_MV78100, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 312 { MARVELL_MV78XX0_MV78100, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 313 { MARVELL_MV78XX0_MV78200, 0, 1, { 40 }, FLAGS_FIX_TQTB }, 314 { MARVELL_MV78XX0_MV78200, 1, 1, { 44 }, FLAGS_FIX_TQTB }, 315 { MARVELL_MV78XX0_MV78200, 2, 1, { 48 }, FLAGS_FIX_TQTB }, 316 { MARVELL_MV78XX0_MV78200, 3, 1, { 52 }, FLAGS_FIX_TQTB }, 317 }; 318 319 320 /* ARGSUSED */ 321 static int 322 mvgbec_match(device_t parent, struct cfdata *match, void *aux) 323 { 324 struct marvell_attach_args *mva = aux; 325 int i; 326 327 if (strcmp(mva->mva_name, match->cf_name) != 0) 328 return 0; 329 if (mva->mva_offset == MVA_OFFSET_DEFAULT) 330 return 0; 331 332 for (i = 0; i < __arraycount(mvgbe_ports); i++) 333 if (mva->mva_model == mvgbe_ports[i].model) { 334 mva->mva_size = MVGBE_SIZE; 335 return 1; 336 } 337 return 0; 338 } 339 340 /* ARGSUSED */ 341 static void 342 mvgbec_attach(device_t parent, device_t self, void *aux) 343 { 344 struct mvgbec_softc *sc = device_private(self); 345 struct marvell_attach_args *mva = aux, gbea; 346 struct mvgbe_softc *port; 347 struct mii_softc *mii; 348 device_t child; 349 uint32_t phyaddr; 350 int i, j; 351 352 aprint_naive("\n"); 353 aprint_normal(": Marvell Gigabit Ethernet Controller\n"); 354 355 sc->sc_dev = self; 356 sc->sc_iot = mva->mva_iot; 357 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, 358 mva->mva_size, &sc->sc_ioh)) { 359 aprint_error_dev(self, "Cannot map registers\n"); 360 return; 361 } 362 363 if (mvgbec0 == NULL) 364 mvgbec0 = self; 365 366 phyaddr = 0; 367 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 368 369 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET); 370 371 /* Disable and clear Gigabit Ethernet Unit interrupts */ 372 MVGBE_WRITE(sc, MVGBE_EUIM, 0); 373 MVGBE_WRITE(sc, MVGBE_EUIC, 0); 374 375 mvgbec_wininit(sc); 376 377 memset(&gbea, 0, sizeof(gbea)); 378 for (i = 0; i < __arraycount(mvgbe_ports); i++) { 379 if (mvgbe_ports[i].model != mva->mva_model || 380 mvgbe_ports[i].unit != mva->mva_unit) 381 continue; 382 383 sc->sc_fix_tqtb = mvgbe_ports[i].flags & FLAGS_FIX_TQTB; 384 385 for (j = 0; j < mvgbe_ports[i].ports; j++) { 386 gbea.mva_name = "mvgbe"; 387 gbea.mva_model = mva->mva_model; 388 gbea.mva_iot = sc->sc_iot; 389 gbea.mva_ioh = sc->sc_ioh; 390 gbea.mva_unit = j; 391 gbea.mva_dmat = mva->mva_dmat; 392 gbea.mva_irq = mvgbe_ports[i].irqs[j]; 393 child = config_found_sm_loc(sc->sc_dev, "mvgbec", NULL, 394 &gbea, mvgbec_print, mvgbec_search); 395 if (child) { 396 port = device_private(child); 397 mii = LIST_FIRST(&port->sc_mii.mii_phys); 398 phyaddr |= MVGBE_PHYADDR_PHYAD(j, mii->mii_phy); 399 } 400 } 401 break; 402 } 403 MVGBE_WRITE(sc, MVGBE_PHYADDR, phyaddr); 404 } 405 406 static int 407 mvgbec_print(void *aux, const char *pnp) 408 { 409 struct marvell_attach_args *gbea = aux; 410 411 if (pnp) 412 aprint_normal("%s at %s port %d", 413 gbea->mva_name, pnp, gbea->mva_unit); 414 else { 415 if (gbea->mva_unit != MVGBECCF_PORT_DEFAULT) 416 aprint_normal(" port %d", gbea->mva_unit); 417 if (gbea->mva_irq != MVGBECCF_IRQ_DEFAULT) 418 aprint_normal(" irq %d", gbea->mva_irq); 419 } 420 return UNCONF; 421 } 422 423 /* ARGSUSED */ 424 static int 425 mvgbec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 426 { 427 struct marvell_attach_args *gbea = aux; 428 429 if (cf->cf_loc[MVGBECCF_PORT] == gbea->mva_unit && 430 cf->cf_loc[MVGBECCF_IRQ] != MVGBECCF_IRQ_DEFAULT) 431 gbea->mva_irq = cf->cf_loc[MVGBECCF_IRQ]; 432 433 return config_match(parent, cf, aux); 434 } 435 436 static int 437 mvgbec_miibus_readreg(device_t dev, int phy, int reg) 438 { 439 struct mvgbe_softc *sc = device_private(dev); 440 struct mvgbec_softc *csc; 441 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 442 uint32_t smi, val; 443 int i; 444 445 if (mvgbec0 == NULL) { 446 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 447 return -1; 448 } 449 csc = device_private(mvgbec0); 450 451 mutex_enter(&csc->sc_mtx); 452 453 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 454 DELAY(1); 455 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 456 break; 457 } 458 if (i == MVGBE_PHY_TIMEOUT) { 459 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 460 mutex_exit(&csc->sc_mtx); 461 return -1; 462 } 463 464 smi = 465 MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | MVGBE_SMI_OPCODE_READ; 466 MVGBE_WRITE(csc, MVGBE_SMI, smi); 467 468 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 469 DELAY(1); 470 smi = MVGBE_READ(csc, MVGBE_SMI); 471 if (smi & MVGBE_SMI_READVALID) 472 break; 473 } 474 475 mutex_exit(&csc->sc_mtx); 476 477 DPRINTFN(9, ("mvgbec_miibus_readreg: i=%d, timeout=%d\n", 478 i, MVGBE_PHY_TIMEOUT)); 479 480 val = smi & MVGBE_SMI_DATA_MASK; 481 482 DPRINTFN(9, ("mvgbec_miibus_readreg phy=%d, reg=%#x, val=%#x\n", 483 phy, reg, val)); 484 485 return val; 486 } 487 488 static void 489 mvgbec_miibus_writereg(device_t dev, int phy, int reg, int val) 490 { 491 struct mvgbe_softc *sc = device_private(dev); 492 struct mvgbec_softc *csc; 493 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 494 uint32_t smi; 495 int i; 496 497 if (mvgbec0 == NULL) { 498 aprint_error_ifnet(ifp, "SMI mvgbec0 not found\n"); 499 return; 500 } 501 csc = device_private(mvgbec0); 502 503 DPRINTFN(9, ("mvgbec_miibus_writereg phy=%d reg=%#x val=%#x\n", 504 phy, reg, val)); 505 506 mutex_enter(&csc->sc_mtx); 507 508 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 509 DELAY(1); 510 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 511 break; 512 } 513 if (i == MVGBE_PHY_TIMEOUT) { 514 aprint_error_ifnet(ifp, "SMI busy timeout\n"); 515 mutex_exit(&csc->sc_mtx); 516 return; 517 } 518 519 smi = MVGBE_SMI_PHYAD(phy) | MVGBE_SMI_REGAD(reg) | 520 MVGBE_SMI_OPCODE_WRITE | (val & MVGBE_SMI_DATA_MASK); 521 MVGBE_WRITE(csc, MVGBE_SMI, smi); 522 523 for (i = 0; i < MVGBE_PHY_TIMEOUT; i++) { 524 DELAY(1); 525 if (!(MVGBE_READ(csc, MVGBE_SMI) & MVGBE_SMI_BUSY)) 526 break; 527 } 528 529 mutex_exit(&csc->sc_mtx); 530 531 if (i == MVGBE_PHY_TIMEOUT) 532 aprint_error_ifnet(ifp, "phy write timed out\n"); 533 } 534 535 static void 536 mvgbec_miibus_statchg(device_t dev) 537 { 538 539 /* nothing to do */ 540 } 541 542 543 static void 544 mvgbec_wininit(struct mvgbec_softc *sc) 545 { 546 device_t pdev = device_parent(sc->sc_dev); 547 uint64_t base; 548 uint32_t en, ac, size; 549 int window, target, attr, rv, i; 550 static int tags[] = { 551 MARVELL_TAG_SDRAM_CS0, 552 MARVELL_TAG_SDRAM_CS1, 553 MARVELL_TAG_SDRAM_CS2, 554 MARVELL_TAG_SDRAM_CS3, 555 556 MARVELL_TAG_UNDEFINED, 557 }; 558 559 /* First disable all address decode windows */ 560 en = MVGBE_BARE_EN_MASK; 561 MVGBE_WRITE(sc, MVGBE_BARE, en); 562 563 ac = 0; 564 for (window = 0, i = 0; 565 tags[i] != MARVELL_TAG_UNDEFINED && window < MVGBE_NWINDOW; i++) { 566 rv = marvell_winparams_by_tag(pdev, tags[i], 567 &target, &attr, &base, &size); 568 if (rv != 0 || size == 0) 569 continue; 570 571 if (base > 0xffffffffULL) { 572 if (window >= MVGBE_NREMAP) { 573 aprint_error_dev(sc->sc_dev, 574 "can't remap window %d\n", window); 575 continue; 576 } 577 MVGBE_WRITE(sc, MVGBE_HA(window), 578 (base >> 32) & 0xffffffff); 579 } 580 581 MVGBE_WRITE(sc, MVGBE_BASEADDR(window), 582 MVGBE_BASEADDR_TARGET(target) | 583 MVGBE_BASEADDR_ATTR(attr) | 584 MVGBE_BASEADDR_BASE(base)); 585 MVGBE_WRITE(sc, MVGBE_S(window), MVGBE_S_SIZE(size)); 586 587 en &= ~(1 << window); 588 /* set full access (r/w) */ 589 ac |= MVGBE_EPAP_EPAR(window, MVGBE_EPAP_AC_FA); 590 window++; 591 } 592 /* allow to access decode window */ 593 MVGBE_WRITE(sc, MVGBE_EPAP, ac); 594 595 MVGBE_WRITE(sc, MVGBE_BARE, en); 596 } 597 598 599 /* ARGSUSED */ 600 static int 601 mvgbe_match(device_t parent, struct cfdata *match, void *aux) 602 { 603 struct marvell_attach_args *mva = aux; 604 uint32_t pbase, maddrh, maddrl; 605 606 pbase = MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE; 607 maddrh = 608 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAH); 609 maddrl = 610 bus_space_read_4(mva->mva_iot, mva->mva_ioh, pbase + MVGBE_MACAL); 611 if ((maddrh | maddrl) == 0) 612 return 0; 613 614 return 1; 615 } 616 617 /* ARGSUSED */ 618 static void 619 mvgbe_attach(device_t parent, device_t self, void *aux) 620 { 621 struct mvgbe_softc *sc = device_private(self); 622 struct mvgbec_softc *csc = device_private(parent); 623 struct marvell_attach_args *mva = aux; 624 struct mvgbe_txmap_entry *entry; 625 struct ifnet *ifp; 626 bus_dma_segment_t seg; 627 bus_dmamap_t dmamap; 628 int rseg, i; 629 uint32_t maddrh, maddrl; 630 void *kva; 631 632 aprint_naive("\n"); 633 aprint_normal("\n"); 634 635 sc->sc_dev = self; 636 sc->sc_port = mva->mva_unit; 637 sc->sc_iot = mva->mva_iot; 638 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 639 MVGBE_PORTR_BASE + mva->mva_unit * MVGBE_PORTR_SIZE, 640 MVGBE_PORTR_SIZE, &sc->sc_ioh)) { 641 aprint_error_dev(self, "Cannot map registers\n"); 642 return; 643 } 644 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, 645 MVGBE_PORTDAFR_BASE + mva->mva_unit * MVGBE_PORTDAFR_SIZE, 646 MVGBE_PORTDAFR_SIZE, &sc->sc_dafh)) { 647 aprint_error_dev(self, 648 "Cannot map destination address filter registers\n"); 649 return; 650 } 651 sc->sc_dmat = mva->mva_dmat; 652 653 maddrh = MVGBE_READ(sc, MVGBE_MACAH); 654 maddrl = MVGBE_READ(sc, MVGBE_MACAL); 655 sc->sc_enaddr[0] = maddrh >> 24; 656 sc->sc_enaddr[1] = maddrh >> 16; 657 sc->sc_enaddr[2] = maddrh >> 8; 658 sc->sc_enaddr[3] = maddrh >> 0; 659 sc->sc_enaddr[4] = maddrl >> 8; 660 sc->sc_enaddr[5] = maddrl >> 0; 661 aprint_normal_dev(self, "Ethernet address %s\n", 662 ether_sprintf(sc->sc_enaddr)); 663 664 /* clear all ethernet port interrupts */ 665 MVGBE_WRITE(sc, MVGBE_IC, 0); 666 MVGBE_WRITE(sc, MVGBE_ICE, 0); 667 668 marvell_intr_establish(mva->mva_irq, IPL_NET, mvgbe_intr, sc); 669 670 /* Allocate the descriptor queues. */ 671 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 672 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 673 aprint_error_dev(self, "can't alloc rx buffers\n"); 674 return; 675 } 676 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, 677 sizeof(struct mvgbe_ring_data), &kva, BUS_DMA_NOWAIT)) { 678 aprint_error_dev(self, "can't map dma buffers (%lu bytes)\n", 679 (u_long)sizeof(struct mvgbe_ring_data)); 680 goto fail1; 681 } 682 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mvgbe_ring_data), 1, 683 sizeof(struct mvgbe_ring_data), 0, BUS_DMA_NOWAIT, 684 &sc->sc_ring_map)) { 685 aprint_error_dev(self, "can't create dma map\n"); 686 goto fail2; 687 } 688 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ring_map, kva, 689 sizeof(struct mvgbe_ring_data), NULL, BUS_DMA_NOWAIT)) { 690 aprint_error_dev(self, "can't load dma map\n"); 691 goto fail3; 692 } 693 for (i = 0; i < MVGBE_RX_RING_CNT; i++) 694 sc->sc_cdata.mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 695 696 SIMPLEQ_INIT(&sc->sc_txmap_head); 697 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 698 sc->sc_cdata.mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 699 700 if (bus_dmamap_create(sc->sc_dmat, 701 MVGBE_JLEN, MVGBE_NTXSEG, MVGBE_JLEN, 0, 702 BUS_DMA_NOWAIT, &dmamap)) { 703 aprint_error_dev(self, "Can't create TX dmamap\n"); 704 goto fail4; 705 } 706 707 entry = kmem_alloc(sizeof(*entry), KM_SLEEP); 708 if (!entry) { 709 aprint_error_dev(self, "Can't alloc txmap entry\n"); 710 bus_dmamap_destroy(sc->sc_dmat, dmamap); 711 goto fail4; 712 } 713 entry->dmamap = dmamap; 714 SIMPLEQ_INSERT_HEAD(&sc->sc_txmap_head, entry, link); 715 } 716 717 sc->sc_rdata = (struct mvgbe_ring_data *)kva; 718 memset(sc->sc_rdata, 0, sizeof(struct mvgbe_ring_data)); 719 720 /* 721 * We can support 802.1Q VLAN-sized frames and jumbo 722 * Ethernet frames. 723 */ 724 sc->sc_ethercom.ec_capabilities |= 725 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 726 727 /* Try to allocate memory for jumbo buffers. */ 728 if (mvgbe_alloc_jumbo_mem(sc)) { 729 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 730 goto fail4; 731 } 732 733 ifp = &sc->sc_ethercom.ec_if; 734 ifp->if_softc = sc; 735 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 736 ifp->if_start = mvgbe_start; 737 ifp->if_ioctl = mvgbe_ioctl; 738 ifp->if_init = mvgbe_init; 739 ifp->if_stop = mvgbe_stop; 740 ifp->if_watchdog = mvgbe_watchdog; 741 /* 742 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 743 */ 744 sc->sc_ethercom.ec_if.if_capabilities |= 745 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 746 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 747 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 748 /* 749 * But, IPv6 packets in the stream can cause incorrect TCPv4 Tx sums. 750 */ 751 sc->sc_ethercom.ec_if.if_capabilities &= ~IFCAP_CSUM_TCPv4_Tx; 752 IFQ_SET_MAXLEN(&ifp->if_snd, max(MVGBE_TX_RING_CNT - 1, IFQ_MAXLEN)); 753 IFQ_SET_READY(&ifp->if_snd); 754 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 755 756 mvgbe_stop(ifp, 0); 757 758 /* 759 * Do MII setup. 760 */ 761 sc->sc_mii.mii_ifp = ifp; 762 sc->sc_mii.mii_readreg = mvgbec_miibus_readreg; 763 sc->sc_mii.mii_writereg = mvgbec_miibus_writereg; 764 sc->sc_mii.mii_statchg = mvgbec_miibus_statchg; 765 766 sc->sc_ethercom.ec_mii = &sc->sc_mii; 767 ifmedia_init(&sc->sc_mii.mii_media, 0, 768 mvgbe_mediachange, mvgbe_mediastatus); 769 mii_attach(self, &sc->sc_mii, 0xffffffff, 770 parent == mvgebc0 ? 0 : 1, MII_OFFSET_ANY, 0); 771 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 772 aprint_error_dev(self, "no PHY found!\n"); 773 ifmedia_add(&sc->sc_mii.mii_media, 774 IFM_ETHER|IFM_MANUAL, 0, NULL); 775 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 776 } else 777 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 778 779 /* 780 * Call MI attach routines. 781 */ 782 if_attach(ifp); 783 784 ether_ifattach(ifp, sc->sc_enaddr); 785 ether_set_ifflags_cb(&sc->sc_ethercom, mvgbe_ifflags_cb); 786 787 #if NRND > 0 788 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 789 RND_TYPE_NET, 0); 790 #endif 791 792 return; 793 794 fail4: 795 while ((entry = SIMPLEQ_FIRST(&sc->sc_txmap_head)) != NULL) { 796 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 797 bus_dmamap_destroy(sc->sc_dmat, entry->dmamap); 798 } 799 bus_dmamap_unload(sc->sc_dmat, sc->sc_ring_map); 800 fail3: 801 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ring_map); 802 fail2: 803 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct mvgbe_ring_data)); 804 fail1: 805 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 806 return; 807 } 808 809 810 static int 811 mvgbe_intr(void *arg) 812 { 813 struct mvgbe_softc *sc = arg; 814 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 815 uint32_t ic, ice, datum = 0; 816 int claimed = 0; 817 818 for (;;) { 819 ice = MVGBE_READ(sc, MVGBE_ICE); 820 ic = MVGBE_READ(sc, MVGBE_IC); 821 822 DPRINTFN(3, ("mvgbe_intr: ic=%#x, ice=%#x\n", ic, ice)); 823 if (ic == 0 && ice == 0) 824 break; 825 826 datum = datum ^ ic ^ ice; 827 828 MVGBE_WRITE(sc, MVGBE_IC, ~ic); 829 MVGBE_WRITE(sc, MVGBE_ICE, ~ice); 830 831 claimed = 1; 832 833 if (ice & MVGBE_ICE_LINKCHG) { 834 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 835 /* Enable port RX and TX. */ 836 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 837 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 838 } else { 839 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ(0)); 840 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 841 } 842 } 843 844 if (ic & (MVGBE_IC_RXBUF | MVGBE_IC_RXERROR)) 845 mvgbe_rxeof(sc); 846 847 if (ice & (MVGBE_ICE_TXBUF | MVGBE_ICE_TXERR)) 848 mvgbe_txeof(sc); 849 } 850 851 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 852 mvgbe_start(ifp); 853 854 #if NRND > 0 855 if (RND_ENABLED(&sc->sc_rnd_source)) 856 rnd_add_uint32(&sc->sc_rnd_source, datum); 857 #endif 858 859 return claimed; 860 } 861 862 static void 863 mvgbe_start(struct ifnet *ifp) 864 { 865 struct mvgbe_softc *sc = ifp->if_softc; 866 struct mbuf *m_head = NULL; 867 uint32_t idx = sc->sc_cdata.mvgbe_tx_prod; 868 int pkts = 0; 869 870 DPRINTFN(3, ("mvgbe_start (idx %d, tx_chain[idx] %p)\n", idx, 871 sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf)); 872 873 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 874 return; 875 /* If Link is DOWN, can't start TX */ 876 if (!(MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP)) 877 return; 878 879 while (sc->sc_cdata.mvgbe_tx_chain[idx].mvgbe_mbuf == NULL) { 880 IFQ_POLL(&ifp->if_snd, m_head); 881 if (m_head == NULL) 882 break; 883 884 /* 885 * Pack the data into the transmit ring. If we 886 * don't have room, set the OACTIVE flag and wait 887 * for the NIC to drain the ring. 888 */ 889 if (mvgbe_encap(sc, m_head, &idx)) { 890 ifp->if_flags |= IFF_OACTIVE; 891 break; 892 } 893 894 /* now we are committed to transmit the packet */ 895 IFQ_DEQUEUE(&ifp->if_snd, m_head); 896 pkts++; 897 898 /* 899 * If there's a BPF listener, bounce a copy of this frame 900 * to him. 901 */ 902 if (ifp->if_bpf) 903 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 904 } 905 if (pkts == 0) 906 return; 907 908 /* Transmit at Queue 0 */ 909 if (idx != sc->sc_cdata.mvgbe_tx_prod) { 910 sc->sc_cdata.mvgbe_tx_prod = idx; 911 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 912 913 /* 914 * Set a timeout in case the chip goes out to lunch. 915 */ 916 ifp->if_timer = 5; 917 } 918 } 919 920 static int 921 mvgbe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 922 { 923 struct mvgbe_softc *sc = ifp->if_softc; 924 struct ifreq *ifr = data; 925 int s, error = 0; 926 927 s = splnet(); 928 929 switch (cmd) { 930 case SIOCGIFMEDIA: 931 case SIOCSIFMEDIA: 932 DPRINTFN(2, ("mvgbe_ioctl MEDIA\n")); 933 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 934 break; 935 default: 936 DPRINTFN(2, ("mvgbe_ioctl ETHER\n")); 937 error = ether_ioctl(ifp, cmd, data); 938 if (error == ENETRESET) { 939 if (ifp->if_flags & IFF_RUNNING) { 940 mvgbe_filter_setup(sc); 941 } 942 error = 0; 943 } 944 break; 945 } 946 947 splx(s); 948 949 return error; 950 } 951 952 int mvgbe_rximt = 0; 953 int mvgbe_tximt = 0; 954 955 static int 956 mvgbe_init(struct ifnet *ifp) 957 { 958 struct mvgbe_softc *sc = ifp->if_softc; 959 struct mvgbec_softc *csc = device_private(device_parent(sc->sc_dev)); 960 struct mii_data *mii = &sc->sc_mii; 961 uint32_t reg; 962 int i; 963 964 DPRINTFN(2, ("mvgbe_init\n")); 965 966 /* Cancel pending I/O and free all RX/TX buffers. */ 967 mvgbe_stop(ifp, 0); 968 969 /* clear all ethernet port interrupts */ 970 MVGBE_WRITE(sc, MVGBE_IC, 0); 971 MVGBE_WRITE(sc, MVGBE_ICE, 0); 972 973 /* Init TX/RX descriptors */ 974 if (mvgbe_init_tx_ring(sc) == ENOBUFS) { 975 aprint_error_ifnet(ifp, 976 "initialization failed: no memory for tx buffers\n"); 977 return ENOBUFS; 978 } 979 if (mvgbe_init_rx_ring(sc) == ENOBUFS) { 980 aprint_error_ifnet(ifp, 981 "initialization failed: no memory for rx buffers\n"); 982 return ENOBUFS; 983 } 984 985 MVGBE_WRITE(sc, MVGBE_PSC, 986 MVGBE_PSC_ANFC | /* Enable Auto-Neg Flow Ctrl */ 987 MVGBE_PSC_RESERVED | /* Must be set to 1 */ 988 MVGBE_PSC_FLFAIL | /* Do NOT Force Link Fail */ 989 MVGBE_PSC_MRU(MVGBE_PSC_MRU_9022) | /* we want 9k */ 990 MVGBE_PSC_SETFULLDX); /* Set_FullDx */ 991 /* XXXX: mvgbe(4) always use RGMII. */ 992 MVGBE_WRITE(sc, MVGBE_PSC1, 993 MVGBE_READ(sc, MVGBE_PSC1) | MVGBE_PSC1_RGMIIEN); 994 /* XXXX: Also always Weighted Round-Robin Priority Mode */ 995 MVGBE_WRITE(sc, MVGBE_TQFPC, MVGBE_TQFPC_EN(0)); 996 997 MVGBE_WRITE(sc, MVGBE_CRDP(0), MVGBE_RX_RING_ADDR(sc, 0)); 998 MVGBE_WRITE(sc, MVGBE_TCQDP, MVGBE_TX_RING_ADDR(sc, 0)); 999 1000 if (csc->sc_fix_tqtb) { 1001 /* 1002 * Queue 0 (offset 0x72700) must be programmed to 0x3fffffff. 1003 * And offset 0x72704 must be programmed to 0x03ffffff. 1004 * Queue 1 through 7 must be programmed to 0x0. 1005 */ 1006 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(0), 0x3fffffff); 1007 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(0), 0x03ffffff); 1008 for (i = 1; i < 8; i++) { 1009 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x0); 1010 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0x0); 1011 } 1012 } else 1013 for (i = 1; i < 8; i++) { 1014 MVGBE_WRITE(sc, MVGBE_TQTBCOUNT(i), 0x3fffffff); 1015 MVGBE_WRITE(sc, MVGBE_TQTBCONFIG(i), 0xffff7fff); 1016 MVGBE_WRITE(sc, MVGBE_TQAC(i), 0xfc0000ff); 1017 } 1018 1019 MVGBE_WRITE(sc, MVGBE_PXC, MVGBE_PXC_RXCS); 1020 MVGBE_WRITE(sc, MVGBE_PXCX, 0); 1021 MVGBE_WRITE(sc, MVGBE_SDC, 1022 MVGBE_SDC_RXBSZ_16_64BITWORDS | 1023 #if BYTE_ORDER == LITTLE_ENDIAN 1024 MVGBE_SDC_BLMR | /* Big/Little Endian Receive Mode: No swap */ 1025 MVGBE_SDC_BLMT | /* Big/Little Endian Transmit Mode: No swap */ 1026 #endif 1027 MVGBE_SDC_IPGINTRX(mvgbe_rximt) | 1028 MVGBE_SDC_TXBSZ_16_64BITWORDS); 1029 MVGBE_WRITE(sc, MVGBE_PTFUT, MVGBE_PTFUT_IPGINTTX(mvgbe_tximt)); 1030 1031 mvgbe_filter_setup(sc); 1032 1033 mii_mediachg(mii); 1034 1035 /* Enable port */ 1036 reg = MVGBE_READ(sc, MVGBE_PSC); 1037 MVGBE_WRITE(sc, MVGBE_PSC, reg | MVGBE_PSC_PORTEN); 1038 1039 /* If Link is UP, Start RX and TX traffic */ 1040 if (MVGBE_READ(sc, MVGBE_PS) & MVGBE_PS_LINKUP) { 1041 /* Enable port RX/TX. */ 1042 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_ENQ(0)); 1043 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_ENQ); 1044 } 1045 1046 /* Enable interrupt masks */ 1047 MVGBE_WRITE(sc, MVGBE_PIM, 1048 MVGBE_IC_RXBUF | 1049 MVGBE_IC_EXTEND | 1050 MVGBE_IC_RXBUFQ_MASK | 1051 MVGBE_IC_RXERROR | 1052 MVGBE_IC_RXERRQ_MASK); 1053 MVGBE_WRITE(sc, MVGBE_PEIM, 1054 MVGBE_ICE_TXBUF | 1055 MVGBE_ICE_TXERR | 1056 MVGBE_ICE_LINKCHG); 1057 1058 ifp->if_flags |= IFF_RUNNING; 1059 ifp->if_flags &= ~IFF_OACTIVE; 1060 1061 return 0; 1062 } 1063 1064 /* ARGSUSED */ 1065 static void 1066 mvgbe_stop(struct ifnet *ifp, int disable) 1067 { 1068 struct mvgbe_softc *sc = ifp->if_softc; 1069 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1070 uint32_t reg; 1071 int i, cnt; 1072 1073 DPRINTFN(2, ("mvgbe_stop\n")); 1074 1075 /* Stop Rx port activity. Check port Rx activity. */ 1076 reg = MVGBE_READ(sc, MVGBE_RQC); 1077 if (reg & MVGBE_RQC_ENQ_MASK) 1078 /* Issue stop command for active channels only */ 1079 MVGBE_WRITE(sc, MVGBE_RQC, MVGBE_RQC_DISQ_DISABLE(reg)); 1080 1081 /* Stop Tx port activity. Check port Tx activity. */ 1082 if (MVGBE_READ(sc, MVGBE_TQC) & MVGBE_TQC_ENQ) 1083 MVGBE_WRITE(sc, MVGBE_TQC, MVGBE_TQC_DISQ); 1084 1085 /* Force link down */ 1086 reg = MVGBE_READ(sc, MVGBE_PSC); 1087 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_FLFAIL); 1088 1089 #define RX_DISABLE_TIMEOUT 0x1000000 1090 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 1091 /* Wait for all Rx activity to terminate. */ 1092 cnt = 0; 1093 do { 1094 if (cnt >= RX_DISABLE_TIMEOUT) { 1095 aprint_error_ifnet(ifp, 1096 "timeout for RX stopped. rqc 0x%x\n", reg); 1097 break; 1098 } 1099 cnt++; 1100 1101 /* 1102 * Check Receive Queue Command register that all Rx queues 1103 * are stopped 1104 */ 1105 reg = MVGBE_READ(sc, MVGBE_RQC); 1106 } while (reg & 0xff); 1107 1108 /* Double check to verify that TX FIFO is empty */ 1109 cnt = 0; 1110 while (1) { 1111 do { 1112 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1113 aprint_error_ifnet(ifp, 1114 "timeout for TX FIFO empty. status 0x%x\n", 1115 reg); 1116 break; 1117 } 1118 cnt++; 1119 1120 reg = MVGBE_READ(sc, MVGBE_PS); 1121 } while 1122 (!(reg & MVGBE_PS_TXFIFOEMP) || reg & MVGBE_PS_TXINPROG); 1123 1124 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) 1125 break; 1126 1127 /* Double check */ 1128 reg = MVGBE_READ(sc, MVGBE_PS); 1129 if (reg & MVGBE_PS_TXFIFOEMP && !(reg & MVGBE_PS_TXINPROG)) 1130 break; 1131 else 1132 aprint_error_ifnet(ifp, 1133 "TX FIFO empty double check failed." 1134 " %d loops, status 0x%x\n", cnt, reg); 1135 } 1136 1137 /* Reset the Enable bit in the Port Serial Control Register */ 1138 reg = MVGBE_READ(sc, MVGBE_PSC); 1139 MVGBE_WRITE(sc, MVGBE_PSC, reg & ~MVGBE_PSC_PORTEN); 1140 1141 /* Disable interrupts */ 1142 MVGBE_WRITE(sc, MVGBE_PIM, 0); 1143 MVGBE_WRITE(sc, MVGBE_PEIM, 0); 1144 1145 /* Free RX and TX mbufs still in the queues. */ 1146 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1147 if (cdata->mvgbe_rx_chain[i].mvgbe_mbuf != NULL) { 1148 m_freem(cdata->mvgbe_rx_chain[i].mvgbe_mbuf); 1149 cdata->mvgbe_rx_chain[i].mvgbe_mbuf = NULL; 1150 } 1151 } 1152 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1153 if (cdata->mvgbe_tx_chain[i].mvgbe_mbuf != NULL) { 1154 m_freem(cdata->mvgbe_tx_chain[i].mvgbe_mbuf); 1155 cdata->mvgbe_tx_chain[i].mvgbe_mbuf = NULL; 1156 } 1157 } 1158 1159 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1160 } 1161 1162 static void 1163 mvgbe_watchdog(struct ifnet *ifp) 1164 { 1165 struct mvgbe_softc *sc = ifp->if_softc; 1166 1167 /* 1168 * Reclaim first as there is a possibility of losing Tx completion 1169 * interrupts. 1170 */ 1171 mvgbe_txeof(sc); 1172 if (sc->sc_cdata.mvgbe_tx_cnt != 0) { 1173 aprint_error_ifnet(ifp, "watchdog timeout\n"); 1174 1175 ifp->if_oerrors++; 1176 1177 mvgbe_init(ifp); 1178 } 1179 } 1180 1181 static int 1182 mvgbe_ifflags_cb(struct ethercom *ec) 1183 { 1184 struct ifnet *ifp = &ec->ec_if; 1185 struct mvgbe_softc *sc = ifp->if_softc; 1186 int change = ifp->if_flags ^ sc->sc_if_flags; 1187 1188 if (change != 0) 1189 sc->sc_if_flags = ifp->if_flags; 1190 1191 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1192 return ENETRESET; 1193 1194 if ((change & IFF_PROMISC) != 0) 1195 mvgbe_filter_setup(sc); 1196 1197 return 0; 1198 } 1199 1200 /* 1201 * Set media options. 1202 */ 1203 static int 1204 mvgbe_mediachange(struct ifnet *ifp) 1205 { 1206 return ether_mediachange(ifp); 1207 } 1208 1209 /* 1210 * Report current media status. 1211 */ 1212 static void 1213 mvgbe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1214 { 1215 ether_mediastatus(ifp, ifmr); 1216 } 1217 1218 1219 static int 1220 mvgbe_init_rx_ring(struct mvgbe_softc *sc) 1221 { 1222 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1223 struct mvgbe_ring_data *rd = sc->sc_rdata; 1224 int i; 1225 1226 memset(rd->mvgbe_rx_ring, 0, 1227 sizeof(struct mvgbe_rx_desc) * MVGBE_RX_RING_CNT); 1228 1229 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1230 cd->mvgbe_rx_chain[i].mvgbe_desc = 1231 &rd->mvgbe_rx_ring[i]; 1232 if (i == MVGBE_RX_RING_CNT - 1) { 1233 cd->mvgbe_rx_chain[i].mvgbe_next = 1234 &cd->mvgbe_rx_chain[0]; 1235 rd->mvgbe_rx_ring[i].nextdescptr = 1236 MVGBE_RX_RING_ADDR(sc, 0); 1237 } else { 1238 cd->mvgbe_rx_chain[i].mvgbe_next = 1239 &cd->mvgbe_rx_chain[i + 1]; 1240 rd->mvgbe_rx_ring[i].nextdescptr = 1241 MVGBE_RX_RING_ADDR(sc, i + 1); 1242 } 1243 } 1244 1245 for (i = 0; i < MVGBE_RX_RING_CNT; i++) { 1246 if (mvgbe_newbuf(sc, i, NULL, 1247 sc->sc_cdata.mvgbe_rx_jumbo_map) == ENOBUFS) { 1248 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1249 "failed alloc of %dth mbuf\n", i); 1250 return ENOBUFS; 1251 } 1252 } 1253 sc->sc_cdata.mvgbe_rx_prod = 0; 1254 sc->sc_cdata.mvgbe_rx_cons = 0; 1255 1256 return 0; 1257 } 1258 1259 static int 1260 mvgbe_init_tx_ring(struct mvgbe_softc *sc) 1261 { 1262 struct mvgbe_chain_data *cd = &sc->sc_cdata; 1263 struct mvgbe_ring_data *rd = sc->sc_rdata; 1264 int i; 1265 1266 memset(sc->sc_rdata->mvgbe_tx_ring, 0, 1267 sizeof(struct mvgbe_tx_desc) * MVGBE_TX_RING_CNT); 1268 1269 for (i = 0; i < MVGBE_TX_RING_CNT; i++) { 1270 cd->mvgbe_tx_chain[i].mvgbe_desc = 1271 &rd->mvgbe_tx_ring[i]; 1272 if (i == MVGBE_TX_RING_CNT - 1) { 1273 cd->mvgbe_tx_chain[i].mvgbe_next = 1274 &cd->mvgbe_tx_chain[0]; 1275 rd->mvgbe_tx_ring[i].nextdescptr = 1276 MVGBE_TX_RING_ADDR(sc, 0); 1277 } else { 1278 cd->mvgbe_tx_chain[i].mvgbe_next = 1279 &cd->mvgbe_tx_chain[i + 1]; 1280 rd->mvgbe_tx_ring[i].nextdescptr = 1281 MVGBE_TX_RING_ADDR(sc, i + 1); 1282 } 1283 rd->mvgbe_tx_ring[i].cmdsts = MVGBE_BUFFER_OWNED_BY_HOST; 1284 } 1285 1286 sc->sc_cdata.mvgbe_tx_prod = 0; 1287 sc->sc_cdata.mvgbe_tx_cons = 0; 1288 sc->sc_cdata.mvgbe_tx_cnt = 0; 1289 1290 MVGBE_CDTXSYNC(sc, 0, MVGBE_TX_RING_CNT, 1291 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1292 1293 return 0; 1294 } 1295 1296 static int 1297 mvgbe_newbuf(struct mvgbe_softc *sc, int i, struct mbuf *m, 1298 bus_dmamap_t dmamap) 1299 { 1300 struct mbuf *m_new = NULL; 1301 struct mvgbe_chain *c; 1302 struct mvgbe_rx_desc *r; 1303 int align; 1304 1305 if (m == NULL) { 1306 void *buf = NULL; 1307 1308 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1309 if (m_new == NULL) { 1310 aprint_error_ifnet(&sc->sc_ethercom.ec_if, 1311 "no memory for rx list -- packet dropped!\n"); 1312 return ENOBUFS; 1313 } 1314 1315 /* Allocate the jumbo buffer */ 1316 buf = mvgbe_jalloc(sc); 1317 if (buf == NULL) { 1318 m_freem(m_new); 1319 DPRINTFN(1, ("%s jumbo allocation failed -- packet " 1320 "dropped!\n", sc->sc_ethercom.ec_if.if_xname)); 1321 return ENOBUFS; 1322 } 1323 1324 /* Attach the buffer to the mbuf */ 1325 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1326 MEXTADD(m_new, buf, MVGBE_JLEN, 0, mvgbe_jfree, sc); 1327 } else { 1328 /* 1329 * We're re-using a previously allocated mbuf; 1330 * be sure to re-init pointers and lengths to 1331 * default values. 1332 */ 1333 m_new = m; 1334 m_new->m_len = m_new->m_pkthdr.len = MVGBE_JLEN; 1335 m_new->m_data = m_new->m_ext.ext_buf; 1336 } 1337 align = (u_long)m_new->m_data & MVGBE_RXBUF_MASK; 1338 if (align != 0) { 1339 DPRINTFN(1,("align = %d\n", align)); 1340 m_adj(m_new, MVGBE_RXBUF_ALIGN - align); 1341 } 1342 1343 c = &sc->sc_cdata.mvgbe_rx_chain[i]; 1344 r = c->mvgbe_desc; 1345 c->mvgbe_mbuf = m_new; 1346 r->bufptr = dmamap->dm_segs[0].ds_addr + 1347 (((vaddr_t)m_new->m_data - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf)); 1348 r->bufsize = MVGBE_JLEN & ~MVGBE_RXBUF_MASK; 1349 r->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_ENABLE_INTERRUPT; 1350 1351 MVGBE_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1352 1353 return 0; 1354 } 1355 1356 /* 1357 * Memory management for jumbo frames. 1358 */ 1359 1360 static int 1361 mvgbe_alloc_jumbo_mem(struct mvgbe_softc *sc) 1362 { 1363 char *ptr, *kva; 1364 bus_dma_segment_t seg; 1365 int i, rseg, state, error; 1366 struct mvgbe_jpool_entry *entry; 1367 1368 state = error = 0; 1369 1370 /* Grab a big chunk o' storage. */ 1371 if (bus_dmamem_alloc(sc->sc_dmat, MVGBE_JMEM, PAGE_SIZE, 0, 1372 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1373 aprint_error_dev(sc->sc_dev, "can't alloc rx buffers\n"); 1374 return ENOBUFS; 1375 } 1376 1377 state = 1; 1378 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, MVGBE_JMEM, 1379 (void **)&kva, BUS_DMA_NOWAIT)) { 1380 aprint_error_dev(sc->sc_dev, 1381 "can't map dma buffers (%d bytes)\n", MVGBE_JMEM); 1382 error = ENOBUFS; 1383 goto out; 1384 } 1385 1386 state = 2; 1387 if (bus_dmamap_create(sc->sc_dmat, MVGBE_JMEM, 1, MVGBE_JMEM, 0, 1388 BUS_DMA_NOWAIT, &sc->sc_cdata.mvgbe_rx_jumbo_map)) { 1389 aprint_error_dev(sc->sc_dev, "can't create dma map\n"); 1390 error = ENOBUFS; 1391 goto out; 1392 } 1393 1394 state = 3; 1395 if (bus_dmamap_load(sc->sc_dmat, sc->sc_cdata.mvgbe_rx_jumbo_map, 1396 kva, MVGBE_JMEM, NULL, BUS_DMA_NOWAIT)) { 1397 aprint_error_dev(sc->sc_dev, "can't load dma map\n"); 1398 error = ENOBUFS; 1399 goto out; 1400 } 1401 1402 state = 4; 1403 sc->sc_cdata.mvgbe_jumbo_buf = (void *)kva; 1404 DPRINTFN(1,("mvgbe_jumbo_buf = %p\n", sc->sc_cdata.mvgbe_jumbo_buf)); 1405 1406 LIST_INIT(&sc->sc_jfree_listhead); 1407 LIST_INIT(&sc->sc_jinuse_listhead); 1408 1409 /* 1410 * Now divide it up into 9K pieces and save the addresses 1411 * in an array. 1412 */ 1413 ptr = sc->sc_cdata.mvgbe_jumbo_buf; 1414 for (i = 0; i < MVGBE_JSLOTS; i++) { 1415 sc->sc_cdata.mvgbe_jslots[i] = ptr; 1416 ptr += MVGBE_JLEN; 1417 entry = kmem_alloc(sizeof(struct mvgbe_jpool_entry), KM_SLEEP); 1418 if (entry == NULL) { 1419 aprint_error_dev(sc->sc_dev, 1420 "no memory for jumbo buffer queue!\n"); 1421 error = ENOBUFS; 1422 goto out; 1423 } 1424 entry->slot = i; 1425 if (i) 1426 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, 1427 jpool_entries); 1428 else 1429 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, 1430 jpool_entries); 1431 } 1432 out: 1433 if (error != 0) { 1434 switch (state) { 1435 case 4: 1436 bus_dmamap_unload(sc->sc_dmat, 1437 sc->sc_cdata.mvgbe_rx_jumbo_map); 1438 case 3: 1439 bus_dmamap_destroy(sc->sc_dmat, 1440 sc->sc_cdata.mvgbe_rx_jumbo_map); 1441 case 2: 1442 bus_dmamem_unmap(sc->sc_dmat, kva, MVGBE_JMEM); 1443 case 1: 1444 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1445 break; 1446 default: 1447 break; 1448 } 1449 } 1450 1451 return error; 1452 } 1453 1454 /* 1455 * Allocate a jumbo buffer. 1456 */ 1457 static void * 1458 mvgbe_jalloc(struct mvgbe_softc *sc) 1459 { 1460 struct mvgbe_jpool_entry *entry; 1461 1462 entry = LIST_FIRST(&sc->sc_jfree_listhead); 1463 1464 if (entry == NULL) 1465 return NULL; 1466 1467 LIST_REMOVE(entry, jpool_entries); 1468 LIST_INSERT_HEAD(&sc->sc_jinuse_listhead, entry, jpool_entries); 1469 return sc->sc_cdata.mvgbe_jslots[entry->slot]; 1470 } 1471 1472 /* 1473 * Release a jumbo buffer. 1474 */ 1475 static void 1476 mvgbe_jfree(struct mbuf *m, void *buf, size_t size, void *arg) 1477 { 1478 struct mvgbe_jpool_entry *entry; 1479 struct mvgbe_softc *sc; 1480 int i, s; 1481 1482 /* Extract the softc struct pointer. */ 1483 sc = (struct mvgbe_softc *)arg; 1484 1485 if (sc == NULL) 1486 panic("%s: can't find softc pointer!", __func__); 1487 1488 /* calculate the slot this buffer belongs to */ 1489 1490 i = ((vaddr_t)buf - (vaddr_t)sc->sc_cdata.mvgbe_jumbo_buf) / MVGBE_JLEN; 1491 1492 if ((i < 0) || (i >= MVGBE_JSLOTS)) 1493 panic("%s: asked to free buffer that we don't manage!", 1494 __func__); 1495 1496 s = splvm(); 1497 entry = LIST_FIRST(&sc->sc_jinuse_listhead); 1498 if (entry == NULL) 1499 panic("%s: buffer not in use!", __func__); 1500 entry->slot = i; 1501 LIST_REMOVE(entry, jpool_entries); 1502 LIST_INSERT_HEAD(&sc->sc_jfree_listhead, entry, jpool_entries); 1503 1504 if (__predict_true(m != NULL)) 1505 pool_cache_put(mb_cache, m); 1506 splx(s); 1507 } 1508 1509 static int 1510 mvgbe_encap(struct mvgbe_softc *sc, struct mbuf *m_head, 1511 uint32_t *txidx) 1512 { 1513 struct mvgbe_tx_desc *f = NULL; 1514 struct mvgbe_txmap_entry *entry; 1515 bus_dma_segment_t *txseg; 1516 bus_dmamap_t txmap; 1517 uint32_t first, current, last, cmdsts = 0; 1518 int m_csumflags, i; 1519 1520 DPRINTFN(3, ("mvgbe_encap\n")); 1521 1522 entry = SIMPLEQ_FIRST(&sc->sc_txmap_head); 1523 if (entry == NULL) { 1524 DPRINTFN(2, ("mvgbe_encap: no txmap available\n")); 1525 return ENOBUFS; 1526 } 1527 txmap = entry->dmamap; 1528 1529 first = current = last = *txidx; 1530 1531 /* 1532 * Preserve m_pkthdr.csum_flags here since m_head might be 1533 * updated by m_defrag() 1534 */ 1535 m_csumflags = m_head->m_pkthdr.csum_flags; 1536 1537 /* 1538 * Start packing the mbufs in this chain into 1539 * the fragment pointers. Stop when we run out 1540 * of fragments or hit the end of the mbuf chain. 1541 */ 1542 if (bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, BUS_DMA_NOWAIT)) { 1543 DPRINTFN(1, ("mvgbe_encap: dmamap failed\n")); 1544 return ENOBUFS; 1545 } 1546 1547 /* Sync the DMA map. */ 1548 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1549 BUS_DMASYNC_PREWRITE); 1550 1551 if (sc->sc_cdata.mvgbe_tx_cnt + txmap->dm_nsegs >= 1552 MVGBE_TX_RING_CNT) { 1553 DPRINTFN(2, ("mvgbe_encap: too few descriptors free\n")); 1554 bus_dmamap_unload(sc->sc_dmat, txmap); 1555 return ENOBUFS; 1556 } 1557 1558 txseg = txmap->dm_segs; 1559 1560 DPRINTFN(2, ("mvgbe_encap: dm_nsegs=%d\n", txmap->dm_nsegs)); 1561 1562 for (i = 0; i < txmap->dm_nsegs; i++) { 1563 f = &sc->sc_rdata->mvgbe_tx_ring[current]; 1564 f->bufptr = txseg[i].ds_addr; 1565 f->bytecnt = txseg[i].ds_len; 1566 f->cmdsts = MVGBE_BUFFER_OWNED_BY_DMA; 1567 last = current; 1568 current = MVGBE_TX_RING_NEXT(current); 1569 } 1570 1571 if (m_csumflags & M_CSUM_IPv4) 1572 cmdsts |= MVGBE_TX_GENERATE_IP_CHKSUM; 1573 if (m_csumflags & M_CSUM_TCPv4) 1574 cmdsts |= 1575 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_TCP; 1576 if (m_csumflags & M_CSUM_UDPv4) 1577 cmdsts |= 1578 MVGBE_TX_GENERATE_L4_CHKSUM | MVGBE_TX_L4_TYPE_UDP; 1579 if (m_csumflags & (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1580 const int iphdr_unitlen = sizeof(struct ip) / sizeof(uint32_t); 1581 1582 cmdsts |= MVGBE_TX_IP_NO_FRAG | 1583 MVGBE_TX_IP_HEADER_LEN(iphdr_unitlen); /* unit is 4B */ 1584 } 1585 if (txmap->dm_nsegs == 1) 1586 f->cmdsts = cmdsts | 1587 MVGBE_BUFFER_OWNED_BY_DMA | 1588 MVGBE_TX_GENERATE_CRC | 1589 MVGBE_TX_ENABLE_INTERRUPT | 1590 MVGBE_TX_ZERO_PADDING | 1591 MVGBE_TX_FIRST_DESC | 1592 MVGBE_TX_LAST_DESC; 1593 else { 1594 f = &sc->sc_rdata->mvgbe_tx_ring[first]; 1595 f->cmdsts = cmdsts | 1596 MVGBE_BUFFER_OWNED_BY_DMA | 1597 MVGBE_TX_GENERATE_CRC | 1598 MVGBE_TX_FIRST_DESC; 1599 1600 f = &sc->sc_rdata->mvgbe_tx_ring[last]; 1601 f->cmdsts = 1602 MVGBE_BUFFER_OWNED_BY_DMA | 1603 MVGBE_TX_ENABLE_INTERRUPT | 1604 MVGBE_TX_ZERO_PADDING | 1605 MVGBE_TX_LAST_DESC; 1606 } 1607 1608 sc->sc_cdata.mvgbe_tx_chain[last].mvgbe_mbuf = m_head; 1609 SIMPLEQ_REMOVE_HEAD(&sc->sc_txmap_head, link); 1610 sc->sc_cdata.mvgbe_tx_map[last] = entry; 1611 1612 /* Sync descriptors before handing to chip */ 1613 MVGBE_CDTXSYNC(sc, *txidx, txmap->dm_nsegs, 1614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1615 1616 sc->sc_cdata.mvgbe_tx_cnt += i; 1617 *txidx = current; 1618 1619 DPRINTFN(3, ("mvgbe_encap: completed successfully\n")); 1620 1621 return 0; 1622 } 1623 1624 static void 1625 mvgbe_rxeof(struct mvgbe_softc *sc) 1626 { 1627 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1628 struct mvgbe_rx_desc *cur_rx; 1629 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1630 struct mbuf *m; 1631 bus_dmamap_t dmamap; 1632 uint32_t rxstat; 1633 int idx, cur, total_len; 1634 1635 idx = sc->sc_cdata.mvgbe_rx_prod; 1636 1637 DPRINTFN(3, ("mvgbe_rxeof %d\n", idx)); 1638 1639 for (;;) { 1640 cur = idx; 1641 1642 /* Sync the descriptor */ 1643 MVGBE_CDRXSYNC(sc, idx, 1644 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1645 1646 cur_rx = &sc->sc_rdata->mvgbe_rx_ring[idx]; 1647 1648 if ((cur_rx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1649 MVGBE_BUFFER_OWNED_BY_DMA) { 1650 /* Invalidate the descriptor -- it's not ready yet */ 1651 MVGBE_CDRXSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1652 sc->sc_cdata.mvgbe_rx_prod = idx; 1653 break; 1654 } 1655 #ifdef DIAGNOSTIC 1656 if ((cur_rx->cmdsts & 1657 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) != 1658 (MVGBE_RX_LAST_DESC | MVGBE_RX_FIRST_DESC)) 1659 panic( 1660 "mvgbe_rxeof: buffer size is smaller than packet"); 1661 #endif 1662 1663 dmamap = sc->sc_cdata.mvgbe_rx_jumbo_map; 1664 1665 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1666 BUS_DMASYNC_POSTREAD); 1667 1668 m = cdata->mvgbe_rx_chain[idx].mvgbe_mbuf; 1669 cdata->mvgbe_rx_chain[idx].mvgbe_mbuf = NULL; 1670 total_len = cur_rx->bytecnt; 1671 rxstat = cur_rx->cmdsts; 1672 1673 cdata->mvgbe_rx_map[idx] = NULL; 1674 1675 idx = MVGBE_RX_RING_NEXT(idx); 1676 1677 if (rxstat & MVGBE_ERROR_SUMMARY) { 1678 #if 0 1679 int err = rxstat & MVGBE_RX_ERROR_CODE_MASK; 1680 1681 if (err == MVGBE_RX_CRC_ERROR) 1682 ifp->if_ierrors++; 1683 if (err == MVGBE_RX_OVERRUN_ERROR) 1684 ifp->if_ierrors++; 1685 if (err == MVGBE_RX_MAX_FRAME_LEN_ERROR) 1686 ifp->if_ierrors++; 1687 if (err == MVGBE_RX_RESOURCE_ERROR) 1688 ifp->if_ierrors++; 1689 #else 1690 ifp->if_ierrors++; 1691 #endif 1692 mvgbe_newbuf(sc, cur, m, dmamap); 1693 continue; 1694 } 1695 1696 if (total_len <= MVGBE_RX_CSUM_MIN_BYTE) /* XXX documented? */ 1697 goto sw_csum; 1698 1699 if (rxstat & MVGBE_RX_IP_FRAME_TYPE) { 1700 /* Check IPv4 header checksum */ 1701 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1702 if (!(rxstat & MVGBE_RX_IP_HEADER_OK)) 1703 m->m_pkthdr.csum_flags |= 1704 M_CSUM_IPv4_BAD; 1705 /* Check TCPv4/UDPv4 checksum */ 1706 if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1707 MVGBE_RX_L4_TYPE_TCP) 1708 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1709 else if ((rxstat & MVGBE_RX_L4_TYPE_MASK) == 1710 MVGBE_RX_L4_TYPE_UDP) 1711 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1712 if (!(rxstat & MVGBE_RX_L4_CHECKSUM)) 1713 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1714 } 1715 sw_csum: 1716 1717 /* 1718 * Try to allocate a new jumbo buffer. If that 1719 * fails, copy the packet to mbufs and put the 1720 * jumbo buffer back in the ring so it can be 1721 * re-used. If allocating mbufs fails, then we 1722 * have to drop the packet. 1723 */ 1724 if (mvgbe_newbuf(sc, cur, NULL, dmamap) == ENOBUFS) { 1725 struct mbuf *m0; 1726 1727 m0 = m_devget(mtod(m, char *), total_len, 0, ifp, NULL); 1728 mvgbe_newbuf(sc, cur, m, dmamap); 1729 if (m0 == NULL) { 1730 aprint_error_ifnet(ifp, 1731 "no receive buffers available --" 1732 " packet dropped!\n"); 1733 ifp->if_ierrors++; 1734 continue; 1735 } 1736 m = m0; 1737 } else { 1738 m->m_pkthdr.rcvif = ifp; 1739 m->m_pkthdr.len = m->m_len = total_len; 1740 } 1741 1742 /* Skip on first 2byte (HW header) */ 1743 m_adj(m, MVGBE_HWHEADER_SIZE); 1744 m->m_flags |= M_HASFCS; 1745 1746 ifp->if_ipackets++; 1747 1748 if (ifp->if_bpf) 1749 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1750 1751 /* pass it on. */ 1752 (*ifp->if_input)(ifp, m); 1753 } 1754 } 1755 1756 static void 1757 mvgbe_txeof(struct mvgbe_softc *sc) 1758 { 1759 struct mvgbe_chain_data *cdata = &sc->sc_cdata; 1760 struct mvgbe_tx_desc *cur_tx; 1761 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1762 struct mvgbe_txmap_entry *entry; 1763 int idx; 1764 1765 DPRINTFN(3, ("mvgbe_txeof\n")); 1766 1767 /* 1768 * Go through our tx ring and free mbufs for those 1769 * frames that have been sent. 1770 */ 1771 idx = cdata->mvgbe_tx_cons; 1772 while (idx != cdata->mvgbe_tx_prod) { 1773 MVGBE_CDTXSYNC(sc, idx, 1, 1774 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1775 1776 cur_tx = &sc->sc_rdata->mvgbe_tx_ring[idx]; 1777 #ifdef MVGBE_DEBUG 1778 if (mvgbe_debug >= 3) 1779 mvgbe_dump_txdesc(cur_tx, idx); 1780 #endif 1781 if ((cur_tx->cmdsts & MVGBE_BUFFER_OWNED_MASK) == 1782 MVGBE_BUFFER_OWNED_BY_DMA) { 1783 MVGBE_CDTXSYNC(sc, idx, 1, BUS_DMASYNC_PREREAD); 1784 break; 1785 } 1786 if (cur_tx->cmdsts & MVGBE_TX_LAST_DESC) 1787 ifp->if_opackets++; 1788 if (cur_tx->cmdsts & MVGBE_ERROR_SUMMARY) { 1789 int err = cur_tx->cmdsts & MVGBE_TX_ERROR_CODE_MASK; 1790 1791 if (err == MVGBE_TX_LATE_COLLISION_ERROR) 1792 ifp->if_collisions++; 1793 if (err == MVGBE_TX_UNDERRUN_ERROR) 1794 ifp->if_oerrors++; 1795 if (err == MVGBE_TX_EXCESSIVE_COLLISION_ERRO) 1796 ifp->if_collisions++; 1797 } 1798 if (cdata->mvgbe_tx_chain[idx].mvgbe_mbuf != NULL) { 1799 entry = cdata->mvgbe_tx_map[idx]; 1800 1801 m_freem(cdata->mvgbe_tx_chain[idx].mvgbe_mbuf); 1802 cdata->mvgbe_tx_chain[idx].mvgbe_mbuf = NULL; 1803 1804 bus_dmamap_sync(sc->sc_dmat, entry->dmamap, 0, 1805 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1806 1807 bus_dmamap_unload(sc->sc_dmat, entry->dmamap); 1808 SIMPLEQ_INSERT_TAIL(&sc->sc_txmap_head, entry, link); 1809 cdata->mvgbe_tx_map[idx] = NULL; 1810 } 1811 cdata->mvgbe_tx_cnt--; 1812 idx = MVGBE_TX_RING_NEXT(idx); 1813 } 1814 if (cdata->mvgbe_tx_cnt == 0) 1815 ifp->if_timer = 0; 1816 1817 if (cdata->mvgbe_tx_cnt < MVGBE_TX_RING_CNT - 2) 1818 ifp->if_flags &= ~IFF_OACTIVE; 1819 1820 cdata->mvgbe_tx_cons = idx; 1821 } 1822 1823 static uint8_t 1824 mvgbe_crc8(const uint8_t *data, size_t size) 1825 { 1826 int bit; 1827 uint8_t byte; 1828 uint8_t crc = 0; 1829 const uint8_t poly = 0x07; 1830 1831 while(size--) 1832 for (byte = *data++, bit = NBBY-1; bit >= 0; bit--) 1833 crc = (crc << 1) ^ ((((crc >> 7) ^ (byte >> bit)) & 1) ? poly : 0); 1834 1835 return crc; 1836 } 1837 1838 CTASSERT(MVGBE_NDFSMT == MVGBE_NDFOMT); 1839 1840 static void 1841 mvgbe_filter_setup(struct mvgbe_softc *sc) 1842 { 1843 struct ethercom *ec = &sc->sc_ethercom; 1844 struct ifnet *ifp= &sc->sc_ethercom.ec_if; 1845 struct ether_multi *enm; 1846 struct ether_multistep step; 1847 uint32_t *dfut, *dfsmt, *dfomt; 1848 uint32_t pxc; 1849 int i; 1850 const uint8_t special[ETHER_ADDR_LEN] = {0x01,0x00,0x5e,0x00,0x00,0x00}; 1851 1852 dfut = kmem_zalloc(sizeof(*dfut) * MVGBE_NDFUT, KM_SLEEP); 1853 dfsmt = kmem_zalloc(sizeof(*dfsmt) * MVGBE_NDFSMT, KM_SLEEP); 1854 dfomt = kmem_zalloc(sizeof(*dfomt) * MVGBE_NDFOMT, KM_SLEEP); 1855 1856 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1857 goto allmulti; 1858 } 1859 1860 ETHER_FIRST_MULTI(step, ec, enm); 1861 while (enm != NULL) { 1862 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1863 /* ranges are complex and somewhat rare */ 1864 goto allmulti; 1865 } 1866 /* chip handles some IPv4 multicast specially */ 1867 if (memcmp(enm->enm_addrlo, special, 5) == 0) { 1868 i = enm->enm_addrlo[5]; 1869 dfsmt[i>>2] = 1870 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1871 } else { 1872 i = mvgbe_crc8(enm->enm_addrlo, ETHER_ADDR_LEN); 1873 dfomt[i>>2] = 1874 MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1875 } 1876 1877 ETHER_NEXT_MULTI(step, enm); 1878 } 1879 goto set; 1880 1881 allmulti: 1882 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 1883 for (i = 0; i < MVGBE_NDFSMT; i++) { 1884 dfsmt[i] = dfomt[i] = 1885 MVGBE_DF(0, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1886 MVGBE_DF(1, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1887 MVGBE_DF(2, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS) | 1888 MVGBE_DF(3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1889 } 1890 } 1891 1892 set: 1893 pxc = MVGBE_READ(sc, MVGBE_PXC); 1894 pxc &= ~MVGBE_PXC_UPM; 1895 pxc |= MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP; 1896 if (ifp->if_flags & IFF_BROADCAST) { 1897 pxc &= ~(MVGBE_PXC_RB | MVGBE_PXC_RBIP | MVGBE_PXC_RBARP); 1898 } 1899 if (ifp->if_flags & IFF_PROMISC) { 1900 pxc |= MVGBE_PXC_UPM; 1901 } 1902 MVGBE_WRITE(sc, MVGBE_PXC, pxc); 1903 1904 /* Set Destination Address Filter Unicast Table */ 1905 i = sc->sc_enaddr[5] & 0xf; /* last nibble */ 1906 dfut[i>>2] = MVGBE_DF(i&3, MVGBE_DF_QUEUE(0) | MVGBE_DF_PASS); 1907 MVGBE_WRITE_FILTER(sc, MVGBE_DFUT, dfut, MVGBE_NDFUT); 1908 1909 /* Set Destination Address Filter Multicast Tables */ 1910 MVGBE_WRITE_FILTER(sc, MVGBE_DFSMT, dfsmt, MVGBE_NDFSMT); 1911 MVGBE_WRITE_FILTER(sc, MVGBE_DFOMT, dfomt, MVGBE_NDFOMT); 1912 1913 kmem_free(dfut, sizeof(dfut[0]) * MVGBE_NDFUT); 1914 kmem_free(dfsmt, sizeof(dfsmt[0]) * MVGBE_NDFSMT); 1915 kmem_free(dfomt, sizeof(dfsmt[0]) * MVGBE_NDFOMT); 1916 } 1917 1918 #ifdef MVGBE_DEBUG 1919 static void 1920 mvgbe_dump_txdesc(struct mvgbe_tx_desc *desc, int idx) 1921 { 1922 #define DESC_PRINT(X) \ 1923 if (X) \ 1924 printf("txdesc[%d]." #X "=%#x\n", idx, X); 1925 1926 #if BYTE_ORDER == BIG_ENDIAN 1927 DESC_PRINT(desc->bytecnt); 1928 DESC_PRINT(desc->l4ichk); 1929 DESC_PRINT(desc->cmdsts); 1930 DESC_PRINT(desc->nextdescptr); 1931 DESC_PRINT(desc->bufptr); 1932 #else /* LITTLE_ENDIAN */ 1933 DESC_PRINT(desc->cmdsts); 1934 DESC_PRINT(desc->l4ichk); 1935 DESC_PRINT(desc->bytecnt); 1936 DESC_PRINT(desc->bufptr); 1937 DESC_PRINT(desc->nextdescptr); 1938 #endif 1939 #undef DESC_PRINT 1940 } 1941 #endif 1942
Indexes created Wed Oct 01 13:09:50 GMT 2025